CN204556739U - A kind of electromagnet comprehensive parameter tester circuit - Google Patents
A kind of electromagnet comprehensive parameter tester circuit Download PDFInfo
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- CN204556739U CN204556739U CN201420856121.1U CN201420856121U CN204556739U CN 204556739 U CN204556739 U CN 204556739U CN 201420856121 U CN201420856121 U CN 201420856121U CN 204556739 U CN204556739 U CN 204556739U
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Abstract
The utility model discloses a kind of electromagnet comprehensive parameter tester circuit, comprising: clock circuit, AD signal sampling treatment circuit, DA signal processing circuit, LCD display driver circuit, function button circuit, motion detector circuit, communication interface circuit and CPU; Described CPU connects clock circuit, AD signal sampling treatment circuit, DA signal processing circuit, LCD display driver circuit, keyboard interface circuit, motion detector circuit and communication interface circuit respectively.The utility model only needs operating personnel tested electromagnet and test interface to be connected, start-up performance arranges fast inspection in button module or essence inspection button, the utility model carries out various parameter testing according to the program of setting in advance to tested electromagnet, operating personnel are without the need to possessing professional knowledge, and detection speed is fast, and detection efficiency is high, except testing single electromagnet, the utility model is also applicable to the production in enormous quantities of streamline, thus increases work efficiency while ensuring the quality of products.
Description
Technical field
The utility model relates to electromagnet comprehensive parameter tester, is specifically related to a kind of electromagnet comprehensive parameter tester circuit.
Background technology
Current existing electromagnet testing synthesis parameter device, its technology mainly adopts adjustable DC source of stable pressure to measure, stabilized voltage supply is applied at tested electromagnet excitation input end, manual adjustments voltage slowly rises from 0V, until hear that the sound of armature movement stops the adjustment of voltage, electromagnet secondary action voltage is measured by the method, due to complicated operation, professional must be had to detect, cause test link loaded down with trivial details, work efficiency is extremely low, very difficult for large batch of electromagnet production testing.
Summary of the invention
It is short, simple to operate that the purpose of this utility model is to provide a kind of test duration, and reliability is high, the appliance circuit of the test electromagnet comprehensive parameters that can enhance productivity, to solve the ineffective situation that prior art level causes.
The technical scheme that the utility model adopts is: a kind of electromagnet comprehensive parameter tester circuit, comprising: clock circuit, AD signal sampling treatment circuit, DA signal processing circuit, LCD display driver circuit, function button circuit, motion detector circuit, communication interface circuit and CPU; Described CPU connects clock circuit, AD signal sampling treatment circuit, DA signal processing circuit, LCD display driver circuit, keyboard interface circuit, motion detector circuit and communication interface circuit respectively.
Further, described clock circuit comprises crystal oscillator Y1, electric capacity C29 and electric capacity C30; Described crystal oscillator Y1 connects electric capacity C29 and electric capacity C30 respectively; Described electric capacity C29 is connected ground respectively with electric capacity C30.
Further, described AD signal sampling treatment circuit comprises A/D conversion chip U32, electric capacity C23, electric capacity C37, electric capacity C38, electric capacity C39, electric capacity C40, electric capacity C24, electric capacity C42, voltage source chip U33, resistance R90, resistance R91, resistance R92, resistance R93, resistance R88, resistance R89, stabilivolt D44 and stabilivolt D45; 12 pin of described A/D conversion chip U32, the 14 pin, the 15 pin and the 16 pin connect described CPU respectively; Described electric capacity C37, electric capacity C38, electric capacity C39, electric capacity C40 one end connect second pin of A/D conversion chip U32, three-prong, the 4th pin and the 5th pin respectively, and the other end of these four electric capacity connects ground MGND respectively; Described electric capacity C23 one end connects power supply VCC, and the other end connects A/D conversion chip U32 the 11 pin; Described electric capacity C24, electric capacity C42, voltage source chip U33 and resistance R88 one end connect the octal of A/D conversion chip U32 respectively, and the other end connects ground MGND respectively; Described voltage source chip U33 contact resistance R88; Described resistance R89 one end connects the octal of A/D conversion chip U32, and the other end connects+6V power supply; Described stabilivolt D44 and stabilivolt D45 one end are connected three-prong and second pin of A/D conversion chip U32 respectively, and the other end connects ground MGND respectively; Described resistance R90, resistance R91, resistance R92, resistance R93 one end connect A/D conversion chip U32 second pin, three-prong, the 4th pin and the 5th pin respectively, and the other end is interface channel 0, passage 1, passage 2 and passage 3 respectively.
Further, described DA signal processing circuit comprises D/A conversion chip U26, electric capacity C32, electric capacity C33, resistance R65, electric capacity C17, electric capacity C41, resistance R64, potentiometer R87 and power module U27; First pin of described D/A conversion chip U26, crus secunda, tripod and the 4th pin connect CPU respectively; The octal of described D/A conversion chip U26 connects power supply VCC and electric capacity C32 respectively; The other end of described electric capacity C32 connects ground; Described electric capacity C33 one end contact resistance R65, the other end connects ground; The described resistance R65 other end connects the 7th pin of D/A conversion chip U26; 5th pin of described D/A conversion chip U26 connects ground; The crus secunda of the 6th pin of described D/A conversion chip U26 respectively contact resistance R64, electric capacity C17, electric capacity C41 and power module U27; The tripod of described power module U27 connects electric capacity C17, electric capacity C41 and ground respectively; First pin of described power module U27 connects potentiometer R87; Described resistance R64 one end connects the crus secunda of power module U27, and the other end connects+6V power supply.
Further, described LCD display driver circuit comprise LCD interface J4, potentiometer W5, impact damper U6 and with door U3B; 5th pin to the 12 pin of described LCD interface J4 connects the 12 pin of impact damper U6 to the 19 pin, respectively as FPDP DATA0 to DATA7; First pin and the tripod of described LCD interface J4 are connected ground respectively; The crus secunda of described LCD interface J4 is connected power supply VCC respectively with the 4th pin; Tenth tripod of LCD interface J4 is connected CPU respectively with the 14 pin; 17 pin of described LCD interface J4 is connected potentiometer W5 respectively with the tenth octal; The other end of described potentiometer W5 connects ground; Described the 4th pin with door U3B and the 5th pin are connected CPU respectively, and the 6th pin connects the 11 pin of impact damper U6; The crus secunda of described impact damper U6 connects CPU respectively to the 9th pin; First pin of described impact damper U6 connects ground.
Further, described keyboard interface circuit comprises diode D32, diode D33, diode D34, diode D35, diode D36, diode D37, diode D38, diode D39, diode D23 and keyboard interface J5; Described diode D32, diode D33, diode D34, diode D35, diode D36, diode D37, diode D38, diode D39 positive pole connect CPU respectively, and negative pole connects keyboard interface J5 respectively.
Further, described motion detector circuit comprises resistance R81, field effect transistor W12, voltage stabilizing diode D48, resistance R54, resistance R55, potentiometer W15, amplifier U30, electric capacity C51, resistance R72, resistance R56, electric capacity C25, resistance R57, potentiometer W14, amplifier U34, diode D49, resistance R58, resistance R9, voltage stabilizing diode D46 and not gate U10C; Described field effect transistor W12 grid connects CPU; Described voltage stabilizing diode D48 positive pole connects field effect transistor W12 source electrode; Described field effect transistor W12 source electrode connects ground 50VGND; Described voltage stabilizing diode D48 negative pole connects field effect transistor W12 drain electrode; Described resistance R81 one end connects field effect transistor W12 drain electrode, and the other end connects output terminal and resistance R55 respectively; The described resistance R55 other end connects amplifier U30 forward end; Described resistance R54 one end ground connection, the other end connects amplifier U30 backward end; Described amplifier U30 the 4th pin connects-6V power supply, and the 7th pin connects+6V power supply; Described potentiometer W15 is connected across between amplifier U30 backward end and output terminal; Described electric capacity C51 one end connects amplifier U30 output terminal, and the other end is contact resistance R72 and resistance R56 respectively; Described amplifier U34 backward end connects potentiometer W14, resistance R56 and electric capacity C25, amplifier U34 forward end contact resistance R57 respectively; The described resistance R57 other end is contact resistance R72, electric capacity C25 and ground MGND respectively; Described amplifier U34 output terminal connects the positive pole of potentiometer W14 and diode D49 respectively; Described resistance R58 one end connects diode D49 negative pole, the 5th pin of other end difference contact resistance R9, voltage stabilizing diode D46 negative pole and not gate U10C; Described voltage stabilizing diode D46 positive pole is contact resistance R9 and ground MGND respectively; 6th pin of described not gate U10C connects CPU.
Further, described communication interface circuit comprises 232 chip U22,485 chip U31, communication interface J11, electric capacity C45, electric capacity C46, electric capacity C47, electric capacity C48, electric capacity C49, resistance R70, resistance R71 and resistance R86; Described 232 chip U22 the 11 pin connect CPU and 485 chip U31 the 4th pin respectively; Described 232 chip U22 the 12 pin connect CPU and 485 chip U31 first pin respectively; Described electric capacity C45 is connected across between 232 chip first pin and tripod; Described electric capacity C46 is connected across between 232 chips the 4th pin and the 5th pin; Described 232 chip U22 the tenth tripods are connected communication interface J11 respectively with 14 pin; Described 232 chip U22 the 16 pin connect power supply VCC and electric capacity C49 respectively; Described electric capacity C47 one end connects power supply VCC, and the other end connects 232 chip U22 crus secundas; Described electric capacity C47 one end connects power supply ground, and the other end connects 232 chip U22 the 6th pin; Described 232 chip U22 the 15 pin connect ground; Described 485 chip U31 crus secundas are connected CPU respectively with tripod; Described 485 chip U31 the 5th pin connect respectively with resistance R71; Described 485 chip U31 the 6th pin contact resistance R86 and communication interface J11 respectively; Described resistance R70 connects power supply VCC, 485 chip U31 the 7th pin and resistance R86 respectively.
The utility model has the following advantages with prior art tool of comparing: 1. reasonable in design, 2. test function is complete, 3. simple to operate.4 test speeds are fast.
Except object described above, feature and advantage, the utility model also has other object, feature and advantage.Below with reference to figure, the utility model is described in further detail.
Accompanying drawing explanation
The accompanying drawing forming a application's part is used to provide further understanding of the present utility model, and schematic description and description of the present utility model, for explaining the utility model, is not formed improper restriction of the present utility model.
Fig. 1 is a kind of electromagnet comprehensive parameter tester circuit theory diagrams of the utility model embodiment;
Fig. 2 is the communication interface circuit schematic diagram of the utility model embodiment;
Fig. 3 is the LCD interface of the utility model embodiment and the catenation principle figure of data bus.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the utility model, and be not used in restriction the utility model.
With reference to figure 1, a kind of electromagnet comprehensive parameter tester circuit as shown in Figure 1, comprising: clock circuit, AD signal sampling treatment circuit, DA signal processing circuit, LCD display driver circuit, function button circuit, motion detector circuit, communication interface circuit and CPU; Described CPU connects clock circuit, AD signal sampling treatment circuit, DA signal processing circuit, LCD display driver circuit, keyboard interface circuit, motion detector circuit and communication interface circuit respectively.
Described clock circuit comprises crystal oscillator Y1, electric capacity C29 and electric capacity C30; Described crystal oscillator Y1 connects electric capacity C29 and electric capacity C30 respectively; Described electric capacity C29 is connected ground respectively with electric capacity C30.
Described AD signal sampling treatment circuit comprises A/D conversion chip U32, electric capacity C23, electric capacity C37, electric capacity C38, electric capacity C39, electric capacity C40, electric capacity C24, electric capacity C42, voltage source chip U33, resistance R90, resistance R91, resistance R92, resistance R93, resistance R88, resistance R89, stabilivolt D44 and stabilivolt D45; 12 pin of described A/D conversion chip U32, the 14 pin, the 15 pin and the 16 pin connect described CPU respectively; Described electric capacity C37, electric capacity C38, electric capacity C39, electric capacity C40 one end connect second pin of A/D conversion chip U32, three-prong, the 4th pin and the 5th pin respectively, and the other end of these four electric capacity connects ground MGND respectively; Described electric capacity C23 one end connects power supply VCC, and the other end connects A/D conversion chip U32 the 11 pin; Described electric capacity C24, electric capacity C42, voltage source chip U33 and resistance R88 one end connect the octal of A/D conversion chip U32 respectively, and the other end connects ground MGND respectively; Described voltage source chip U33 contact resistance R88; Described resistance R89 one end connects the octal of A/D conversion chip U32, and the other end connects+6V power supply; Described stabilivolt D44 and stabilivolt D45 one end are connected three-prong and second pin of A/D conversion chip U32 respectively, and the other end connects ground MGND respectively; Described resistance R90, resistance R91, resistance R92, resistance R93 one end connect A/D conversion chip U32 second pin, three-prong, the 4th pin and the 5th pin respectively, and the other end is interface channel 0, passage 1, passage 2 and passage 3 respectively.
Described DA signal processing circuit comprises D/A conversion chip U26, electric capacity C32, electric capacity C33, resistance R65, electric capacity C17, electric capacity C41, resistance R64, potentiometer R87 and power module U27; First pin of described D/A conversion chip U26, crus secunda, tripod level the 4th pin connect CPU respectively; The octal of described D/A conversion chip U26 connects power supply VCC and electric capacity C32 respectively; The other end of described electric capacity C32 connects ground; Described electric capacity C33 one end contact resistance R65, the other end connects ground; The described resistance R65 other end connects the 7th pin of D/A conversion chip U26; 5th pin of described D/A conversion chip U26 connects ground; The crus secunda of the 6th pin of described D/A conversion chip U26 respectively contact resistance R64, electric capacity C17, electric capacity C41 and power module U27; The tripod of described power module U27 connects electric capacity C17, electric capacity C41 and ground respectively; First pin of described power module U27 connects potentiometer R87; Described resistance R64 one end connects the crus secunda of power module U27, and the other end connects+6V power supply.
Described LCD display driver circuit comprise LCD interface J4, potentiometer W5, impact damper U6 and with door U3B; 5th pin to the 12 pin of described LCD interface J4 connects the 12 pin of impact damper U6 to the 19 pin, respectively as FPDP DATA0 to DATA7; First pin and the tripod of described LCD interface J4 are connected ground respectively; The crus secunda of described LCD interface J4 is connected power supply VCC respectively with the 4th pin; Tenth tripod of LCD interface J4 is connected CPU respectively with the 14 pin; 17 pin of described LCD interface J4 is connected potentiometer W5 respectively with the tenth octal; The other end of described potentiometer W5 connects ground; Described the 4th pin with door U3B and the 5th pin are connected CPU respectively, and the 6th pin connects the 11 pin of impact damper U6; The crus secunda of described impact damper U6 connects CPU respectively to the 9th pin; First pin of described impact damper U6 connects ground.
Described keyboard interface circuit comprises diode D32, diode D33, diode D34, diode D35, diode D36, diode D37, diode D38, diode D39, diode D23 and keyboard interface J5; Described diode D32, diode D33, diode D34, diode D35, diode D36, diode D37, diode D38, diode D39 positive pole connect CPU respectively, and negative pole connects keyboard interface J5 respectively.
Described motion detector circuit comprises resistance R81, field effect transistor W12, voltage stabilizing diode D48, resistance R54, resistance R55, potentiometer W15, amplifier U30, electric capacity C51, resistance R72, resistance R56, electric capacity C25, resistance R57, potentiometer W14, amplifier U34, diode D49, resistance R58, resistance R9, voltage stabilizing diode D46 and not gate U10C; Described field effect transistor W12 grid connects CPU; Described voltage stabilizing diode D48 positive pole connects field effect transistor W12 source electrode; Described field effect transistor W12 source electrode connects ground 50VGND; Described voltage stabilizing diode D48 negative pole connects field effect transistor W12 drain electrode; Described resistance R81 one end connects field effect transistor W12 drain electrode, and the other end connects output terminal and resistance R55 respectively; The described resistance R55 other end connects amplifier U30 forward end; Described resistance R54 one end ground connection, the other end connects amplifier U30 backward end; Described amplifier U30 the 4th pin connects-6V power supply, and the 7th pin connects+6V power supply; Described potentiometer W15 is connected across between amplifier U30 backward end and output terminal; Described electric capacity C51 one end connects amplifier U30 output terminal, and the other end is contact resistance R72 and resistance R56 respectively; Described amplifier U34 backward end connects potentiometer W14, resistance R56 and electric capacity C25, amplifier U34 forward end contact resistance R57 respectively; The described resistance R57 other end is contact resistance R72, electric capacity C25 and ground MGND respectively; Described amplifier U34 output terminal connects the positive pole of potentiometer W14 and diode D49 respectively; Described resistance R58 one end connects diode D49 negative pole, the 5th pin of other end difference contact resistance R9, voltage stabilizing diode D46 negative pole and not gate U10C; Described voltage stabilizing diode D46 positive pole is contact resistance R9 and ground MGND respectively; 6th pin of described not gate U10C connects CPU.
Described communication interface circuit comprises 232 chip U22,485 chip U31, communication interface J11, electric capacity C45, electric capacity C46, electric capacity C47, electric capacity C48, electric capacity C49, resistance R70, resistance R71 and resistance R86; Described 232 chip U22 the 11 pin connect CPU and 485 chip U31 the 4th pin respectively; Described 232 chip U22 the 12 pin connect CPU and 485 chip U31 first pin respectively; Described electric capacity C45 is connected across between 232 chip first pin and tripod; Described electric capacity C46 is connected across between 232 chips the 4th pin and the 5th pin; Described 232 chip U22 the tenth tripods are connected communication interface J11 respectively with 14 pin; Described 232 chip U22 the 16 pin connect power supply VCC and electric capacity C49 respectively; Described electric capacity C47 one end connects power supply VCC, and the other end connects 232 chip U22 crus secundas; Described electric capacity C47 one end connects power supply ground, and the other end connects 232 chip U22 the 6th pin; Described 232 chip U22 the 15 pin connect ground; Described 485 chip U31 crus secundas are connected CPU respectively with tripod; Described 485 chip U31 the 5th pin connect respectively with resistance R71; Described 485 chip U31 the 6th pin contact resistance R86 and communication interface J11 respectively; Described resistance R70 connects power supply VCC, 485 chip U31 the 7th pin and resistance R86 respectively.
The utility model clock frequency module is used for providing frequency of operation to CPU.
Test interface module is connected with each pin of electromagnet.
Motion detector circuit is for detecting the sudden change of tested electromagnet coil current.
The utility model only needs operating personnel tested electromagnet and test interface to be connected, start-up performance arranges fast inspection in button module or essence inspection button, the utility model carries out various parameter testing according to the program of setting in advance to tested electromagnet, operating personnel are without the need to possessing professional knowledge, and detection speed is fast, and detection efficiency is high, except testing single electromagnet, the utility model is also applicable to the production in enormous quantities of streamline, thus increases work efficiency while ensuring the quality of products.
The foregoing is only preferred embodiment of the present utility model, not in order to limit the utility model, all within spirit of the present utility model and principle, any amendment done, equivalent replacement, improvement etc., all should be included within protection domain of the present utility model.
Claims (8)
1. an electromagnet comprehensive parameter tester circuit, is characterized in that, comprising: clock circuit,
AD signal sampling treatment circuit, DA signal processing circuit, LCD display driver circuit, function button circuit, motion detector circuit, communication interface circuit and CPU; Described CPU connects clock circuit, AD signal sampling treatment circuit, DA signal processing circuit, LCD display driver circuit, keyboard interface circuit, motion detector circuit and communication interface circuit respectively.
2. electromagnet comprehensive parameter tester circuit according to claim 1, is characterized in that,
Described clock circuit comprises crystal oscillator Y1, electric capacity C29 and electric capacity C30; Described crystal oscillator Y1 connects electric capacity C29 and electric capacity C30 respectively; Described electric capacity C29 is connected ground respectively with electric capacity C30.
3. electromagnet comprehensive parameter tester circuit according to claim 1, is characterized in that,
Described AD signal sampling treatment circuit comprises A/D conversion chip U32, electric capacity C23, electric capacity C37, electric capacity C38, electric capacity C39, electric capacity C40, electric capacity C24, electric capacity C42, voltage source chip U33, resistance R90, resistance R91, resistance R92, resistance R93, resistance R88, resistance R89, stabilivolt D44 and stabilivolt D45; 12 pin of described A/D conversion chip U32, the 14 pin, the 15 pin and the 16 pin connect described CPU respectively; Described electric capacity C37, electric capacity C38, electric capacity C39, electric capacity C40 one end connect second pin of A/D conversion chip U32, three-prong, the 4th pin and the 5th pin respectively, and the other end of these four electric capacity connects ground MGND respectively; Described electric capacity C23 one end connects power supply VCC, and the other end connects A/D conversion chip U32 the 11 pin; Described electric capacity C24, electric capacity C42, voltage source chip U33 and resistance R88 one end connect the octal of A/D conversion chip U32 respectively, and the other end connects ground MGND respectively; Described voltage source chip U33 contact resistance R88; Described resistance R89 one end connects the octal of A/D conversion chip U32, and the other end connects+6V power supply; Described stabilivolt D44 and stabilivolt D45 one end are connected three-prong and second pin of A/D conversion chip U32 respectively, and the other end connects ground MGND respectively; Described resistance R90, resistance R91, resistance R92, resistance R93 one end connect A/D conversion chip U32 second pin, three-prong, the 4th pin and the 5th pin respectively, and the other end is interface channel 0, passage 1, passage 2 and passage 3 respectively.
4. electromagnet comprehensive parameter tester circuit according to claim 1, is characterized in that,
Described DA signal processing circuit comprises D/A conversion chip U26, electric capacity C32, electric capacity C33, resistance R65, electric capacity C17, electric capacity C41, resistance R64, potentiometer R87 and power module U27; First pin of described D/A conversion chip U26, crus secunda, tripod and the 4th pin connect CPU respectively; The octal of described D/A conversion chip U26 connects power supply VCC and electric capacity C32 respectively; The other end of described electric capacity C32 connects ground; Described electric capacity C33 one end contact resistance R65, the other end connects ground; The described resistance R65 other end connects the 7th pin of D/A conversion chip U26; 5th pin of described D/A conversion chip U26 connects ground; The crus secunda of the 6th pin of described D/A conversion chip U26 respectively contact resistance R64, electric capacity C17, electric capacity C41 and power module U27; The tripod of described power module U27 connects electric capacity C17, electric capacity C41 and ground respectively; First pin of described power module U27 connects potentiometer R87; Described resistance R64 one end connects the crus secunda of power module U27, and the other end connects+6V power supply.
5. electromagnet comprehensive parameter tester circuit according to claim 1, is characterized in that,
Described LCD display driver circuit comprise LCD interface J4, potentiometer W5, impact damper U6 and with door U3B; 5th pin to the 12 pin of described LCD interface J4 connects the 12 pin of impact damper U6 to the 19 pin, respectively as FPDP DATA0 to DATA7; First pin and the tripod of described LCD interface J4 are connected ground respectively; The crus secunda of described LCD interface J4 is connected power supply VCC respectively with the 4th pin; Tenth tripod of LCD interface J4 is connected CPU respectively with the 14 pin; 17 pin of described LCD interface J4 is connected potentiometer W5 respectively with the tenth octal; The other end of described potentiometer W5 connects ground; Described the 4th pin with door U3B and the 5th pin are connected CPU respectively, and the 6th pin connects the 11 pin of impact damper U6; The crus secunda of described impact damper U6 connects CPU respectively to the 9th pin; First pin of described impact damper U6 connects ground.
6. electromagnet comprehensive parameter tester circuit according to claim 1, is characterized in that,
Described keyboard interface circuit comprises diode D32, diode D33, diode D34, diode D35, diode D36, diode D37, diode D38, diode D39, diode D23 and keyboard interface J5; Described diode D32, diode D33, diode D34, diode D35, diode D36, diode D37, diode D38, diode D39 positive pole connect CPU respectively, and negative pole connects keyboard interface J5 respectively.
7. electromagnet comprehensive parameter tester circuit according to claim 1, is characterized in that,
Described motion detector circuit comprises resistance R81, field effect transistor W12, voltage stabilizing diode D48, resistance R54, resistance R55, potentiometer W15, amplifier U30, electric capacity C51, resistance R72, resistance R56, electric capacity C25, resistance R57, potentiometer W14, amplifier U34, diode D49, resistance R58, resistance R9, voltage stabilizing diode D46 and not gate U10C; Described field effect transistor W12 grid connects CPU; Described voltage stabilizing diode D48 positive pole connects field effect transistor W12 source electrode; Described field effect transistor W12 source electrode connects ground 50VGND; Described voltage stabilizing diode D48 negative pole connects field effect transistor W12 drain electrode; Described resistance R81 one end connects field effect transistor W12 drain electrode, and the other end connects output terminal and resistance R55 respectively; The described resistance R55 other end connects amplifier U30 forward end; Described resistance R54 one end ground connection, the other end connects amplifier U30 backward end; Described amplifier U30 the 4th pin connects-6V power supply, and the 7th pin connects+6V power supply; Described potentiometer W15 is connected across between amplifier U30 backward end and output terminal; Described electric capacity C51 one end connects amplifier U30 output terminal, and the other end is contact resistance R72 and resistance R56 respectively; Described amplifier U34 backward end connects potentiometer W14, resistance R56 and electric capacity C25, amplifier U34 forward end contact resistance R57 respectively; The described resistance R57 other end is contact resistance R72, electric capacity C25 and ground MGND respectively; Described amplifier U34 output terminal connects the positive pole of potentiometer W14 and diode D49 respectively; Described resistance R58 one end connects diode D49 negative pole, the 5th pin of other end difference contact resistance R9, voltage stabilizing diode D46 negative pole and not gate U10C; Described voltage stabilizing diode D46 positive pole is contact resistance R9 and ground MGND respectively; 6th pin of described not gate U10C connects CPU.
8. according to the arbitrary described electromagnet comprehensive parameter tester circuit of claim 1-7, its feature
Be, described communication interface circuit comprises 232 chip U22,485 chip U31, communication interface J11, electric capacity C45, electric capacity C46, electric capacity C47, electric capacity C48, electric capacity C49, resistance R70, resistance R71 and resistance R86; Described 232 chip U22 the 11 pin connect CPU and 485 chip U31 the 4th pin respectively; Described 232 chip U22 the 12 pin connect CPU and 485 chip U31 first pin respectively; Described electric capacity C45 is connected across between 232 chip first pin and tripod; Described electric capacity C46 is connected across between 232 chips the 4th pin and the 5th pin; Described 232 chip U22 the tenth tripods are connected communication interface J11 respectively with 14 pin; Described 232 chip U22 the 16 pin connect power supply VCC and electric capacity C49 respectively; Described electric capacity C47 one end connects power supply VCC, and the other end connects 232 chip U22 crus secundas; Described electric capacity C47 one end connects power supply ground, and the other end connects 232 chip U22 the 6th pin; Described 232 chip U22 the 15 pin connect ground; Described 485 chip U31 crus secundas are connected CPU respectively with tripod; Described 485 chip U31 the 5th pin connect respectively with resistance R71; Described 485 chip U31 the 6th pin contact resistance R86 and communication interface J11 respectively; Described resistance R70 connects power supply VCC, 485 chip U31 the 7th pin and resistance R86 respectively.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420856121.1U CN204556739U (en) | 2014-12-30 | 2014-12-30 | A kind of electromagnet comprehensive parameter tester circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420856121.1U CN204556739U (en) | 2014-12-30 | 2014-12-30 | A kind of electromagnet comprehensive parameter tester circuit |
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| CN204556739U true CN204556739U (en) | 2015-08-12 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110207690A (en) * | 2019-05-22 | 2019-09-06 | 南京理工大学 | A kind of AGV high-precision magnetic navigation sensor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110207690A (en) * | 2019-05-22 | 2019-09-06 | 南京理工大学 | A kind of AGV high-precision magnetic navigation sensor |
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