CN204538006U - The encapsulating structure of New Image process chip - Google Patents
The encapsulating structure of New Image process chip Download PDFInfo
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- CN204538006U CN204538006U CN201520110564.0U CN201520110564U CN204538006U CN 204538006 U CN204538006 U CN 204538006U CN 201520110564 U CN201520110564 U CN 201520110564U CN 204538006 U CN204538006 U CN 204538006U
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- image sensor
- sensor chip
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- supporting bracket
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
The utility model discloses a kind of encapsulating structure of New Image process chip, comprises image sensor chip, printed circuit supporting bracket, transparent cover plate and PCB substrate; Be positioned in the middle part of printed circuit supporting bracket medial surface and there is lug boss, the neighboring area of transparent cover plate contacts with lug boss, the edge area distribution of image sensor chip upper surface has several blind holes, the blind via bottom of image sensor chip has aluminium welding pad, is positioned at blind hole and has nickel dam, guard metal layer successively at aluminium welding pad upper surface; Metal conducting layer is electrically connected with the lug boss lower surface circuit of printed circuit supporting bracket by conducting resinl, described image sensor chip is between lug boss and PCB substrate, PCB substrate is electrically connected with being fitted by conducting resinl bottom printed circuit supporting bracket, and metal conducting layer conducts electricity layering and tin by copper from the bottom up and conducts electricity layering and superpose and form.It is better that the utility model heat shock resistance and steam impact expression effect, improves the optical property of module and and reduce production cost.
Description
Technical field
The utility model relates to a kind of image sensing device encapsulating structure, belongs to technical field of semiconductor encapsulation.
Background technology
Imageing sensor has been widely used in such as digital camera, in the digital devices such as camera phone.Image sensor module comprises the imageing sensor being converted to telecommunications breath for image information.Specifically, imageing sensor can comprise and photon can be converted to electronics with display and the semiconductor device of memory image.The example of imageing sensor comprises a little and coupled apparatus (CCD), complementary metal oxide silicon (CMOS) imageing sensor (CIS) etc.
A kind of packaged type of conventional images transducer makes box dam cavity on the glass substrate and upper bonding glue, wafer and glass substrate is bonded together, adopts silicon through hole and the technology of rerouting to complete the wafer-level packaging of chip, be finally cut to single crystal grain.But there is following technical problem:
The problem that this technology mainly solves is as follows:
(1), wafer factory make welding pad structure be aluminium material, thus wafer front photoetching developing process can to aluminum metal weld pad produce corrosion.This technology by aluminium welding pad chemical nickel plating, is protected aluminium welding pad after wafer supplied materials, avoids by alkaline development corrosion.
(2), use the special material protection wafer pixel region easily removed, guarantee that subsequent wafer front PROCESS FOR TREATMENT does not have an impact to pixel region;
(3), below wafer convex point, make one deck pressure stresses resilient coating, solve the low integrity problem of salient point.
(4), at wafer frontside aluminium solder joint place directly grow wafer convex point, greatly reduce line transmission distance, solve Signal transmissions instability problem;
(5) wafer convex point technology, is used to realize ultra fine-pitch encapsulation;
(6), use middle hollowed-out PCB, adopt flip-chip technology by chip and printed circuit board (PCB) welding, chip is embedded in printed circuit board (PCB), makes encapsulation module thickness thinner;
(7), PCB hollow part attaches IR sheet glass, plays and strengthens the effect of product optical property.
(8), this technology solves the product warpage issues that CSP processes high pixel, large-size images product sensor runs into.
(9), this technology simplifies product packaging technology flow process greatly, and eliminate dry etching in TSV technique, production efficiency is higher, and cost is lower.
Summary of the invention
The utility model object is to provide a kind of encapsulating structure of New Image process chip, the encapsulating structure of this New Image process chip adopts front to connect, silicon layer below metal pad is complete, support force is better than technique before, metal solder joint there will not be phenomenon of rupture, and it is better that the heat shock resistance of product and steam impact expression effect, and at wafer frontside aluminium solder joint, place directly grows wafer convex point, greatly reduce line transmission distance, Signal transmissions is more stable.
For achieving the above object, the technical solution adopted in the utility model is: a kind of encapsulating structure of New Image process chip, comprise image sensor chip, printed circuit supporting bracket, transparent cover plate and PCB substrate, described printed circuit supporting bracket center has vacancy section, described transparent cover plate is covered in vacancy section, and the upper surface of described image sensor chip has photosensitive area;
Be positioned in the middle part of described printed circuit supporting bracket medial surface and have lug boss, the neighboring area of described transparent cover plate contacts with lug boss, thus forms cavity between transparent cover plate and image sensor chip;
The edge area distribution of image sensor chip upper surface has several blind holes, the blind via bottom of described image sensor chip has aluminium welding pad, be positioned at blind hole and successively there is nickel dam at aluminium welding pad upper surface, guard metal layer, be positioned at described image sensor chip upper surface and at blind hole periphery, there is stress relief layer, described blind via bottom, side surface and stress relief layer upper surface have a titanium copper layer, metal conducting layer is filled with in described blind hole, described metallic conduction layer height higher than blind hole depth and extend to be positioned at directly over stress relief layer titanium copper layer surface, thus make metal conducting layer top cover the titanium copper layer segment region be positioned at directly over stress relief layer, described stress relief layer is the photoresist layer after development,
Described metal conducting layer is electrically connected with the lug boss lower surface circuit of printed circuit supporting bracket by conducting resinl, described image sensor chip is between lug boss and PCB substrate, described PCB substrate is electrically connected with being fitted by conducting resinl bottom printed circuit supporting bracket, and described metal conducting layer conducts electricity layering and tin by copper from the bottom up and conducts electricity layering and superpose and form.
In technique scheme, further improved plan is as follows:
1., in such scheme, described boss is in the middle part of printed circuit supporting bracket medial surface.
2., in such scheme, described guard metal layer is nickel-gold layer or nickel palladium layers.
Because technique scheme is used, the utility model compared with prior art has following advantages and effect:
1. the encapsulating structure of the utility model New Image process chip, it instead of TSV(silicon through hole) back side connected mode in technique, employing front connects, silicon layer below metal pad is complete, and support force is better than technique before, and metal solder joint there will not be phenomenon of rupture, it is better that the heat shock resistance of product and steam impact expression effect, at wafer frontside aluminium solder joint, place directly grows wafer convex point, and greatly reduce line transmission distance, Signal transmissions is more stable; Secondly, its metal conducting layer is superposed by copper conduction layering and the layering of tin conduction from the bottom up and forms, and is conducive to reducing contact resistance further, reduces the response time; Again, adopt printed circuit board and the flip-chip of center hollow out, greatly reduce the thickness of chip module, substantially increase the optical property of module and and reduce production cost.
2. the encapsulating structure of the utility model New Image process chip; the blind via bottom of its image sensor chip has aluminium welding pad; be positioned at blind hole and there is nickel dam, guard metal layer successively for the aluminum metal weld pad of wafer at aluminium welding pad upper surface; first weld pad protection is carried out; effectively prevent subsequent technique from affecting it, improve product reliability.
3. the encapsulating structure of the utility model New Image process chip, it is positioned at described image sensor chip upper surface and has stress relief layer at blind hole periphery, described stress relief layer is the photoresist layer after development, make stress-buffer layer bottom metal salient point, effectively improve the soldering reliability of metal salient point.
Accompanying drawing explanation
Accompanying drawing 1 is image sensor chip structural representation in the encapsulating structure of the utility model New Image process chip;
Accompanying drawing 2 is A place partial structurtes enlarged diagram in accompanying drawing 1;
Accompanying drawing 3 is the utility model printed circuit supporting plate structure enlarged diagram;
Accompanying drawing 4 is the encapsulating structure structural representation of the utility model New Image process chip.
In above accompanying drawing: 1, image sensor chip; 2, printed circuit supporting bracket; 3, transparent cover plate; 4, PCB substrate; 5, vacancy section; 6, photosensitive area; 7, lug boss; 8, cavity; 9, blind hole; 10, aluminium welding pad; 11, nickel dam; 12, guard metal layer; 13, stress relief layer; 14, titanium copper layer; 15, metal conducting layer; 151, copper conduction layering; 152, tin conduction layering; 16, conducting resinl; 17, v-depression.
Embodiment
Below in conjunction with embodiment, the utility model is further described:
Embodiment: a kind of encapsulating structure of New Image process chip, comprise image sensor chip 1, printed circuit supporting bracket 2, transparent cover plate 3 and PCB substrate 4, described printed circuit supporting bracket 2 center has vacancy section 5, described transparent cover plate 3 is covered in vacancy section 5, and the upper surface of described image sensor chip 1 has photosensitive area 6;
Be positioned in the middle part of described printed circuit supporting bracket 2 medial surface and have lug boss 7, the neighboring area of described transparent cover plate 3 contacts with lug boss 7, thus forms cavity 8 between transparent cover plate 3 and image sensor chip 1;
The edge area distribution of image sensor chip 1 upper surface has several blind holes 9, bottom the blind hole 9 of described image sensor chip 1, there is aluminium welding pad 10, be positioned at blind hole 9 and at aluminium welding pad 10 upper surface, there is nickel dam 11 successively, guard metal layer 12, be positioned at described image sensor chip 1 upper surface and at blind hole 9 periphery, there is stress relief layer 13, bottom described blind hole 9, side surface and stress relief layer upper surface have a titanium copper layer 14, metal conducting layer 15 is filled with in described blind hole 9, described metal conducting layer 15 height is higher than blind hole 9 degree of depth and extend to titanium copper layer 14 surface be positioned at directly over stress relief layer 13, thus make metal conducting layer 15 top cover titanium copper layer 14 subregion be positioned at directly over stress relief layer 13, described stress relief layer 13 is the photoresist layer after development,
Described metal conducting layer 15 is electrically connected with the lug boss 7 lower surface circuit of printed circuit supporting bracket 2 by conducting resinl 16, described image sensor chip 1 is between lug boss and PCB substrate 4, described PCB substrate 4 fit with bottom printed circuit supporting bracket 2 be electrically connected by conducting resinl 16, and described metal conducting layer 15 conducts electricity layering 151 and tin conduction layering 152 superposition by copper from the bottom up and forms.
Described lug boss 7 is positioned at the middle part of printed circuit supporting bracket 2 medial surface.
Above-mentioned guard metal layer 12 is nickel-gold layer or nickel palladium layers.
When adopting the encapsulating structure of above-mentioned New Image process chip, it instead of TSV(silicon through hole) back side connected mode in technique, employing front connects, silicon layer below metal pad is complete, and support force is better than technique before, and metal solder joint there will not be phenomenon of rupture, it is better that the heat shock resistance of product and steam impact expression effect, at wafer frontside aluminium solder joint, place directly grows wafer convex point, and greatly reduce line transmission distance, Signal transmissions is more stable; Secondly, its metal conducting layer is superposed by copper conduction layering and the layering of tin conduction from the bottom up and forms, and is conducive to reducing contact resistance further, reduces the response time; Again, adopt printed circuit board and the flip-chip of center hollow out, greatly reduce the thickness of chip module, substantially increase module optical property and and reduce production cost; Again, the blind via bottom of its image sensor chip has aluminium welding pad, is positioned at blind hole and has nickel dam, guard metal layer successively for the aluminum metal weld pad of wafer at aluminium welding pad upper surface, first carrying out weld pad protection, effectively prevent subsequent technique from affecting it, improve product reliability; Again, it is positioned at described image sensor chip upper surface and has stress relief layer at blind hole periphery, and described stress relief layer is the photoresist layer after development, makes stress-buffer layer bottom metal salient point, effectively improves the soldering reliability of metal salient point.
Above-described embodiment, only for technical conceive of the present utility model and feature are described, its object is to person skilled in the art can be understood content of the present utility model and implement according to this, can not limit protection range of the present utility model with this.All equivalences done according to the utility model Spirit Essence change or modify, and all should be encompassed within protection range of the present utility model.
Claims (3)
1. the encapsulating structure of a New Image process chip, it is characterized in that: comprise image sensor chip (1), printed circuit supporting bracket (2), transparent cover plate (3) and PCB substrate (4), described printed circuit supporting bracket (2) center has vacancy section (5), described transparent cover plate (3) is covered in vacancy section (5), and the upper surface of described image sensor chip (1) has photosensitive area (6);
Be positioned in the middle part of described printed circuit supporting bracket (2) medial surface and have lug boss (7), the neighboring area of described transparent cover plate (3) contacts with lug boss (7), thus forms cavity (8) between transparent cover plate (3) and image sensor chip (1);
The edge area distribution of image sensor chip (1) upper surface has several blind holes (9), blind hole (9) bottom of described image sensor chip (1) has aluminium welding pad (10), be positioned at blind hole (9) and at aluminium welding pad (10) upper surface, there is nickel dam (11) successively, guard metal layer (12), be positioned at described image sensor chip (1) upper surface and at blind hole (9) periphery, there is stress relief layer (13), described blind hole (9) bottom, side surface and stress relief layer upper surface have a titanium copper layer (14), metal conducting layer (15) is filled with in described blind hole (9), described metal conducting layer (15) height higher than blind hole (9) degree of depth and extend to be positioned at directly over stress relief layer (13) titanium copper layer (14) surface, thus make metal conducting layer (15) top cover titanium copper layer (14) subregion be positioned at directly over stress relief layer (13), described stress relief layer (13) is the photoresist layer after development,
Described metal conducting layer (15) is electrically connected with lug boss (7) the lower surface circuit of printed circuit supporting bracket (2) by conducting resinl (16), described image sensor chip (1) is positioned between lug boss and PCB substrate (4), fits be electrically connected by conducting resinls (16) in described PCB substrate (4) and printed circuit supporting bracket (2) bottom, described metal conducting layer (15) conducts electricity layering (151) and tin conduction layering (152) superposition by copper from the bottom up and forms.
2. the encapsulating structure of New Image process chip according to claim 1, is characterized in that: described lug boss (7) is positioned at the middle part of printed circuit supporting bracket (2) medial surface.
3. the encapsulating structure of New Image process chip according to claim 1, is characterized in that: described guard metal layer (12) is nickel-gold layer or nickel palladium layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520110564.0U CN204538006U (en) | 2015-02-15 | 2015-02-15 | The encapsulating structure of New Image process chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520110564.0U CN204538006U (en) | 2015-02-15 | 2015-02-15 | The encapsulating structure of New Image process chip |
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| CN204538006U true CN204538006U (en) | 2015-08-05 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109156079A (en) * | 2018-08-17 | 2019-01-04 | 深圳市汇顶科技股份有限公司 | Optical sensing mould group and preparation method thereof |
| CN113764373A (en) * | 2020-06-04 | 2021-12-07 | 安普林荷兰有限公司 | Molded air cavity package and device including the same |
-
2015
- 2015-02-15 CN CN201520110564.0U patent/CN204538006U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109156079A (en) * | 2018-08-17 | 2019-01-04 | 深圳市汇顶科技股份有限公司 | Optical sensing mould group and preparation method thereof |
| CN109156079B (en) * | 2018-08-17 | 2022-01-28 | 深圳市汇顶科技股份有限公司 | Optical sensing module and manufacturing method thereof |
| CN113764373A (en) * | 2020-06-04 | 2021-12-07 | 安普林荷兰有限公司 | Molded air cavity package and device including the same |
| CN113764373B (en) * | 2020-06-04 | 2024-03-05 | 安普林荷兰有限公司 | Molded air cavity package and device including the same |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 215143, No. 568, Fang Qiao Road, Lake Industrial Park, Xiangcheng Economic Development Zone, Jiangsu, Suzhou Patentee after: Suzhou Keyang Semiconductor Co., Ltd Address before: 215143, No. 568, Fang Qiao Road, Lake Industrial Park, Xiangcheng Economic Development Zone, Jiangsu, Suzhou Patentee before: SUZHOU KEYANG PHOTOELECTRIC TECHNOLOGY CO., LTD. |
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| CP01 | Change in the name or title of a patent holder |