CN204348707U - A kind of ultra-thin potted element - Google Patents
A kind of ultra-thin potted element Download PDFInfo
- Publication number
- CN204348707U CN204348707U CN201520003374.9U CN201520003374U CN204348707U CN 204348707 U CN204348707 U CN 204348707U CN 201520003374 U CN201520003374 U CN 201520003374U CN 204348707 U CN204348707 U CN 204348707U
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- CN
- China
- Prior art keywords
- salient point
- chip
- metal salient
- silver coating
- ultra
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model discloses a kind of ultra-thin potted element, comprise plastic-sealed body and be encapsulated in the chip in plastic-sealed body, metal salient point, silver coating, plating NiPdAu layer and copper articulamentum, chip, metal salient point, silver coating, copper articulamentum and plating NiPdAu layer constitute power supply and the signalling channel of circuit, described copper articulamentum has multiple, the upper surface of each copper articulamentum and lower surface are respectively arranged with silver coating and plating NiPdAu layer, described multiple silver coatings are separate, described chip soldering junction is provided with multiple metal salient point, chip is connected with multiple silver coating by metal salient point simultaneously, the utility model potted element will plate NiPdAu layer as the signal interface channel with external circuit, plating link can be saved, under the prerequisite that metal salient point arrangement and I/O number do not limit by Frame Design and making, achieve metal salient point arrangement can define arbitrarily, realize the interconnection of chip and carrier better.
Description
Technical field
The utility model belongs to integrated antenna package technical field, is specifically related to a kind of ultra-thin potted element.
Background technology
The QFN(Quad Flat No-leadPackage of integrated circuit, quad flat non-pin package) and DFN(Dual Flat Package, bilateral pin flat packaging) in recent years along with communication apparatus (as base station, switch), smart mobile phone, portable set (as panel computer), wearable device (as intelligent watch, intelligent glasses, Intelligent bracelet etc.) universal and developing rapidly, be specially adapted to the encapsulation of the large scale integrated circuit of the electrical requirements such as high frequency, high bandwidth, low noise, high heat conduction, small size, high speed.
QFN/DFN efficiently utilizes the encapsulated space of terminal pin, thus improves packaging efficiency significantly.This encapsulation due to go between short and small, plastic-sealed body size is little, packaging body is thin, can make CPU volume-diminished 30%-50%, has good heat dispersion simultaneously.
Traditional QFN/DFN mainly has the following disadvantages: one is that design and fabrication cycle are long, and cost compare is high; Two is restrictions that the arrangement of salient point and the dense degree of I/O are subject to Frame Design and frame manufacturing process; Three is frameworks after corrosion is thinning, has the risk of slip in mould, and package reliability can not get ensureing; Four is that traditional QFN/DFN product thickness is still larger, cannot meet the demand of current portable set to small size, high-density packages.
Utility model content
One of the purpose of this utility model is for above-mentioned the deficiencies in the prior art, a kind of ultra-thin potted element of exempting from pad pasting, exempting from plating connected based on Flip-chip.
The utility model solves the technical scheme that its technical problem adopts: a kind of ultra-thin potted element, comprise plastic-sealed body and be encapsulated in the chip in plastic-sealed body, metal salient point, silver coating, plating NiPdAu layer and copper articulamentum, chip, metal salient point, silver coating, copper articulamentum and plating NiPdAu layer constitute power supply and the signalling channel of circuit, described copper articulamentum has multiple, the upper surface of each copper articulamentum and lower surface are respectively arranged with silver coating and plating NiPdAu layer, described multiple silver coatings are separate, described chip soldering junction is provided with multiple metal salient point, chip is connected with multiple silver coating by metal salient point simultaneously.
Described a kind of ultra-thin potted element, the thickness of its silver coating and plating NiPdAu layer is 3-5um.
Described a kind of ultra-thin potted element, the thickness of its plastic-sealed body is less than 0.35mm.
Described a kind of ultra-thin potted element, one group of relative edge of its copper articulamentum lower end is provided with chamfering.
Described a kind of ultra-thin potted element, its chamfering is right angle chamfering.
The beneficial effects of the utility model are: potted element will plate NiPdAu layer as the signal interface channel with external circuit, be equivalent to " pin " of common encapsulation, plating link can be saved, under the prerequisite that metal salient point arrangement and I/O number do not limit by Frame Design and making, achieve metal salient point arrangement can define arbitrarily, realize the interconnection of chip and carrier better.
Accompanying drawing explanation
Fig. 1 is the profile of utility model.
Each Reference numeral is: 2-metal salient point, 3-chip, 4-plastic-sealed body, 5-silver coating, 6-plating NiPdAu layer, 7-copper articulamentum.
Embodiment
Below in conjunction with accompanying drawing, the utility model is described in further detail.
With reference to shown in Fig. 1, the utility model discloses a kind of ultra-thin potted element, comprise plastic-sealed body 4 and be encapsulated in the chip 3 in plastic-sealed body 4, metal salient point 2, silver coating 5, plating NiPdAu layer 6 and copper articulamentum 7, chip 3, metal salient point 2, silver coating 5, copper articulamentum 7 and plating NiPdAu layer 6 constitute power supply and the signalling channel of circuit, described copper articulamentum 7 has multiple, the upper surface of each copper articulamentum 7 and lower surface are respectively arranged with silver coating 5 and plating NiPdAu layer 6, described multiple silver coatings 5 are separate, described chip 3 solder side is provided with multiple metal salient point 2, chip 3 is connected with multiple silver coating 5 by metal salient point 2 simultaneously, due to will NiPdAu layer 6 be plated as the signal interface channel with external circuit, be equivalent to " pin " of common encapsulation, plating link can be saved, under the prerequisite that metal salient point arrangement and I/O number do not limit by Frame Design and making, achieve metal salient point arrangement can define arbitrarily, realize the interconnection of chip and carrier better.
Further, the thickness of described silver coating 5 and plating NiPdAu layer 6 is 3-5um, greatly reduces the thickness of QFN/DFN encapsulating products, the thickness of plastic-sealed body 4 can be set to be less than 0.35mm, and traditional QFN/DFN packaging body thickness is at more than 0.7mm, packaging body thickness can be made like this to reduce 100%.
Further, one group of relative edge of copper articulamentum 7 lower end is provided with chamfering, as a kind of preferred embodiment, chamfering can also be arranged to right angle chamfering, not only form effective anti-traction structure, after plastic packaging, plastic packaging material fills the groove of full copper chamfering layer, form effective anti-traction structure, significantly reduce framework after corrosion is thinning, the risk of sliding in mould, also greatly facilitates the processing of copper articulamentum 7, simultaneously, reduce plastic packaging material pressure, add the bonding area of plastic packaging material and metal framework, package reliability significantly promotes.
The utility model adopts frame-generic to carry out production flow process, without the need to crossing multi-processing frame carrier, shortening the design cycle, reducing costs, and realizes the interconnected of chip and carrier better, makes I/O more crypto set.
Traditional QFN/DFN framework, in order to prevent occurring during plastic packaging " overflow glue ", posts a skim at the framework back side; And the utility model is owing to having plated layer of Ni PdAu above framework, can play the effect of isolation plastic packaging material, plastic packaging post-etching has fallen framework, can play the effect preventing " overflow glue " equally, so just can save the process of framework manufacturer " pad pasting ".
The potted element provided due to the utility model can in order to avoid plating, exempt from pad pasting, fabrication cycle is short, the dense degree of I/O and package reliability high, production cost significantly reduces, and product is more competitive.
Above-described embodiment is illustrative principle of the present utility model and effect thereof only; and the embodiment that part is used; for the person of ordinary skill of the art; under the prerequisite not departing from the utility model creation design; can also make some distortion and improvement, these all belong to protection range of the present utility model.
Claims (5)
1. a ultra-thin potted element, it is characterized in that: comprise plastic-sealed body (4) and be encapsulated in the chip (3) in plastic-sealed body (4), metal salient point (2), silver coating (5), plating NiPdAu layer (6) and copper articulamentum (7), chip (3), metal salient point (2), silver coating (5), copper articulamentum (7) and plating NiPdAu layer (6) constitute power supply and the signalling channel of circuit, described copper articulamentum (7) has multiple, the upper surface of each copper articulamentum (7) and lower surface are respectively arranged with silver coating (5) and plating NiPdAu layer (6), described multiple silver coatings (5) are separate, described chip (3) solder side is provided with multiple metal salient point (2), chip (3) is connected with multiple silver coating (5) by metal salient point (2) simultaneously.
2. a kind of ultra-thin potted element according to claim 1, is characterized in that, the thickness of described silver coating (5) and plating NiPdAu layer (6) is 3-5um.
3. a kind of ultra-thin potted element according to claim 2, is characterized in that, the thickness of described plastic-sealed body (4) is less than 0.35mm.
4. a kind of ultra-thin potted element according to claim 3, is characterized in that, one group of relative edge of described copper articulamentum (7) lower end is provided with chamfering.
5. a kind of ultra-thin potted element according to claim 4, is characterized in that, described chamfering is right angle chamfering.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520003374.9U CN204348707U (en) | 2015-01-05 | 2015-01-05 | A kind of ultra-thin potted element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520003374.9U CN204348707U (en) | 2015-01-05 | 2015-01-05 | A kind of ultra-thin potted element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204348707U true CN204348707U (en) | 2015-05-20 |
Family
ID=53231958
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520003374.9U Active CN204348707U (en) | 2015-01-05 | 2015-01-05 | A kind of ultra-thin potted element |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204348707U (en) |
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2015
- 2015-01-05 CN CN201520003374.9U patent/CN204348707U/en active Active
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |