CN204315565U - Lead frame - Google Patents
Lead frame Download PDFInfo
- Publication number
- CN204315565U CN204315565U CN201520013960.1U CN201520013960U CN204315565U CN 204315565 U CN204315565 U CN 204315565U CN 201520013960 U CN201520013960 U CN 201520013960U CN 204315565 U CN204315565 U CN 204315565U
- Authority
- CN
- China
- Prior art keywords
- pin
- lead frame
- area
- chip region
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Abstract
The utility model relates to a kind of new component, especially a kind of lead frame, in order to chip, the pin area comprising fin and be connected with described fin, radiating area and the chip region that at least two chips can be installed is provided with in described fin, described chip region is connected with two pin area at least respectively, and each described pin area comprises the left side pin and right side pin that be arranged in parallel.Owing to can install at least two chips in chip region, and the quantity of the pin area be connected with chip region is at least two, thus energy serial or parallel connection at least two chips during assembling, increase chip area, also easier and convenient in operation in addition.
Description
Technical field
The utility model relates to a kind of new component, and especially a kind of lead frame, belongs to electronic information technology.
Background technology
Lead frame is as the chip carrier of integrated circuit, it is a kind of electrical connection realizing chip internal circuits exit and outer lead by means of bonding gold wire, form the key structure part of electric loop, it serves the function served as bridge be connected with outer lead, all need in the semiconductor integrated block of the overwhelming majority to use lead frame, lead frame is basic material important in electronics and information industry.Lead frame needs recurrence chip region surface mount chip, recycles resin plastic-sealed chip fixing in holistic half guiding element.Lead frame has the fin of chip, the restriction of existing radiating area, maximumly can fill about 4.6mm*5.3mm, and the limited amount system of chip, fill at most two chips, product current/voltage is less.
Because above-mentioned defect, the design people, actively in addition research and innovation, to founding a kind of lead frame of new structure, make it have more value in industry.
Utility model content
The purpose of this utility model is to provide one and increases chip area, and also more easily and easily lead frame in operation.
In order to achieve the above object, the technical scheme that the utility model adopts is as follows: a kind of lead frame, in order to chip, the pin area comprising fin and be connected with described fin, radiating area and the chip region that at least two chips can be installed is provided with in described fin, described chip region is connected with two pin area at least respectively, and each described pin area comprises the left side pin and right side pin that be arranged in parallel.
Further, the length of described chip region is the multiple being greater than the positive integer of 1 of TO-220C lead frame length, and the height of described chip region is identical with the height of TO-220C lead frame.
Further, the length of described radiating area is identical with the length of chip region.
Further, described radiating area only offers a louvre.
Further, at least two described pin area be arranged in parallel, and are positioned at immediately below chip region.
Further, each described pin area also comprises the middle pin district be set in parallel between left side pin and right side pin, and described middle pin district is connected to chip region, described left side pin and right side pin is provided with and spatters a portion.
By such scheme, the utility model at least has the following advantages: owing to can install at least two chips in chip region, and the quantity of the pin area be connected with chip region is at least two, thus energy serial or parallel connection at least two chips during assembling, increase chip area, also easier and convenient in operation in addition.
Above-mentioned explanation is only the general introduction of technical solutions of the utility model, in order to better understand technological means of the present utility model, and can be implemented according to the content of specification, coordinates accompanying drawing to be described in detail as follows below with preferred embodiment of the present utility model.
Accompanying drawing explanation
Fig. 1 is the structural representation of the utility model lead frame.
Embodiment
Below in conjunction with drawings and Examples, embodiment of the present utility model is described in further detail.Following examples for illustration of the utility model, but are not used for limiting scope of the present utility model.
See Fig. 1, a kind of lead frame 10 described in the utility model one preferred embodiment in order to install TO-220C-B chip (not shown), hereafter by this lead frame 10 called after TO-220C-B lead frame.The pin area 2 that TO-220C-B lead frame 10 comprises fin 1 and is connected with described fin 1, is provided with radiating area 11 and the chip region 12 can installing at least two chips in described fin 1.Described chip region 12 is connected with two pin area 2 at least respectively, each described pin area 2 comprises the left side pin 21 and right side pin 22 that be arranged in parallel and the middle pin 23 be set in parallel between left side pin 21 and right side pin 22, described middle pin 23 is connected to chip region 12, described left side pin 21 and right side pin 22 is provided with and spatters a portion 24.The length of described chip region 12 is the multiple being greater than the positive integer of 1 of TO-220C lead frame 20 length, and the height of described chip region 12 is identical with the height of TO-220C lead frame 20.The length of described radiating area 11 is identical with the length of chip region 12.Described radiating area 11 only offers a louvre 13.At least two described pin area 2 be arranged in parallel, and are positioned at immediately below chip region 12.
Below for the assembling flow path of TO-220C-B lead frame 10, the TO-220C-B device adopting the present embodiment is generally:
S1, (adding) some solder---by a certain amount of slicken solder at high temperature, be melted on TO-220C-B lead frame 10;
S2, load---TO-220C-B chip is at high temperature contained on the solder melted;
S3, bonding---use specific wire, the terminal pins that the electrode of TO-220C-B chip surface is corresponding with TO-220C-B lead frame 10 connects;
S4, plastic packaging---use specific epoxy resin, inject TO-220C-B plastic package die, form the TO-220C-B device of whole row;
S5, cleaning---the overlap between the TO-220C-B pin removing whole row;
S6, cut muscle---by muscle and the excision of end muscle between connection TO-220C-B unit pin, form single TO-220C-B device;
S7, test---according to the electrical property of each TO-220C-B device, carry out stepping (class);
S8, packaging---the TO-220C-B device after test is protected, convenient transport.
In sum, owing to can install at least two chips in chip region 12, and the quantity of the pin area 2 be connected with chip region 12 is at least two, thus energy serial or parallel connection at least two TO-220C-B chips during assembling, increase chip area, also easier and convenient in operation in addition.
In addition, length due to chip region 12 is the multiple being greater than the positive integer of 1 of TO-220C lead frame 20, the height of described chip region 12 is identical with the height of TO-220C lead frame 20, it can use with the track of normal TO-220C lead frame 20 jointly when bonding die bonding on the one hand, contribute to saving cost, on the other hand, lead frame 10 of the present utility model expands fin 1 area, can do high-power product while assembling multiple TO-220C-B chip.
The above is only preferred implementation of the present utility model; be not limited to the utility model; should be understood that; for those skilled in the art; under the prerequisite not departing from the utility model know-why; can also make some improvement and modification, these improve and modification also should be considered as protection range of the present utility model.
Claims (6)
1. a lead frame, in order to chip, the pin area comprising fin and be connected with described fin, it is characterized in that: in described fin, be provided with radiating area and the chip region that at least two chips can be installed, described chip region is connected with two pin area at least respectively, and each described pin area comprises the left side pin and right side pin that be arranged in parallel.
2. lead frame according to claim 1, is characterized in that: the length of described chip region is the multiple being greater than the positive integer of 1 of TO-220C lead frame length, and the height of described chip region is identical with the height of TO-220C lead frame.
3. lead frame according to claim 2, is characterized in that: the length of described radiating area is identical with the length of chip region.
4. lead frame according to claim 3, is characterized in that: described radiating area only offers a louvre.
5. lead frame according to claim 1, is characterized in that: at least two described pin area be arranged in parallel, and are positioned at immediately below chip region.
6. lead frame according to claim 5, it is characterized in that: each described pin area also comprises the middle pin district be set in parallel between left side pin and right side pin, described middle pin district is connected to chip region, described left side pin and right side pin is provided with and spatters a portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520013960.1U CN204315565U (en) | 2015-01-09 | 2015-01-09 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520013960.1U CN204315565U (en) | 2015-01-09 | 2015-01-09 | Lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204315565U true CN204315565U (en) | 2015-05-06 |
Family
ID=53137866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520013960.1U Expired - Fee Related CN204315565U (en) | 2015-01-09 | 2015-01-09 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204315565U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449578A (en) * | 2016-09-21 | 2017-02-22 | 无锡罗姆半导体科技有限公司 | Semiconductor packaging part and packaging method therefor |
| CN111199941A (en) * | 2018-11-16 | 2020-05-26 | 泰州友润电子科技股份有限公司 | High-insulation lead frame and gluing method |
-
2015
- 2015-01-09 CN CN201520013960.1U patent/CN204315565U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449578A (en) * | 2016-09-21 | 2017-02-22 | 无锡罗姆半导体科技有限公司 | Semiconductor packaging part and packaging method therefor |
| CN111199941A (en) * | 2018-11-16 | 2020-05-26 | 泰州友润电子科技股份有限公司 | High-insulation lead frame and gluing method |
| CN111199941B (en) * | 2018-11-16 | 2022-03-25 | 泰州友润电子科技股份有限公司 | High-insulation lead frame and gluing method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150506 Termination date: 20160109 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |