CN204190367U - A kind of novel current foldback circuit - Google Patents

Abstract

The utility model relates to circuit protection technical field, especially a kind of novel current foldback circuit.It comprises by the 14 power switch pipe, 13 field effect transistor, first resistance and, second resistance, 3rd resistance, 4th resistance, the sample circuit that 5th resistance and the 6th resistance are formed, by the 4th field effect transistor, 5th field effect transistor, 6th field effect transistor, 7th field effect transistor, 8th field effect transistor, 9th field effect transistor, the comparator main body circuit that first triode and the second triode are formed, by the temperature-compensating to sample circuit, further reduce the mistake flow point change because variations in temperature causes, improve flow point precision, effectively reduce temperature to the impact of crossing flow point.The utility model structure is simple, reliability is high and low in energy consumption, has very strong practicality.

Description

A kind of novel current foldback circuit

Technical field

The utility model relates to circuit protection technical field, especially a kind of novel current foldback circuit.

Background technology

In recent years, along with the develop rapidly of electronic technology and the extensive application of integrated circuit, the reliability and stability of circuit and system are had higher requirement, and need Circuits System can detect critical operational parameters rapidly and accurately.And the ability that the high power device in integrated circuit bears short-time overload as MOSFET, IGBT etc. is poor, the energy easily making pipe inner accumulated too much because of overvoltage or overcurrent, thus cause damaged tubular.

In conventional overcurrent protective circuit; current sample method is the external sampling resistor by being in series with inductance or power device; be that voltage is sampled by current conversion, then compare with the reference voltage of inside, by conducting or the shutoff of control circuit control switch power tube.But when adopting in this way, the electric current flowing through power tube flows through sampling resistor, increases power loss; Requiring the occasion of low-power consumption, its application is limited by very large.

The power consumption existed for conventional overcurrent protective circuit is comparatively large, cross the larger problem of flow point temperature drift, therefore, is necessary existing current foldback circuit proposition improvement project, to improve the practicality of circuit.

Utility model content

For above-mentioned the deficiencies in the prior art, the purpose of this utility model is to provide a kind of reliability high, low in energy consumption, that the drift of flow point temperature is little excessively novel current foldback circuit.

To achieve these goals, the utility model adopts following technical scheme:

A kind of novel current foldback circuit, it comprises the 14 power switch pipe, the 13 field effect transistor, the first field effect transistor, the second field effect transistor, the 3rd field effect transistor, the 4th field effect transistor, the 5th field effect transistor, the 6th field effect transistor, the 7th field effect transistor, the 8th field effect transistor, the 9th field effect transistor, the tenth field effect transistor, the 11 field effect transistor, the 12 field effect transistor, the first triode and the second triode;

The drain electrode of described 14 power switch pipe is connected to the drain electrode of the 13 field effect transistor, the grid of described 13 field effect transistor is connected with the first electric capacity, the source electrode of described 13 field effect transistor is connected with the first resistance and the second resistance in turn, the source electrode of described 13 field effect transistor is in series with the 3rd resistance, the 4th resistance, the 5th resistance and the 6th resistance successively, the grid of described first field effect transistor is connected to the grid of the second field effect transistor, and the drain electrode of described second field effect transistor is connected to the drain electrode of the 3rd field effect transistor;

The grid of described 3rd field effect transistor is connected to the grid of the 4th field effect transistor, the drain electrode of described 4th field effect transistor is connected to the drain electrode of the 5th field effect transistor, the grid of described 5th field effect transistor is connected to the grid of the 6th field effect transistor, the drain electrode of described 6th field effect transistor is connected to the collector electrode of the first triode, the base stage of described first triode is connected between the 4th resistance and the 5th resistance, the emitter of described first triode is connected to the drain electrode of the 7th field effect transistor, the source electrode of described 7th field effect transistor is connected to the drain electrode of the 8th field effect transistor, the grid of described 9th field effect transistor is connected to the drain electrode of the 3rd field effect transistor, the drain electrode of described 9th field effect transistor is connected to the emitter of the second triode, the base stage of described second triode is connected to the 7th resistance and the second electric capacity, the base stage of described second triode is connected to the drain electrode of the 11 field effect transistor, the source electrode of described 11 field effect transistor is connected to the drain electrode of the tenth field effect transistor, the grid of described 11 field effect transistor is connected to the grid of the 12 field effect transistor.

Owing to have employed such scheme, the utility model adopts by the 14 power switch pipe, 13 field effect transistor, first resistance, second resistance, 3rd resistance, 4th resistance, the sample circuit that 5th resistance and the 6th resistance are formed, by the 4th field effect transistor, 5th field effect transistor, 6th field effect transistor, 7th field effect transistor, 8th field effect transistor, 9th field effect transistor, the comparator main body circuit that first triode and the second triode are formed, by the temperature-compensating to sample circuit, further reduce the mistake flow point change because variations in temperature causes, improve flow point precision, reliability height is low in energy consumption, there is very strong practicality.

Accompanying drawing explanation

Fig. 1 is the circuit connection structure figure of the utility model embodiment.

Embodiment

Below in conjunction with accompanying drawing, embodiment of the present utility model is described in detail, but the multitude of different ways that the utility model can be defined by the claims and cover is implemented.

As shown in Figure 1, the novel current foldback circuit of one of the present embodiment, it comprises the 14 power switch pipe MOSFET, the 13 field effect transistor JFET, the first field effect transistor M1, the second field effect transistor M2, the 3rd field effect transistor M3, the 4th field effect transistor M4, the 5th field effect transistor M5, the 6th field effect transistor M6, the 7th field effect transistor M7, the 8th field effect transistor M8, the 9th field effect transistor M9, the tenth field effect transistor M10, the 11 field effect transistor M11, the 12 field effect transistor M12, the first triode Q1 and the second triode Q2;

The drain electrode of the 14 power switch pipe MOSFET is connected to the drain electrode of the 13 field effect transistor JFET and receives sample rate current I1, and the grid of the 14 power switch pipe MOSFET receives RIVER signal and its source ground; The source electrode of the 13 field effect transistor JFET is connected with the first resistance R1 and the second resistance R2 in turn, the grid of the 13 field effect transistor JFET is connected with the first electric capacity C1 and is connected between the first resistance R1 and the second resistance R2, and the source electrode of the 13 field effect transistor JFET is in series with the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5 and the 6th resistance R6 successively; The grid of the first field effect transistor M1 is connected to the grid of the second field effect transistor M2, the grid of the first field effect transistor M1 and its drain electrode short circuit; The drain electrode of the second field effect transistor M2 is connected to the drain electrode of the 3rd field effect transistor M3;

The grid of the 3rd field effect transistor M3 is connected to the grid of the 4th field effect transistor M4, the grid of the 3rd field effect transistor M3 and its drain electrode short circuit; The drain electrode of the 4th field effect transistor M4 is connected to the drain electrode of the 5th field effect transistor M5, and the grid of the 5th field effect transistor M5 is connected to the grid of the 6th field effect transistor M6; The drain electrode of the 6th field effect transistor M6 is connected to the collector electrode of the first triode Q1, the grid of the 6th field effect transistor M6 and its drain electrode short circuit; The base stage of the first triode Q1 is connected between the 4th resistance R4 and the 5th resistance R5, and the emitter of the first triode Q1 is connected to the drain electrode of the 7th field effect transistor M7; The source electrode of the 7th field effect transistor M7 is connected to the drain electrode of the 8th field effect transistor M8, and the grid of the 7th field effect transistor M7 is connected to the grid of the 14 power switch pipe MOSFET; The grid of the 8th field effect transistor M8 is connected to the grid of the 9th field effect transistor M9, and the grid of the 9th field effect transistor M9 is connected to the drain electrode of the 3rd field effect transistor M3, and the drain electrode of the 9th field effect transistor M9 is connected to the emitter of the second triode Q2; The base stage of the second triode Q2 is connected to the drain electrode of the 11 field effect transistor M11, and the source electrode of the 11 field effect transistor M11 is connected to the drain electrode of the tenth field effect transistor M10; The grid of the tenth field effect transistor M10 is connected to the grid of the 14 power switch pipe MOSFET by an inverter, the grid of the 11 field effect transistor M11 is connected to the grid of the 12 field effect transistor M12, the grid of the 12 field effect transistor M12 and its drain electrode short circuit, the base stage of the second triode Q2 is connected to the 7th resistance R7 and the second electric capacity C2.

The wherein sample circuit of the 14 power switch pipe MOSFET, the 13 field effect transistor JFET, the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5 and the 6th resistance R6 formation; The comparator main body circuit that 4th field effect transistor M4, the 5th field effect transistor M5, the 6th field effect transistor M6, the 7th field effect transistor M7, the 8th field effect transistor M8, the 9th field effect transistor M9, the first triode Q1 and the second triode Q2 are formed.

In the circuit of the present embodiment, when the grid of the 14 power switch pipe MOSFET is high level, the 7th field effect transistor M7 and the tenth field effect transistor M10 conducting; When 14 power switch pipe MOSFET is low level, the 7th field effect transistor M7 and the tenth field effect transistor M10 turns off, and reduces the power loss of overcurrent protection module.During the 14 power switch pipe MOSFET conducting, the voltage of its drain electrode reflects the size of drain-source current.

In sample circuit, for reducing power consumption, the order of magnitude of the first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5 and the 6th resistance R6 is all set to 100k Ω.During circuit working, during the 14 power switch pipe MOSFET conducting, the voltage compare of the drain electrode of the 14 power switch pipe MOSFET and the 13 field effect transistor JFET is low, first resistance R1 and the second resistance R2 potential-divider network, guarantee that the 13 field effect transistor JFET always works in degree of depth linear zone when the 14 power switch pipe MOSFET conducting, pressure drop between the drain electrode of the 13 field effect transistor JFET and source electrode is made to be about zero, first resistance R1, second resistance R2, 3rd resistance R3, 4th resistance R4, the pressure drop that 5th resistance R5 and the 6th resistance R6 bears is very low, the electric current flowing through resistance is very little.And when the 14 power switch pipe MOSFET turns off, the voltage of the drain electrode of the 14 power switch pipe MOSFET and the 13 field effect transistor JFET raises, 13 field effect transistor JFET enters linear zone, pressure drop between the drain electrode of the 13 field effect transistor JFET and source electrode increases, the pressure drop that first resistance R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5 and the 6th resistance R6 bear is still very low, and the electric current flowing through resistance is also very little.Wherein, the output of the resistance pressure-dividing network of the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5 and the 6th resistance R6 composition directly accesses comparator main body circuit, as an input of comparator.

In comparator main body circuit, current source I2 is mirrored to the 4th field effect transistor M4 by the first field effect transistor M1, the second field effect transistor M2 and the 3rd field effect transistor M3, and the output stage for comparator provides biased; Be mirrored to the 8th field effect transistor M8 and the 9th field effect transistor M9, for differential pair provides biased simultaneously.Current source I3 is mirrored to the 11 field effect transistor M11 by the 12 field effect transistor M12, flows through the comparative level VREF that the 7th resistance R7 produces a comparator.Second electric capacity C2 strobes, the high-frequency signal that filtering comparative level VREF may exist.When VQ1B voltage is equal with comparative level VREF, comparator output voltage VO UT overturns, and output voltage is input to driver module, controls the 14 power switch pipe MOSFET and turns off, damage to avoid the 14 power switch pipe MOSFET.

Conducting resistance RDS has positive temperature coefficient.In order to reduce the change of the over-current protection point causing the 14 power switch pipe MOSFET because of temperature coefficient, the 7th resistance R7 also should have positive temperature coefficient.But because the temperature coefficient of conducting resistance RDS can not be identical with the temperature coefficient of the 7th resistance R7, so the resistance pressure-dividing network be made up of the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5 and the 6th resistance R6 in sample circuit introduces temperature-compensating.3rd resistance R3 and the 5th resistance R5 adopts the resistance of positive temperature coefficient; 4th resistance R4 and the 6th resistance R6 adopts the resistance of negative temperature coefficient; regulate the value of the 3rd resistance R3, the 4th resistance R4, the 5th resistance R5 and the 6th resistance R6; VQ1B and VREF can be made to have identical positive temperature coefficient, and ensure to set up at over-current protection point place VQ1B=VREF.

The foregoing is only preferred embodiment of the present utility model; not thereby the scope of the claims of the present utility model is limited; every utilize the utility model specification and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present utility model.

Claims (1)

1. a novel current foldback circuit, is characterized in that: it comprises the 14 power switch pipe, the 13 field effect transistor, the first field effect transistor, the second field effect transistor, the 3rd field effect transistor, the 4th field effect transistor, the 5th field effect transistor, the 6th field effect transistor, the 7th field effect transistor, the 8th field effect transistor, the 9th field effect transistor, the tenth field effect transistor, the 11 field effect transistor, the 12 field effect transistor, the first triode and the second triode;

The drain electrode of described 14 power switch pipe is connected to the drain electrode of the 13 field effect transistor, the grid of described 13 field effect transistor is connected with the first electric capacity, the source electrode of described 13 field effect transistor is connected with the first resistance and the second resistance in turn, the source electrode of described 13 field effect transistor is in series with the 3rd resistance, the 4th resistance, the 5th resistance and the 6th resistance successively, the grid of described first field effect transistor is connected to the grid of the second field effect transistor, and the drain electrode of described second field effect transistor is connected to the drain electrode of the 3rd field effect transistor;

The grid of described 3rd field effect transistor is connected to the grid of the 4th field effect transistor, the drain electrode of described 4th field effect transistor is connected to the drain electrode of the 5th field effect transistor, the grid of described 5th field effect transistor is connected to the grid of the 6th field effect transistor, the drain electrode of described 6th field effect transistor is connected to the collector electrode of the first triode, the base stage of described first triode is connected between the 4th resistance and the 5th resistance, the emitter of described first triode is connected to the drain electrode of the 7th field effect transistor, the source electrode of described 7th field effect transistor is connected to the drain electrode of the 8th field effect transistor, the grid of described 9th field effect transistor is connected to the drain electrode of the 3rd field effect transistor, the drain electrode of described 9th field effect transistor is connected to the emitter of the second triode, the base stage of described second triode is connected to the 7th resistance and the second electric capacity, the base stage of described second triode is connected to the drain electrode of the 11 field effect transistor, the source electrode of described 11 field effect transistor is connected to the drain electrode of the tenth field effect transistor, the grid of described 11 field effect transistor is connected to the grid of the 12 field effect transistor.