CN204180173U - Cmos image sensor double-channel data transmission structure - Google Patents

Cmos image sensor double-channel data transmission structure Download PDF

Info

Publication number
CN204180173U
CN204180173U CN201420642210.6U CN201420642210U CN204180173U CN 204180173 U CN204180173 U CN 204180173U CN 201420642210 U CN201420642210 U CN 201420642210U CN 204180173 U CN204180173 U CN 204180173U
Authority
CN
China
Prior art keywords
data transmission
transmission structure
image processing
channel data
processing module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201420642210.6U
Other languages
Chinese (zh)
Inventor
赵晓海
程杰
刘志碧
陈杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Superpix Micro Technology Co Ltd
Original Assignee
Beijing Superpix Micro Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Superpix Micro Technology Co Ltd filed Critical Beijing Superpix Micro Technology Co Ltd
Priority to CN201420642210.6U priority Critical patent/CN204180173U/en
Application granted granted Critical
Publication of CN204180173U publication Critical patent/CN204180173U/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Abstract

The utility model discloses a kind of cmos image sensor double-channel data transmission structure, comprise pel array, Digital Image Processing module and passage concatenation module, adopt double-channel data transmission structure to be connected between pel array with Digital Image Processing module, between Digital Image Processing module with passage concatenation module, adopt double-channel data transmission structure to be connected.Passage concatenation module is spliced by the color sequences of preimage pixel array the view data that binary channels inputs, final output image data.Can efficiency of transmission be improved, thus effectively reduce the power consumption of this adhesive integrated circuit.

Description

Cmos image sensor double-channel data transmission structure
Technical field
The utility model relates to a kind of cmos image sensor, particularly relates to a kind of cmos image sensor double-channel data transmission structure.
Background technology
At present, cmos image sensor is widely used in the fields such as Aero-Space, watch-dog, mobile terminal, and especially in various mobile terminal device, it plays a part indispensable especially.But along with the fluency of consumer to the picture quality of still picture and video image requires more and more higher, cmos image sensor has to increase substantially operating frequency, meets the requirement of process high-resolution and high frame rate image.
But, there is following defect in prior art: the single-pass data transmission structure of prior art is as shown in Figure 1a after the requirement meeting high operate frequency, when process and transmitting image, as shown in table 1, the power consumption of cmos image sensor can be substantially increased, the battery durable ability of mobile terminal device is greatly affected.
Utility model content
The purpose of this utility model is to provide a kind of efficiency of transmission cmos image sensor double-channel data transmission structure high, low in energy consumption.
The purpose of this utility model is achieved through the following technical solutions:
Cmos image sensor double-channel data transmission structure of the present utility model, comprise pel array, Digital Image Processing module and passage concatenation module, adopt double-channel data transmission structure to be connected between described pel array with Digital Image Processing module, described Digital Image Processing module is connected with adopting double-channel data transmission structure between passage concatenation module.
The technical scheme provided as can be seen from above-mentioned the utility model, the cmos image sensor double-channel data transmission structure that the utility model embodiment provides, due to transfer of data is become binary channels from single channel, can efficiency of transmission be improved, thus effectively reduce the power consumption of this adhesive integrated circuit.
Accompanying drawing explanation
Fig. 1 a is the schematic diagram of single channel transmission in prior art;
Fig. 1 b is the schematic diagram of dual-channel transmission in the utility model embodiment.
Embodiment
To be described in further detail the utility model embodiment below.
Cmos image sensor double-channel data transmission structure of the present utility model, its preferably embodiment be:
Comprise pel array, Digital Image Processing module and passage concatenation module, adopt double-channel data transmission structure to be connected between described pel array with Digital Image Processing module, described Digital Image Processing module is connected with adopting double-channel data transmission structure between passage concatenation module.
Above-mentioned cmos image sensor double-channel data transmission structure of the present utility model realizes the method for transfer of data, comprises step:
A, read view data in binary channels mode from pel array;
B, this two channel data is sent into Digital Image Processing module, this Digital Image Processing module carries out image procossing to input data;
C, described Digital Image Processing module send view data with binary channels;
D, passage concatenation module are spliced by the color sequences of preimage pixel array the view data that binary channels inputs, final output image data.
In stepb, the operating frequency of Digital Image Processing module is consistent with the operating frequency that Digital Image Processing module sends view data with binary channels.
In step D, the operating frequency of passage concatenation module is consistent with the operating frequency of final output image data.
The operating frequency of passage concatenation module and the operating frequency of final output image data are that the operating frequency of Digital Image Processing module and Digital Image Processing module send 2 times of viewdata operation frequency with binary channels.
Transfer of data, by a kind of structure that can reduce the power consumption of cmos image sensor, is become binary channels from single channel by the utility model, to improve efficiency of transmission, thus effectively reduces the power consumption of this adhesive integrated circuit.This structure, by widening the width of data transmission channel, reduces the frequency of transfer of data, and then reduces the power consumption of whole integrated circuit.
Specific embodiment:
Be described with the RAW data instance that cmos image sensor wants output resolution ratio to be 1600x1200, Digital Image Processing module carries out work with 42Mhz frequency.For the cmos image sensor of other output formats or the cmos image sensor of other resolution, or the cmos image sensor of other operating frequencies all can be applied.
As shown in Figure 1 b, in the cmos image sensor double-channel data transmission structure of this specific embodiment, at least comprise pel array, Digital Image Processing module, passage concatenation module, pel array and Digital Image Processing module use double-channel data transmission structure, Digital Image Processing module with binary channels from cmos pixel array by view data series read-out; Image processing module and passage concatenation module adopt double-channel data transmission structure, after double-channel data transfers to passage concatenation module, carry out data splicing.Its principle is, data concatenation module spells two channel datas for single channel, and now data frequency improves 1 times; Digital Image Processing module completes various image processing function.
Can see from the contrast of Fig. 1 a and Fig. 1 b and table 1 and table 2, the operating frequency of Digital Image Processing module becomes 42Mhz from 84Mhz, because this reducing the power consumption of whole cmos image sensor.
In the present embodiment, specific implementation step during cmos image sensor work is:
1, with binary channels and the frequency of every passage 42Mhz, RAW data are read from pel array;
2, this two channel data is sent into Digital Image Processing module, this module carries out various image procossing with the operating frequency of 42Mhz to input data;
3, Digital Image Processing module sends view data with the frequency of binary channels, every passage 42Mhz;
4, passage concatenation module is operated in the frequency of 84Mhz, and it splices by the color sequences of preimage pixel array the view data of binary channels, every passage 42Mhz, the final RAW data exporting 84Mhz.
Table 1, the power consumption citing of single channel digital image processing IC in prior art:
Table 2, the power consumption citing of two-channel digital image processing IC in the utility model embodiment:
The above; be only the utility model preferably embodiment; but protection range of the present utility model is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; the change that can expect easily or replacement, all should be encompassed within protection range of the present utility model.Therefore, protection range of the present utility model should be as the criterion with the protection range of claims.

Claims (1)

1. a cmos image sensor double-channel data transmission structure, comprise pel array, Digital Image Processing module and passage concatenation module, it is characterized in that, adopt double-channel data transmission structure to be connected between described pel array with Digital Image Processing module, described Digital Image Processing module is connected with adopting double-channel data transmission structure between passage concatenation module.
CN201420642210.6U 2014-10-30 2014-10-30 Cmos image sensor double-channel data transmission structure Expired - Fee Related CN204180173U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201420642210.6U CN204180173U (en) 2014-10-30 2014-10-30 Cmos image sensor double-channel data transmission structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201420642210.6U CN204180173U (en) 2014-10-30 2014-10-30 Cmos image sensor double-channel data transmission structure

Publications (1)

Publication Number Publication Date
CN204180173U true CN204180173U (en) 2015-02-25

Family

ID=52568946

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201420642210.6U Expired - Fee Related CN204180173U (en) 2014-10-30 2014-10-30 Cmos image sensor double-channel data transmission structure

Country Status (1)

Country Link
CN (1) CN204180173U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104284111A (en) * 2014-10-30 2015-01-14 北京思比科微电子技术股份有限公司 CMOS image sensor double-channel data transmission structure and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104284111A (en) * 2014-10-30 2015-01-14 北京思比科微电子技术股份有限公司 CMOS image sensor double-channel data transmission structure and method

Similar Documents

Publication Publication Date Title
CN101819755B (en) Monitor joined screen with function of displaying multi-channel video signals and realization method thereof
CN103813107A (en) Multichannel high-definition video overlapping method based on FPGA (field programmable gata array)
CN204180173U (en) Cmos image sensor double-channel data transmission structure
CN103533352A (en) Compression method and device and decompression method and device for image with transparency
US20120306828A1 (en) Driving circuit and operating method thereof
CN203734741U (en) Two-channel LVDS video rotating and overlapping system
CA2675579A1 (en) Programmable pattern-based unpacking and packing of data channel information
CN103997399A (en) EDP interface, handset and method for improving transmission rate of eDP interface communication
CN104284111A (en) CMOS image sensor double-channel data transmission structure and method
CN204031327U (en) Based on DisplayPort, realize the control device of video wall splicing
CN101729845A (en) Camera-Link digital video information superimposing method
CN205231423U (en) Multi -functional connection converter
CN105516757B (en) A kind of Z-operation system intelligent radio display system detached with intelligent use system
CN205212951U (en) 4K display screen devices that show more
CN205051789U (en) High -speed image acquisition processing apparatus based on USB3. 0
CN203311817U (en) LED splicer
CN204086740U (en) A kind of LCD display interface switching device
CN204408493U (en) A kind of four full HD video processing circuitss in tunnel based on FPGA
CN103607545A (en) High definition video acquisition device and working method thereof
CN102857777B (en) Display system and display control method thereof
CN105681825B (en) A kind of video code flow output-controlling device and method
CN203104673U (en) Monitoring device with two power inputs
CN203455829U (en) Printing system using analog audio signal to transmit data
CN203942574U (en) A kind of broad width scanning instrument system
CN203827450U (en) Display device and display system

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20150225

Termination date: 20181030

CF01 Termination of patent right due to non-payment of annual fee