CN203311817U - LED splicer - Google Patents
LED splicer Download PDFInfo
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- CN203311817U CN203311817U CN2013204037082U CN201320403708U CN203311817U CN 203311817 U CN203311817 U CN 203311817U CN 2013204037082 U CN2013204037082 U CN 2013204037082U CN 201320403708 U CN201320403708 U CN 201320403708U CN 203311817 U CN203311817 U CN 203311817U
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Abstract
The utility model provides an LED splicer. The LED splicer comprises an input port, an input decoder, a button panel, a microcontroller, a digital video processor, an output encoder, an output port, an EEPROM chip and a memory; the input port is connected with the input decoder; the input decoder is connected with the digital video processor; the button panel is connected with the microcontroller; the microcontroller is connected with the digital video processor; the digital video processor is connected with the output encoder; the output encoder is connected with the output port; the EEPROM chip is connected with the microcontroller; and the memory is connected with the digital video processor. The LED splicer is advantageous in that the LED splicer is capable of receiving image signals of multiple kinds of general formats, dynamically outputting video in real time and being widely applied, and is simple in structure, easy to operate and strong in practicability.
Description
Technical field
The utility model belongs to the large screen display field, is specifically related to a kind of LED splicer.
Background technology
Large screen display system is widely used in communication, electric power, military field, plays an important role providing aspect shared information, decision support, situation.Large screen display system mainly is comprised of video input device, splicer and demonstration wall, and splicer is the key equipment of realizing large screen display.
Publication number is the utility model patent of CN20288948U, the digital jointing device that a kind of input and output are the HDMI signal is disclosed, it is changed by signal extension, be pooled to and collect the differential data signals line and collect clock cable, signal, by arbitrary extracting stack output, has been realized the raising of signal transfer rate and image quality.
Publication number is the utility model patent of CN201523431U, discloses the video montaging device that a kind of FPGA data processing module connects many framings buffer memory FIFO.Based on synchronous control signal, the FPGA data processing module is controlled each frame buffer FIFO and from corresponding video signal source, is received the digital image information of digital image information and output buffer memory, realizes the sequential control between each way video, and then realizes video-splicing.
Existing large screen display wall is all the display device of fixed resolution, if the specification of input video and display screen resolution is different, easily causes the appearance of screen slots, thereby affects globality and consistance that image shows.And available liquid crystal display and plasma display have a physics frame, consisting of combination, all have splicing gap in various degree, can't reach perfect visual effect.
The utility model content
The utility model provides a kind of LED splicer, to solve prior art in the situation that input video is different with the display screen resolution specification, easily causes screen slots to occur, and then affects globality and the conforming technical matters that image shows.
In order to solve above technical matters, the technical scheme that the utility model is taked is:
A kind of LED splicer, described LED splicer comprises input interface, input decoder, key panel, microcontroller, digital video processor, output coder, output interface, eeprom chip and storer; Described input interface connects described input decoder, described input decoder connects described digital video processor, described key panel connects described microcontroller, described microcontroller connects described digital video processor, described digital video processor connects described output coder, described output coder connects described output interface, and described eeprom chip is connected with described microcontroller, and described storer is connected with described digital video processor.
Be preferably, described input interface comprises DVI input interface, HDMI input interface, SDI input interface, YCbCr input interface, YPbPr input interface and VGA input interface.
Be preferably, described output coder comprises DVI scrambler and HDMI scrambler.
Be preferably, described output interface comprises DVI output interface and HDMI output interface.
Be preferably, described input decoder comprises video receiver, Video Decoder and analog to digital converter; Described video receiver connects described DVI input interface and described HDMI input interface; Described Video Decoder connects described SDI input interface and described YCbCr input interface; Described analog to digital converter connects described YPbPr input interface and described VGA input interface.
Be preferably, described DVI scrambler connects described DVI output interface; Described HDMI scrambler connects described HDMI output interface.
Be preferably, described storer is comprised of two DDR2 chips.
After adopting technique scheme, LED splicer described in the utility model has been broken through video image, transmitting chip necessary consistent limitation on resolution, thereby it is seamless spliced to have realized that image shows, the LED splicer can receive the signal of many general form, thereby output video, have applicability widely in real time, and the LED splicer has simple in structure, advantage easy and simple to handle, practical.
The accompanying drawing explanation
Fig. 1 is the structured flowchart of LED splicer described in the utility model.
Embodiment
For the purpose, technical scheme and the advantage that make the utility model embodiment is clearer, below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described.
As shown in Figure 1, the LED splicer is by input interface 1, input decoder 2, key panel 3, microcontroller 4, digital video processor 5, output coder 6, output interface 7, EEPROM(Electrically Erasable Programmable Read-Only Memory EEPROM (Electrically Erasable Programmable Read Only Memo)) chip 8 and storer 9 formations; Storer 9 is that the DDR2 chip by two same model forms, wherein the DDR2 chip is SDRAM storer (Synchronous Dynamic Random Access Memory, and the common storage of the DDR2 chip of two same model one two field picture synchronous DRAM).Input interface 1 comprises DVI input interface 11, HDMI input interface 12, SDI input interface 13, YCbCr input interface 14, YPbPr input interface 15 and VGA input interface 16, output coder 6 comprises DVI scrambler 61 and HDMI scrambler 62, output interface 7 comprises DVI output interface 71 and HDMI output interface 72, wherein said input interface 1 connects described input decoder 2, described input decoder 2 connects described digital video processor 5, described key panel 3 connects described microcontroller 4, described microcontroller 4 connects described digital video processor 5, described digital video processor 5 connects described output coder 6, described output coder 6 connects described output interface 7, described digital video processor 5 is connected with described storer 9, described microcontroller 4 connects described eeprom chip 8, described input decoder 2 comprises video receiver 21, Video Decoder 22 and analog to digital converter 23, wherein said video receiver 21 connects DVI input interface 11 and HDMI input interface 12, described Video Decoder 22 connects SDI input interface 13 and YCbCr input interface 14, and described analog to digital converter 23 connects YPbPr input interface 15 and VGA input interface 16, described output coder 6 consists of 6 identical scrambler groups, and each scrambler group comprises a DVI scrambler 61 and a HDMI scrambler 62, wherein each DVI scrambler 61 connects a DVI output interface 71, and each HDMI scrambler 62 connects a HDMI output interface 72, the corresponding output interface group of each group coding device, an output interface group comprises a DVI output interface 71 and a HDMI output interface 72, the output interface group is arranged in order, has 6 output interface groups.
According to the position of transmitting chip control area at display screen, according to Row Column, provide order, by serial number, give each transmitting chip.Because output interface 7 is arranged in order on splicer, to transmitting chip, giving serial number is that the convenient transmitting chip of describing is plugged on the output interface 7 of coupling.To transmitting chip, giving serial number is also conveniently on key panel 3, to input in order transmitting chip resolution, and different transmitting chips itself is concurrent working.
The button control information treatment circuit of digital video processor 5 is according to the resolution of connecting method and transmitting chip, thereby the actual displayed resolution that calculates large display screen calculates the line segment of cutting apart that ratio means.
According to what ratio meaned, cut apart line segment, the Video segmentation circuit of digital video processor 5 is cut apart video image, obtains cutting apart the sub-video image that rear multichannel is complete, and controls the sequential relationship between each way video.
According to the ratio of large display screen actual displayed resolution and image resolution ratio, digital video processor 5 calculate each way video in the horizontal direction with vertical direction on the multiple M and the N that amplify; The sub-video amplifying circuit of digital video processor 5 carries out M * N times of interpolation amplification to the sub-video image after cutting apart to be processed, and carries out edge treated, the image information of each way video after being amplified.
RGB sub-video image information after digital video processor 5 will be processed inputs to output coder 6.
After above-mentioned processing, the sub-video image is consistent with corresponding transmitting chip control area in large display screen, realizes seamless spliced.
6 pairs of video informations of output coder are further encoded, and the video information after encoding by corresponding output interface 7 exports outside transmitting chip to.
Outside transmitting chip exports vision signal on display screen to.
Each transmitting chip beyond the LED splicer, according to described being linked in sequence on an output interface group, alternatively is connected on DVI output interface 71 or HDMI output interface 72.
The described LED splicer of the utility model embodiment connects outside transmitting chip by output interface 7, and outside transmitting chip exports vision signal on display screen to.
The utility model embodiment key panel 3 provides the connecting method option, level is arranged 1 minute 2, level 1 minute 3, level 1 minute 4, level 1 minute 6,2*2 splicing, 3*2 splicing, first level 1 minute 6, left half vertical 1 minute 6, right half vertical 1 minute 6, vertical 1 minute 2, vertical 1 minute 3, vertical 1 minute 4, vertical 1 minute 6,2*3 splicing, second level 1 minute 6, left half level 1 minute 6, right half level 1 minute 6.
The utility model embodiment using method of described LED splicer below is provided.
The LED large display screen connecting method that the utility model embodiment connects is that the pixel of 1 minute 3, three DVI transmission cards of level is 1280*768,1280*768 successively, 800*768.Input picture is that resolution is the HDMI image of 1024*768.
The described LED splicer of the utility model embodiment is connected in large screen display system.Input picture access HDMI input interface 12.Three pixels are respectively to 1280*768,1280*768, and the DVI transmission cards of 800*768 access respectively the DVI output interface 71 of tri-output interface groups of the utility model embodiment.Utilize key panel 3,1 minute 3 connecting method of selection level, input 1280*768,1280*768,800*768 successively.
It is below the process that the described LED splicer of the utility model embodiment is processed image.
The button control information treatment circuit of digital video processor 5, according to the transmitting chip resolution of connecting method and order, calculates large display screen actual displayed resolution 3360*768.Cut apart line segment with initial end points and stop end points and mean, each point means with horizontal coordinate and vertical coordinate, horizontal coordinate means by end points left side image pixel and end points right side image pixel ratio, and vertical point coordinate image pixel ratio below image pixel above end points and end points means.Calculate with two cut-off rules that ratio means and be respectively (1280:1280+800,0:768; 1280:1280+800,768:0)=(8:13,0:1; 8:13,1:0), (1280+1280,800,0:768; 1280+1280,800,768:0)=(16:5,0:1; 16:5,1:0).
5 pairs of video images of digital video processor are cut apart, and obtain cutting apart the sub-video image that Hou Sanlu is complete, and its resolution is 390*768,390*768,244*768.
According to the large display screen actual displayed resolution that calculates and image resolution ratio ratio 3360:1024, the 768:768 in level, vertical direction, digital video processor 5 calculate each way video in the horizontal direction with vertical direction on the multiple that amplifies be 3.28 and 1; The sub-video amplifying circuit of digital video processor 5 carries out 3.28 * 1 times of interpolation amplifications processing, edge treated, each way video image information 1280*768,1280*768,800*768 after being amplified to the sub-video image after cutting apart.
Each way video image information after digital video processor 5 will be processed transfers to DVI scrambler 61.
61 pairs of video informations of DVI scrambler are further encoded, and the video information after encoding by corresponding DVI output interface 71 exports outside transmitting chip to.
LED splicer described in the utility model can cascade, for example the output interface 7 of the input interface of six LED splicers described in the utility model 1 and a LED splicer described in the utility model is connected, can realize the LED splicer of road input picture 36 road output images, because these seven LED splicers are identical, therefore need not consider to connect the signal stationary problem brought.
Finally it should be noted that: above embodiment only illustrates the technical solution of the utility model, is not intended to limit; Although with reference to previous embodiment, the utility model is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme that aforementioned each embodiment puts down in writing, or part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of each embodiment technical scheme of the utility model.
Claims (7)
1. a LED splicer, is characterized in that, described LED splicer comprises input interface, input decoder, key panel, microcontroller, digital video processor, output coder, output interface, eeprom chip and storer; Described input interface connects described input decoder, described input decoder connects described digital video processor, described key panel connects described microcontroller, described microcontroller connects described digital video processor, described digital video processor connects described output coder, described output coder connects described output interface, and described eeprom chip is connected with described microcontroller, and described storer is connected with described digital video processor.
2. LED splicer according to claim 1, is characterized in that, described input interface comprises DVI input interface, HDMI input interface, SDI input interface, YCbCr input interface, YPbPr input interface and VGA input interface.
3. LED splicer according to claim 2, is characterized in that, described output coder comprises DVI scrambler and HDMI scrambler.
4. LED splicer according to claim 3, is characterized in that, described output interface comprises DVI output interface and HDMI output interface.
5. LED splicer according to claim 4, is characterized in that, described input decoder comprises video receiver, Video Decoder and analog to digital converter; Described video receiver connects described DVI input interface and described HDMI input interface; Described Video Decoder connects described SDI input interface and described YCbCr input interface; Described analog to digital converter connects described YPbPr input interface and described VGA input interface.
6. LED splicer according to claim 5, is characterized in that, described DVI scrambler connects described DVI output interface; Described HDMI scrambler connects described HDMI output interface.
7. according to the arbitrary described LED splicer of claim 1-6, it is characterized in that, described storer is comprised of two DDR2 chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013204037082U CN203311817U (en) | 2013-07-08 | 2013-07-08 | LED splicer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013204037082U CN203311817U (en) | 2013-07-08 | 2013-07-08 | LED splicer |
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| Publication Number | Publication Date |
|---|---|
| CN203311817U true CN203311817U (en) | 2013-11-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2013204037082U Expired - Fee Related CN203311817U (en) | 2013-07-08 | 2013-07-08 | LED splicer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103971660A (en) * | 2014-05-20 | 2014-08-06 | 河北科技大学 | Multipath signal multi-screen splicing processing system |
| CN106448550A (en) * | 2016-12-27 | 2017-02-22 | 福州海天微电子科技有限公司 | LED screen parameter automatic identifying method and device |
-
2013
- 2013-07-08 CN CN2013204037082U patent/CN203311817U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103971660A (en) * | 2014-05-20 | 2014-08-06 | 河北科技大学 | Multipath signal multi-screen splicing processing system |
| CN106448550A (en) * | 2016-12-27 | 2017-02-22 | 福州海天微电子科技有限公司 | LED screen parameter automatic identifying method and device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131127 Termination date: 20150708 |
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| EXPY | Termination of patent right or utility model |