CN204180017U

CN204180017U - Low Drift Temperature CMOS pierce circuit

Info

Publication number: CN204180017U
Application number: CN201420693439.2U
Authority: CN
Inventors: 刘小淮; 陈远金; 张谨; 张紫乾; 白涛
Original assignee: China North Industries Group Corp No 214 Research Institute Suzhou R&D Center
Current assignee: China North Industries Group Corp No 214 Research Institute Suzhou R&D Center
Priority date: 2014-11-18
Filing date: 2014-11-18
Publication date: 2015-02-25
Anticipated expiration: 2024-11-18

Abstract

The utility model discloses a kind of Low Drift Temperature CMOS pierce circuit, after first, second, third resistance is connected successively, the end ground connection of the 3rd resistance, the top of the first resistance meets power vd D; First, second resistance connect the positive input being a little connected to operational amplifier altogether, the reverse input end of operational amplifier is connected to the positive input of comparator through the 4th resistance, the output of operational amplifier is connected to the reverse input end of comparator through the first switch; Second, third resistance connect the reverse input end being a little connected to comparator through second switch altogether; The positive input of comparator is connected with the drain electrode of NMOS tube through the 6th resistance; The output of comparator exports running clock CLK through a circuits for triggering positive feedback.The control realization Low Drift Temperature CMOS pierce circuit of comparator dual threshold, can vary with temperature by automatic monitoring comparator time of delay, reduces the temperature drift of CMOS oscillator.Circuit structure is simple, and temperature drift is low, and technique is portable strong.

Description

Low Drift Temperature CMOS pierce circuit

Technical field

The utility model relates to a kind of analog integrated circuit technology, especially a kind of temperature variant technology of frequency of oscillation reducing CMOS oscillator.

Background technology

In recent years, the electronic building brick microminiaturization of originating as electronic product sophisticated functions is required to extend to oscillator, excites the research to microminiature oscillator.The clock frequency that quartz crystal oscillator exports has good temperature and voltage stability, but its cost is high, and volume is large, is unfavorable for the system integration.Measured digital CMOS process realizes on chip clock oscillator, can reduction system volume, reduce power consumption, improve antijamming capability, increase the advantages such as the flexibility of reliability and use, have and important practical significance.

At present, the difficult point adopting CMOS technology to realize oscillator is that frequency of oscillation is easily with temperature, power supply and technique change.Yu Xiaofan, standing forest is put down " a kind of on chip clock oscillator with temperature and technological compensa tion ", adopts switched capacitor array compensate for process deviation on the impact of frequency of oscillation, but adds area and the control end of circuit.This circuit adopts LDO source of stable pressure on sheet to power to whole oscillator simultaneously, adds power consumption and the design complexities of system; " a kind of CMOS relaxation oscillation (CN103701411A) with temperature and technique self compensation characteristic proposes and a kind ofly not to compensate frequency of oscillation with the Low Drift Temperature reference current of technique change and the method for reference voltage Chinese patent, but the method have ignored the comparator temperature variant non-linear impact on frequency of oscillation time of delay.

Utility model content

Technical problem to be solved in the utility model is to provide a kind of Low Drift Temperature CMOS pierce circuit, the threshold voltage of sampling output frequency FEEDBACK CONTROL comparator is transformed by pulse generation and F-V (frequency-voltage), and then automatic monitoring comparator varies with temperature time of delay, reduce the temperature drift of CMOS oscillator.

For solving the problems of the technologies described above, the utility model provides a kind of Low Drift Temperature CMOS pierce circuit, it is characterized in that, after the first resistance, the second resistance, the 3rd resistance are connected successively, and the end ground connection of the 3rd resistance, the top of the first resistance meets power vd D; First resistance, the second resistance connect the positive input that an A is connected to operational amplifier altogether, the reverse input end of operational amplifier is connected to the positive input of comparator through the 4th resistance, the output of operational amplifier is connected to the reverse input end of comparator through the first switch; Second resistance, the 3rd resistance connect the reverse input end being a little connected to comparator through second switch altogether;

The positive input of comparator is connected with the drain electrode of NMOS tube through the 6th resistance, is also connected with the drain electrode of PMOS through the 5th resistance simultaneously; The source ground of NMOS tube, grid is connected to the output of the second inverter; The source electrode of PMOS is connected to power supply, and grid is connected to the output of the second inverter; The output of comparator exports running clock CLK through a circuits for triggering positive feedback.

The output C of described first operational amplifier is connected to the reverse input end of the first operational amplifier through the first capacitive feedback.

The positive input of described comparator with simultaneously through the second capacity earth.

Described circuits for triggering are made up of the first inverter, the second inverter, the first NOR gate and the second NOR gate; The input of the first inverter, the first input end of the first NOR gate link the output of comparator altogether, the output of the first inverter is connected to the second input of the second NOR gate, the output of the second NOR gate is connected to the second input of the second NOR gate, and the output of the first NOR gate is connected to the first input end of the second NOR gate; The output of the first NOR gate is connected to the input of the second inverter simultaneously, and the output of the second inverter exports running clock CLK.

The beneficial effect that the utility model reaches:

The utility model achieves the Low Drift Temperature of on-chip CMOS oscillator by pulse generation and frequency-voltage, and circuit structure is simple, and temperature drift is low, and technique is portable strong.

Accompanying drawing explanation

Fig. 1 is the utility model CMOS pierce circuit;

Fig. 2 (a) is the waveform (variations in temperature causes the increase of comparator time of delay) of B point and P (CLK);

Fig. 2 (b) is the waveform (variations in temperature causes the reduction of comparator time of delay) of B point and P (CLK).

Embodiment

Below in conjunction with accompanying drawing, the utility model is further described.Following examples only for clearly the technical solution of the utility model being described, and can not limit protection range of the present utility model with this.

1. circuit structure

The utility model embodiment 1 is as shown in Figure 1, Figure 2 shown in (a), Fig. 2 (b), and it is the control realization of device dual threshold based on the comparison.

After resistance R1, R2, R3 connect successively, the end ground connection of resistance R3, the top of resistance R1 meets power vd D, resistance R1, R2 connect the positive input that an A is connected to operational amplifier A 1 altogether, the output C of operational amplifier A 1 is connected to the reverse input end of operational amplifier A 1 through electric capacity C1, meanwhile, the reverse input end of operational amplifier A 1 is connected to the positive input B of comparator A2 through resistance R4, the output C of operational amplifier A 1 is connected to the reverse input end of comparator A2 through K switch 1.Resistance R2, R3 connect a D is connected to comparator A2 reverse input end through K switch 2 altogether.

The positive input B of comparator A2 with through electric capacity C2 ground connection, be connected with the drain electrode of NMOS tube M1 through resistance R6 simultaneously, be also connected with the drain electrode of PMOS M2 through resistance R5 simultaneously; The source ground of NMOS tube M1, grid is connected to the output P of inverter INV2.The source electrode of PMOS M2 is connected to power vd D, and grid is connected to the output P of inverter INV2.The output of comparator A2 is connected with the input of inverter INV1, the first input end of NOR gate NOR1 respectively, the output of inverter INV1 is connected to second input of NOR gate NOR2, the output of NOR gate NOR2 is connected to second input of NOR gate NOR1, and the output of NOR gate NOR1 is connected to the first input end of NOR gate NOR2.The output of NOR gate NOR1 is connected to the input of inverter INV2 simultaneously, and the output P of inverter INV2 exports running clock CLK.

Resistance R5 and electric capacity C2 determines the charging interval, and resistance R6 and electric capacity C2 determines discharge time.

The dual threshold voltage of comparator A2 is respectively VT+=VC, VT-=VD, and VT+>VT-.

Running clock CLK is low, K switch 1 conducting, and K switch 2 disconnects; Running clock CLK is high, and K switch 1 disconnects, K switch 2 conducting.

(1) when P point voltage CLK is low, K switch 1 conducting, power supply is charged to electric capacity C2 by resistance R5, B point voltage raises gradually, until VB>VC, CLK export as high, now K switch 2 conducting, electric capacity C2 starts electric discharge over the ground by resistance R6.B point voltage reduces gradually, until VB<VD, CLK export as low, and K switch 1 conducting.This process iterative cycles, CLK exports vibration square wave.

(2) trigger be made up of inverter INV1, INV2, NOR gate NOR1 and NOR2, forms positive feedback, accelerates comparator A2 upset.

(3) when variations in temperature causes comparator A2 to change time of delay, cycle of oscillation changes, then feedback threshold voltage VC changes, and then compensates cycle of oscillation.

The above is only preferred implementation of the present utility model; should be understood that; for those skilled in the art; under the prerequisite not departing from the utility model know-why; can also make some improvement and distortion, these improve and distortion also should be considered as protection range of the present utility model.

Claims

1. a Low Drift Temperature CMOS pierce circuit, is characterized in that, after the first resistance, the second resistance, the 3rd resistance are connected successively, and the end ground connection of the 3rd resistance, the top of the first resistance meets power vd D; First resistance, the second resistance connect the positive input that an A is connected to operational amplifier altogether, the reverse input end of operational amplifier is connected to the positive input of comparator through the 4th resistance, the output of operational amplifier is connected to the reverse input end of comparator through the first switch; Second resistance, the 3rd resistance connect the reverse input end being a little connected to comparator through second switch altogether;

2. Low Drift Temperature CMOS pierce circuit according to claim 1, it is characterized in that, the output C of described first operational amplifier is connected to the reverse input end of the first operational amplifier through the first capacitive feedback.

3. Low Drift Temperature CMOS pierce circuit according to claim 1, is characterized in that, the positive input of described comparator with simultaneously through the second capacity earth.

4. Low Drift Temperature CMOS pierce circuit according to claim 1, it is characterized in that, described circuits for triggering are made up of the first inverter, the second inverter, the first NOR gate and the second NOR gate; The input of the first inverter, the first input end of the first NOR gate link the output of comparator altogether, the output of the first inverter is connected to the second input of the second NOR gate, the output of the second NOR gate is connected to the second input of the second NOR gate, and the output of the first NOR gate is connected to the first input end of the second NOR gate; The output of the first NOR gate is connected to the input of the second inverter simultaneously, and the output of the second inverter exports running clock CLK.