CN204179071U - Wafer scale fingerprint recognition chip-packaging structure - Google Patents
Wafer scale fingerprint recognition chip-packaging structure Download PDFInfo
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- CN204179071U CN204179071U CN201420525192.3U CN201420525192U CN204179071U CN 204179071 U CN204179071 U CN 204179071U CN 201420525192 U CN201420525192 U CN 201420525192U CN 204179071 U CN204179071 U CN 204179071U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
A kind of wafer scale fingerprint recognition chip-packaging structure, comprise: substrate, described substrate comprises some induction chip districts, and described substrate has first surface and the second surface relative with described first surface, and the first surface in described induction chip district comprises induction zone; Be positioned at the cover layer of substrate first surface; Be positioned at the plug structure in the induction chip district of described substrate, one end of described plug structure is electrically connected with described induction zone, and the second surface of described substrate exposes the other end of described plug structure.Described wafer scale fingerprint recognition chip-packaging structure is simple, the sensitivity requirement of induction chip is reduced, apply more extensive.
Description
Technical field
The utility model relates to technical field of manufacturing semiconductors, particularly relates to a kind of wafer scale fingerprint recognition chip-packaging structure.
Background technology
Along with the progress of modern society, the importance of person identification and personal information security progressively receives the concern of people.Because somatic fingerprint has uniqueness and consistency, make fingerprint identification technology have fail safe good, reliability is high, feature easy to use, makes fingerprint identification technology be widely used in protecting the various fields of personal information security.And along with the development of science and technology, the information security issue of each electronic product is one of concern main points of technical development all the time.Especially for mobile terminal, such as mobile phone, notebook computer, dull and stereotyped computer, digital camera etc., the demand for Information Security is more outstanding.
The sensing mode of existing fingerprint recognition device comprises condenser type (Electric field) and inductance type, and user fingerprints by extracting user fingerprints, and is converted to signal of telecommunication output by fingerprint recognition device, thus obtains the finger print information of user.Concrete, as shown in Figure 1, Fig. 1 is the cross-sectional view of a kind of fingerprint recognition device of prior art, comprising: substrate 100; Be coupled in the fingerprint recognition chip 101 on substrate 100 surface; Be covered in the glass substrate 102 on described fingerprint recognition chip 101 surface.
For capacitance type fingerprint identification chip, in described fingerprint recognition chip 101, there is one or more capacitor plate.The epidermis pointed due to user or hypodermic layer have protruding ridge and the paddy of depression, when user points 103 contact described glass substrate 102 surface, described ridge is different to the distance of fingerprint recognition chip 101 from paddy, therefore, user points 103 ridges or the capacitance between paddy from capacitor plate is different, and fingerprint recognition chip 101 can obtain described different capacitance, and be translated into the output of the corresponding signal of telecommunication, and after fingerprint recognition device gathers the suffered signal of telecommunication, the finger print information of user can be obtained.
But, in existing fingerprint recognition device, higher to the sensitivity requirement of fingerprint recognition chip, the manufacture of fingerprint recognition device and application are restricted.
Utility model content
The problem that the utility model solves makes fingerprint recognition chip-packaging structure simple, the sensitivity requirement of induction chip is reduced, apply more extensive.
For solving the problem, the utility model provides a kind of wafer scale fingerprint recognition chip-packaging structure, comprise: substrate, described substrate comprises some induction chip districts, described substrate has first surface and the second surface relative with described first surface, and the first surface in described induction chip district comprises induction zone; Be positioned at the cover layer of substrate first surface; Be positioned at the plug structure in the induction chip district of described substrate, one end of described plug structure is electrically connected with described induction zone, and the second surface of described substrate exposes the other end of described plug structure.
Optionally, described plug structure comprises: the through hole being positioned at described substrate, and the top of described through hole is positioned at the second surface of described substrate; Be positioned at the insulating barrier on described through-hole side wall surface; Be positioned at the conductive layer on described surface of insulating layer and via bottoms surface, the conductive layer being positioned at described via bottoms is electrically connected with described induction zone; Be positioned at the welding resisting layer of described conductive layer surface, described welding resisting layer fills full described through hole.
Optionally, also comprise: the wiring layer and the metal coupling that are positioned at substrate second surface, described wiring layer is connected with described conductive layer and metal coupling, and described wiring layer and metal coupling are positioned at induction chip district.
Optionally, described plug structure comprises: the through hole being positioned at described substrate, and the top of described through hole is positioned at the second surface of described substrate; Be positioned at the insulating barrier on described through-hole side wall surface; Be positioned at the conductive plunger on described surface of insulating layer and via bottoms surface, described conductive plunger fills full described through hole.
Optionally, also comprise: the metal coupling being positioned at the conductive plunger top that described substrate second surface exposes.
Optionally, the first surface in described induction chip district also comprises the external zones surrounding described induction zone.
Optionally, be positioned at chip circuit and first weld pad of described external zones, described chip circuit is electrically connected with described induction zone and described first weld pad.
Optionally, one end of described plug structure is connected with described first weld pad.
Optionally, described substrate also comprises the Cutting Road district between adjacent induction chip district.
Optionally, also comprise: substrate; Be coupled in the induction chip of substrate surface, described induction chip has first surface and the second surface relative with described first surface, and the first surface of described induction chip comprises induction zone, and the second surface of described induction chip is positioned at substrate surface; Be positioned at the cover layer of described induction chip first surface; Be positioned at the plug structure of described induction chip, one end of described plug structure is electrically connected with described induction zone, the second surface of described induction chip exposes the other end of described plug structure, and the plug structure that described induction chip second surface exposes is connected with described substrate.
Optionally, described substrate has first surface, and the first surface of described substrate has some second weld pads, and described induction chip is coupled in the first surface of described substrate.
Optionally, the plug structure that described induction chip second surface exposes is electrically connected with described second weld pad.
Optionally, one end of described substrate has connecting portion, and described connecting portion is used for induction chip is electrically connected with external circuit.
Optionally, also comprise: the guard ring being positioned at substrate surface, described guard ring surrounds described induction chip and cover layer.
Optionally, also comprise: the shell surrounding described induction chip, cover layer and guard ring, described shell exposes the cover layer on surface, induction zone.
Optionally, also comprise: surround described induction chip and tectal shell, described shell exposes the cover layer on surface, described induction zone.
Compared with prior art, the technical solution of the utility model has the following advantages:
In wafer scale fingerprint recognition chip-packaging structure of the present utility model, in the induction chip district of described substrate, there is plug structure, one end of described plug structure is electrically connected with described induction zone, and the second surface of described substrate exposes the other end of described plug structure, therefore, namely can realize being electrically connected between described induction zone with the external circuit beyond induction chip district by described plug structure.And, described plug structure is positioned at described substrate, without the need to extra at described induction chip district and the conductor wire arranged between described external circuit for being electrically connected, therefore, follow-up with when independently induction chip district forms encapsulating structure, be conducive to formed encapsulating structure size is reduced.In addition, due to when follow-up formation encapsulating structure, conductor wire is connected without the need to being formed at the first surface of described substrate; therefore; can arrange described cover layer at the first surface of described substrate, described cover layer can directly and user's finger contacts, for the protection of described induction zone.Described wafer scale fingerprint recognition chip structure is simple, and follow-up being easy to is formed encapsulating structure with independently induction chip district.
Further, cover layer is positioned at the first surface of induction chip, and described cover layer is used for substituting traditional glass substrate, can directly and user's finger contacts, for the protection of described induction chip.And, compared to traditional glass substrate, described cover layer can thinner thickness, adopt described cover layer can reduce the distance of first surface to cover surface of induction chip, induction chip is made to be easy to user fingerprints be detected, correspondingly, described encapsulating structure reduces the requirement to induction chip sensitivity, makes the application of the encapsulating structure of fingerprint recognition chip more extensive.In addition, also there is plug structure in described induction chip, one end of described plug structure is electrically connected with described induction zone, the second surface of described induction chip exposes the other end of described plug structure, therefore by plug structure that described induction chip second surface exposes, described induction chip can be made to be fixed on described substrate surface, and the electrical connection that can realize between induction zone and substrate, described encapsulating structure is simple and be easy to assembling, the manufacturing cost of described encapsulating structure reduces, and output capacity improves.
Further, described substrate surface also has the described induction chip of encirclement and tectal guard ring.Described guard ring is used for carrying out electrostatic defending to described induction chip; the user fingerprints data accuracy avoiding induction zone to detect declines; or can eliminate the signal noise that induction chip exports, the signal of the data making induction chip detect and output is more accurate.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of a kind of fingerprint recognition device of prior art;
Fig. 2 and Fig. 3 is the cross-sectional view of the wafer scale fingerprint recognition chip-packaging structure of the utility model one embodiment;
Fig. 4 to Fig. 8 is the cross-sectional view of the wafer scale fingerprint recognition chip-packaging structure of another embodiment of the utility model.
Embodiment
As stated in the Background Art, in existing fingerprint recognition device, higher to the sensitivity requirement of fingerprint recognition chip, the manufacture of fingerprint recognition device and application are restricted.
Find through research; please continue to refer to Fig. 1; fingerprint recognition chip 101 surface coverage has glass substrate 102; described glass substrate 102 is for the protection of fingerprint recognition chip 101; and the finger 103 of user directly contacts with described glass substrate 102; therefore, in order to ensure that described glass substrate 102 has enough protective capabilities, the thickness of described glass substrate 102 is thicker.But, because the thickness of described glass substrate 102 is thicker, therefore require that fingerprint recognition chip 101 has higher sensitivity, to guarantee accurately to extract user fingerprints.But highly sensitive fingerprint recognition chip manufacturing difficulty is comparatively large, manufacturing cost is higher, then causes the application of fingerprint recognition chip and popularization to be restricted.
Concrete, continue for capacitance type fingerprint recognition means, when user's finger puts 103 when glass substrate 102 is surperficial, user points between the capacitor plate in 103 and fingerprint recognition chip 101 can form electric capacity; Wherein, described user point 103 and capacitor plate be the two poles of the earth of electric capacity, described glass substrate 102 is the dielectric between electric capacity the two poles of the earth.But, because the thickness of described glass substrate 102 is thicker, the capacitance that user is pointed between 103 and capacity substrate is larger, and the difference in height that user points between the ridge of 103 and paddy is less, therefore, capacitance between described ridge and capacitor plate, minimum relative to the difference between the capacitance between described paddy and capacitor plate, in order to the difference of described capacitance accurately can be detected, require that described fingerprint recognition chip 101 has higher sensitivity.
In order to solve the problem, the utility model proposes a kind of wafer scale fingerprint recognition chip-packaging structure.Wherein, cover layer is positioned at the first surface of induction chip, and described cover layer is used for substituting traditional glass substrate, can directly and user's finger contacts, for the protection of described induction chip.And, compared to traditional glass substrate, described cover layer can thinner thickness, adopt described cover layer can reduce the distance of first surface to cover surface of induction chip, induction chip is made to be easy to user fingerprints be detected, correspondingly, described encapsulating structure reduces the requirement to induction chip sensitivity, makes the application of the encapsulating structure of fingerprint recognition chip more extensive.In addition, also there is plug structure in described induction chip, one end of described plug structure is electrically connected with described induction zone, the second surface of described induction chip exposes the other end of described plug structure, therefore by plug structure that described induction chip second surface exposes, described induction chip can be made to be fixed on described substrate surface, and the electrical connection that can realize between induction zone and substrate, described encapsulating structure is simple and be easy to assembling, the manufacturing cost of described encapsulating structure reduces, and output capacity improves.
For enabling above-mentioned purpose of the present utility model, feature and advantage more become apparent, and are described in detail specific embodiment of the utility model below in conjunction with accompanying drawing.
Fig. 2 and Fig. 3 is the cross-sectional view of the wafer scale fingerprint recognition chip-packaging structure of the utility model one embodiment.
Please refer to Fig. 2, described wafer scale fingerprint recognition chip-packaging structure comprises:
Substrate 200, described substrate 200 comprises some induction chip districts 201, and described substrate 200 has first surface 210 and the second surface 220 relative with described first surface 210, and the first surface 210 in described induction chip district 201 comprises induction zone 211;
Be positioned at the cover layer 203 of substrate 200 first surface 210, the thickness of described cover layer 203 is less than 100 microns;
Be positioned at the plug structure 204 in the induction chip district 201 of described substrate 200, one end of described plug structure 204 is electrically connected with described induction zone 211, and the second surface 220 of described substrate 200 exposes the other end of described plug structure 204.
Below with reference to accompanying drawing, described wafer scale fingerprint recognition chip-packaging structure is described in detail.
Described substrate 200 is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, germanium on insulator (GOI) substrate silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, germanium on insulator (GOI) substrate; And described substrate 200 is full wafer wafer.
Described induction chip district 201 is for the formation of induction chip, and described induction chip is used for encapsulation, and the some induction chip districts 201 in described substrate 200 are in arrayed.In the present embodiment, described substrate 200 also comprises the Cutting Road district 202 between adjacent induction chip district 201, by cutting described Cutting Road district 202, can Shi Ge induction chip district 201 separate, formed induction chip.
Be positioned at the induction zone 211 of described induction chip district 201 first surface 210 for detecting and receive the finger print information of user; there is in described induction zone 211 capacitance structure for obtaining user fingerprints information or induction structure, and the cover layer 203 being positioned at described substrate 200 first surface 210 is for the protection of described induction zone 211.
In the present embodiment, in described induction zone 211, there is at least one capacitor plate, when user's finger is placed in cover layer 203 surface, described capacitor plate, cover layer 203 and user point formation capacitance structure, and described induction zone 211 can obtain user's finger surface ridge and the capacitance difference between paddy and capacitor plate, and export after described capacitance difference is processed by chip circuit, obtain user fingerprints data with this.
In the present embodiment, the first surface 210 in described induction chip district 201 also comprises the external zones 212 surrounding described induction zone 211, there is in described external zones 212 chip circuit and the first weld pad 213, described chip circuit is electrically connected with the capacitance structure in induction zone 211 or induction structure, processes for the signal of telecommunication exported capacitance structure or induction structure.
Described chip circuit is electrically connected with described induction zone 211 and described first weld pad 213, and one end of described plug structure 204 is connected with described first weld pad 213, thus the electrical connection realized between described plug structure 204 and described induction zone 211, again because the second surface 220 of described substrate 200 exposes described plug structure 204, therefore, by described plug structure 204, can make to realize being electrically connected between the induction zone 211 of substrate 200 first surface 210 with the external circuit beyond substrate 200.
Described plug structure 204 is positioned at substrate 200, and in the present embodiment, described plug structure 204 is positioned at the corresponding region of described external zones 212, and by electrical connection that namely described plug structure 204 can realize beyond induction zone 211 and substrate 200 between external circuit, therefore, when adopting that independently induction chip district 201 encapsulates, without the need to arranging extra conductive structure at the first surface 210 in described induction chip district 201, thus, can before the described substrate 200 of cutting, described cover layer 203 is covered at the first surface 210 of described substrate 200, described cover layer 203 is cut together with described substrate 200.
Because the first surface 210 of described substrate 200 is covered by described cover layer 203 completely, namely described cover layer 203 is except being positioned at surface, induction zone 211, external zones 212 and surface, Cutting Road district 202 can also be positioned at, the region area covered due to described cover layer 203 is larger, make the formation process of described cover layer 203 simple, and the technique forming described cover layer 203 can not cause damage to the first surface 210 in described induction chip district 201, further, the follow-up technique being undertaken encapsulating by independently induction chip district 201 is simple.
In addition, due to follow-up with when independently induction chip district 201 is formed encapsulating structure, without the need to arranging extra conductive structure at the first surface 210 in described induction chip district 201, therefore, the first surface 210 in described induction chip district 201 is smooth, namely the surface of described induction zone 211 and external zones 212 flushes, without the need to forming extra edge groove in described external zones 212, to be formed at the conductive structure that induction zone 211 connects, the simple and formation process of the structure making to be formed described wafer scale fingerprint recognition chip structure simplifies.
The material of described cover layer 203 is polymeric material, inorganic nano material or ceramic material.In the present embodiment, the material of described cover layer 203 is inorganic nano material, and described inorganic nano material comprises aluminium oxide or cobalt oxide; Described cover layer 203 can be formed with typography, spraying coating process or spin coating proceeding.
In another embodiment, the material of described cover layer 203 is polymeric material, and described polymeric material is epoxy resin, polyimide resin, benzocyclobutane olefine resin, polybenzoxazoles resin, polybutylene terephthalate, Merlon, PETG, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol or other suitable polymeric materials; Described cover layer 203 can be formed with typography, spraying coating process or spin coating proceeding.
In other embodiments, the material of described cover layer 203 is glass material or ceramic material, and described cover layer 203 is hard material, then described cover layer 203 needs the first surface being fixed on substrate 200 by adhesive linkage.Described adhesive linkage has viscosity, and described adhesive linkage can be capacitance plate glue.
The Mohs' hardness of described cover layer 203 is more than or equal to 8H.The hardness of described cover layer 203 is higher; therefore, even if the thinner thickness of described cover layer 203, described cover layer 203 is also enough to the induction zone 211 protecting induction chip 201; when user's finger is when described cover layer 203 surface is mobile, damage can not be caused to induction chip 201 surface.And, because the hardness of described cover layer 203 is higher, therefore described cover layer 203 is difficult to deformation occurs, even if user's finger presses is in described cover layer 203 surface, the thickness of described cover layer 203 is also difficult to change, thus ensure that the testing result accuracy of induction zone 211.
The dielectric constant of described cover layer 203 is more than or equal to 7.Because the dielectric constant of described cover layer 203 is comparatively large, make the electric isolution ability of described cover layer 203 comparatively strong, then the protective capability of described cover layer 203 pairs of induction zones 211 is stronger.
The thickness of described cover layer 203 is 20 microns ~ 200 microns.The thinner thickness of described cover layer 203, when user's finger is placed in described cover layer 203 surface, described finger reduces to the distance of induction zone 211, therefore, described induction zone 211 more easily detects the fingerprint that user points, thus reduces the highly sensitive requirement of induction chip 201.
Due to the thinner thickness of cover layer 203, and capacitance between user's finger with capacitor plate and the thickness of cover layer 203 are inversely proportional to, be directly proportional to the dielectric constant of cover layer 203, therefore, when the thinner thickness of cover layer 203, and dielectric constant larger time, user can be made to point capacitance between capacitor plate in the scope that induction zone 211 can be detected, avoid capacitance excessive or too small and the detection of induction zone 211 was lost efficacy.
And, when the thickness of cover layer 203 is in the scope of 20 microns ~ 200 microns, and dielectric constant in the scope being more than or equal to 7 time, the thickness of described cover layer 203 is increased, the then dielectric constant of described cover layer 203 also corresponding increase, user can be made to point capacitance between capacitor plate comparatively large, then described capacitance is easier to sensed district 211 and detects.
In the present embodiment, described plug structure 204 comprises: the through hole being positioned at described substrate 200, and the top of described through hole is positioned at the second surface 220 of described substrate 200; Be positioned at the insulating barrier 240 on described through-hole side wall surface; Be positioned at the conductive layer 241 on described insulating barrier 240 surface and via bottoms surface, the conductive layer 241 be positioned at bottom described through hole 241 is electrically connected with described induction zone 211; Be positioned at the welding resisting layer 242 on described conductive layer 241 surface, described welding resisting layer 242 fills full described through hole.
The material of described insulating barrier 240 is silica, silicon nitride, silicon oxynitride or high K dielectric material, and described insulating barrier 240 for carrying out electric isolution between conductive layer 241 and substrate 200; The material of described conductive layer 241 is metal, and described metal is one or more combinations in copper, tungsten, aluminium, titanium, silicon nitride, tantalum, tantalum nitride; In the present embodiment, described conductive layer 241 does not fill full described through hole, therefore, need to form welding resisting layer 242 on described conductive layer 241 surface, described welding resisting layer 242 fills full described through hole, and to form stable plug structure 204, described anti-welding material is polymeric material or inorganic insulating material, described polymeric material can be insulating resin, and described inorganic insulating material can be silica, silicon nitride or silicon oxynitride.
Described wafer scale fingerprint recognition chip structure also comprises: the wiring layer 221 and the metal coupling 222 that are positioned at substrate 200 second surface 220, described wiring layer 221 is connected with described conductive layer 241 and metal coupling 222, and described wiring layer 221 and metal coupling 222 are positioned at induction chip district 201.Described wiring layer 221 and metal coupling 222 can be electrically connected with the external circuit outside substrate 200 for making plug structure 204.
In another embodiment, please refer to Fig. 3, described plug structure 204 comprises: the through hole being positioned at described substrate 200, and the top of described through hole is positioned at the second surface 220 of described substrate 200; Be positioned at the insulating barrier 240 on described through-hole side wall surface; Be positioned at the conductive plunger 243 on described insulating barrier 240 surface and via bottoms surface, described conductive plunger 243 fills full described through hole.
The material of described insulating barrier 240 is silica, silicon nitride, silicon oxynitride or high K dielectric material, and described insulating barrier 240 for carrying out electric isolution between conductive plunger 243 and substrate 200; The material of described conductive layer 241 is metal, and described metal is one or more combinations in copper, tungsten, aluminium, titanium, silicon nitride, tantalum, tantalum nitride.
Described wafer scale fingerprint recognition chip structure also comprises: the metal coupling 223 being positioned at conductive plunger 243 top that described substrate 200 second surface 220 exposes.Described metal coupling 223 can be electrically connected with the external circuit outside substrate 200 for making plug structure 204.
To sum up, in the present embodiment, in the induction chip district of described substrate, there is plug structure, one end of described plug structure is electrically connected with described induction zone, and the second surface of described substrate exposes the other end of described plug structure, therefore, namely can realize being electrically connected between described induction zone with the external circuit beyond induction chip district by described plug structure.And, described plug structure is positioned at described substrate, without the need to extra at described induction chip district and the conductor wire arranged between described external circuit for being electrically connected, therefore, follow-up with when independently induction chip district forms encapsulating structure, be conducive to formed encapsulating structure size is reduced.In addition, due to when follow-up formation encapsulating structure, conductor wire is connected without the need to being formed at the first surface of described substrate; therefore; can arrange described cover layer at the first surface of described substrate, described cover layer can directly and user's finger contacts, for the protection of described induction zone.Described wafer scale fingerprint recognition chip structure is simple, and follow-up being easy to is formed encapsulating structure with independently induction chip district.
Fig. 4 to Fig. 8 is the cross-sectional view of the wafer scale fingerprint recognition chip-packaging structure of another embodiment of the utility model.
Please refer to Fig. 4, described wafer scale fingerprint recognition chip-packaging structure comprises:
Substrate 300;
Be coupled in the induction chip 301 on substrate 300 surface, described induction chip 301 has first surface 310 and the second surface 320 relative with described first surface 310, the first surface 310 of described induction chip 301 comprises induction zone 311, and the second surface 320 of described induction chip 301 is positioned at substrate 300 surface;
Be positioned at the cover layer 302 of described induction chip 301 first surface 310, the thickness of described cover layer 302 is less than 100 microns;
Be positioned at the plug structure 303 of described induction chip 301, one end of described plug structure 303 is electrically connected with described induction zone 311, the second surface 320 of described induction chip 301 exposes the other end of described plug structure 303, and the plug structure 303 that described induction chip 301 second surface 320 exposes is connected with described substrate 300.
Below with reference to accompanying drawing, described wafer scale fingerprint recognition chip-packaging structure is described in detail.
Described induction chip 301 is by carrying out cutting technique formation to wafer scale fingerprint recognition chip structure as shown in Figure 2 or Figure 3.Concrete, in wafer scale fingerprint recognition chip structure as shown in Figure 2 or Figure 3, there is in substrate 200 (as shown in Figure 2 or Figure 3) some induction chip districts 201 (as shown in Figure 2 or Figure 3) in arrayed, and between adjacent induction chip district 201, there is Cutting Road district 202 (as shown in Figure 2 or Figure 3), by cutting described Cutting Road district 202, some independently induction chip districts 201 can be obtained, the independently induction chip district 201 obtained i.e. induction chip 301 as shown in Figure 4.
In wafer scale fingerprint recognition chip structure as shown in Figure 2 or Figure 3, the first surface 210 of substrate 200 (as shown in Figure 2 or Figure 3) has cover layer 203 (as shown in Figure 2 or Figure 3), therefore, when cutting described Cutting Road district 202, described cover layer 203 is also cut simultaneously, forms cover layer 302 as shown in Figure 4.
Be positioned at the induction zone 311 of described induction chip 301 first surface 310 for detecting and receive the finger print information of user; there is in described induction zone 311 capacitance structure for obtaining user fingerprints information or induction structure, and the cover layer 302 being positioned at described induction chip 301 first surface 310 is for the protection of described induction zone 311.
In the present embodiment, in described induction zone 311, there is at least one capacitor plate, when user's finger is placed in cover layer 302 surface, described capacitor plate, cover layer 302 and user point formation capacitance structure, and described induction zone 311 can obtain user's finger surface ridge and the capacitance difference between paddy and capacitor plate, and export after described capacitance difference is processed by chip circuit, obtain user fingerprints data with this.
In the present embodiment, the first surface 310 of described induction chip 301 also comprises the external zones 312 surrounding described induction zone 311, there is in described external zones 312 chip circuit and the first weld pad 313, described chip circuit is electrically connected with the capacitance structure in induction zone 311 or induction structure, processes for the signal of telecommunication exported capacitance structure or induction structure.
Described chip circuit is electrically connected with described induction zone 311 and described first weld pad 313, and one end of described plug structure 303 is connected with described first weld pad 313, thus the electrical connection realized between described plug structure 303 and described induction zone 311, again because the second surface 320 of described substrate 300 exposes described plug structure 303, therefore, by described plug structure 303, can make to realize being electrically connected between the induction zone 311 of substrate 300 first surface 310 with the external circuit beyond substrate 300.
Described induction chip 301 is fixed on described substrate 300 surface, and described induction chip 301 can be electrically connected with other device or circuit by described substrate 300.In the present embodiment, the second surface 320 of described induction chip 301 exposes one end of described plug structure 303, and described induction chip 301 is fixed on described substrate 300 surface by described plug structure 303.
Described substrate 300 is rigid substrate or flexible base plate, can need to arrange the device of induction chip 301 or the demand of terminal, and adjusting described substrate 300 is rigid substrate or flexible base plate.In the present embodiment, described substrate 300 is rigid substrate, and described rigid substrate is PCB substrate, glass substrate, metal substrate, semiconductor substrate or polymeric substrates.
Described substrate 300 has first surface 330, the first surface 330 of described substrate 300 has some second weld pads 331 and wiring layer (not shown), described wiring layer is connected with described second weld pad 331, and described second weld pad 331 is for being connected with the chip circuit of induction chip 301 first surface 310, thus described induction chip 301 is made to be coupled in the first surface 330 of described substrate 300.
In the present embodiment, the plug structure 303 that described induction chip 301 second surface 320 exposes is welded in described second weld pad 331 surface, make described induction chip 301 be fixed on the first surface 330 of substrate 300, and the induction zone 311 being positioned at described induction chip 301 first surface 301 is electrically connected by the wiring layer of described plug structure 303 with substrate 300 surface.
In the present embodiment, one end of described substrate 300 has connecting portion 304, the material of described connecting portion 304 comprises electric conducting material, connecting portion 304 is electrically connected with described wiring layer, the induction zone 311 on described induction chip 301 surface can be electrically connected with external circuit or device, thus realize the transmission of the signal of telecommunication.
The material of described cover layer 302 is polymeric material, inorganic nano material or ceramic material.In the present embodiment, the material of described cover layer 302 is inorganic nano material, and described inorganic nano material comprises aluminium oxide or cobalt oxide; Described cover layer 302 can be formed with typography, spraying coating process or spin coating proceeding.
In another embodiment, the material of described cover layer 302 is polymeric material, and described polymeric material is epoxy resin, polyimide resin, benzocyclobutane olefine resin, polybenzoxazoles resin, polybutylene terephthalate, Merlon, PETG, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol or other suitable polymeric materials; Described cover layer 302 can be formed with typography, spraying coating process or spin coating proceeding.
The Mohs' hardness of described cover layer 302 is more than or equal to 8H.The hardness of described cover layer 302 is higher; therefore, even if the thinner thickness of described cover layer 302, described cover layer 302 is also enough to the induction zone 311 protecting induction chip 301; when user's finger is when described cover layer 302 surface is mobile, damage can not be caused to induction chip 301 surface.And, because the hardness of described cover layer 302 is higher, therefore described cover layer 302 is difficult to deformation occurs, even if user's finger presses is in described cover layer 302 surface, the thickness of described cover layer 302 is also difficult to change, thus ensure that the testing result accuracy of induction zone 311.
The dielectric constant of described cover layer 302 is more than or equal to 7.Because the dielectric constant of described cover layer 302 is comparatively large, make the electric isolution ability of described cover layer 302 comparatively strong, then the protective capability of described cover layer 302 pairs of induction zones 311 is stronger.
The thickness of described cover layer 302 is 20 microns ~ 200 microns.The thinner thickness of described cover layer 302, when user's finger is placed in described cover layer 302 surface, described finger reduces to the distance of induction zone 311, therefore, described induction zone 311 more easily detects the fingerprint that user points, thus reduces the highly sensitive requirement of induction chip 301.
Due to the thinner thickness of cover layer 302, and capacitance between user's finger with capacitor plate and the thickness of cover layer 302 are inversely proportional to, be directly proportional to the dielectric constant of cover layer 302, therefore, when the thinner thickness of cover layer 302, and dielectric constant larger time, user can be made to point capacitance between capacitor plate in the scope that induction zone 311 can be detected, avoid capacitance excessive or too small and the detection of induction zone 311 was lost efficacy.
And, when the thickness of cover layer 302 is in the scope of 20 microns ~ 200 microns, and dielectric constant in the scope being more than or equal to 7 time, the thickness of described cover layer 302 is increased, the then dielectric constant of described cover layer 302 also corresponding increase, user can be made to point capacitance between capacitor plate comparatively large, then described capacitance is easier to sensed district 311 and detects.
Described plug structure 303 is positioned at induction chip 301, and in the present embodiment, described plug structure 303 is positioned at the corresponding region of described external zones 312, and the electrical connection between the wiring layer that namely can be realized induction zone 311 and substrate 300 surface by described plug structure 303, therefore, when described induction chip 301 encapsulates, without the need to arranging extra conductive structure at the first surface 310 of described induction chip 301, make described fingerprint recognition chip-packaging structure simple, be conducive to the size of described encapsulating structure is reduced.
Because the first surface 310 of described induction chip 301 is covered by described cover layer 302 completely, after and substrate 300 surface fixing at described induction chip 301, first surface 310 again in induction chip 301 covers described cover layer 302, and the first surface 310 of technique to described induction chip 301 avoiding the formation of cover layer 302 causes damage.
In the present embodiment, described plug structure 303 comprises: the through hole being positioned at described induction chip 301, and the top of described through hole is positioned at the second surface 320 of described substrate 300; Be positioned at the insulating barrier 330 on described through-hole side wall surface; Be positioned at the conductive layer 331 on described insulating barrier 330 surface and via bottoms surface, the conductive layer 331 being positioned at described via bottoms is electrically connected with described induction zone 311; Be positioned at the welding resisting layer 332 on described conductive layer 331 surface, described welding resisting layer 332 fills full described through hole.
The material of described insulating barrier 330 is silica, silicon nitride, silicon oxynitride or high K dielectric material, and described insulating barrier 330 for carrying out electric isolution between conductive layer 331 and substrate 200; The material of described conductive layer 331 is metal, and described metal is one or more combinations in copper, tungsten, aluminium, titanium, silicon nitride, tantalum, tantalum nitride; In the present embodiment, described conductive layer 331 does not fill full described through hole, therefore, need to form welding resisting layer 332 on described conductive layer 331 surface, described welding resisting layer 332 fills full described through hole, and to form stable plug structure 303, described anti-welding material is polymeric material or inorganic insulating material, described polymeric material can be insulating resin, and described inorganic insulating material can be silica, silicon nitride or silicon oxynitride.
Described fingerprint recognition chip-packaging structure also comprises: the wiring layer 321 and the metal coupling 322 that are positioned at induction chip 301 second surface 320, and described wiring layer 321 is connected with described conductive layer 331 and convex 322 pieces of metal.Described wiring layer 321 and metal coupling 322 can be electrically connected with the external circuit outside substrate 300 for making plug structure 303.
In another embodiment, please refer to Fig. 5, described plug structure 303 comprises: the through hole being positioned at described induction chip 301, and the top of described through hole is positioned at the second surface 320 of described induction chip 301; Be positioned at the insulating barrier 330 on described through-hole side wall surface; Be positioned at the conductive plunger 333 on described insulating barrier 330 surface and via bottoms surface, described conductive plunger 333 fills full described through hole.
The material of described insulating barrier 330 is silica, silicon nitride, silicon oxynitride or high K dielectric material, and described insulating barrier 330 for carrying out electric isolution between conductive plunger 333 and induction chip 301; The material of described conductive plunger 333 is metal, and described metal is one or more combinations in copper, tungsten, aluminium, titanium, silicon nitride, tantalum, tantalum nitride.
Described fingerprint recognition chip-packaging structure comprises: the metal coupling 323 at conductive plunger 333 top that the second surface 320 being positioned at described induction chip 301 exposes.Described metal coupling 323 can be electrically connected with the external circuit outside substrate 300 for making plug structure 303.
In another embodiment, please refer to Fig. 6, described fingerprint recognition chip-packaging structure also comprises: the guard ring 305 being positioned at substrate 300 surface, and described guard ring 305 surrounds described induction chip 301 and cover layer 302.
The material of described guard ring 305 is metal, and described guard ring 305 is by described substrate 300 ground connection, and described guard ring 305 is fixed on the first surface 330 of substrate 300.
In the present embodiment, described guard ring 305 is positioned at described induction chip 301 and cover layer 302 around, and part guard ring 305 also to extend to above described cover layer 302 and exposes part of covering layer 305 surface be positioned on induction zone 311.In another embodiment, guard ring is only positioned at induction chip 301 and cover layer 302 around, and exposes described cover layer 302 surface completely.
The material of described guard ring 305 is metal, and described metal is copper, tungsten, aluminium, silver or golden.Described guard ring 305 is for carrying out electrostatic defending to described induction chip 301; Because described guard ring 305 is metal; described guard ring 305 can conduct electricity; when user's finger produces electrostatic when contacting cover layer 302; then first electrostatic charge can reach substrate 300 from described guard ring 305; thus avoid cover layer 302 to be punctured by excessive electrostatic potential, protect induction chip 301 with this, improve the accuracy of fingerprint detection; eliminate the signal noise that induction chip exports, the signal that induction chip is exported is more accurate.
In another embodiment, please refer to Fig. 7, described fingerprint recognition chip-packaging structure also comprises: the shell 306 surrounding described induction chip 301, cover layer 302 and guard ring 305, and described shell 306 exposes the cover layer 302 on surface, induction zone 311.Described shell 306 can, for being provided with the described device of fingerprint recognition chip or the shell of terminal, can also be the shell of the encapsulating structure of described fingerprint recognition chip.
In another embodiment, please refer to Fig. 8, described fingerprint recognition chip-packaging structure also comprises: the shell 307 surrounding described induction chip 301 and cover layer 302, and described shell 307 exposes the cover layer 302 on surface, described induction zone 311.Described shell 307 is for the protection of described induction chip 301 and cover layer 302; and; due in the present embodiment; described induction chip 301 is fixed on substrate 300 surface by described plug structure 303; therefore; described induction chip 301 can without the need to being fixed with capsulation material, and described shell 307 is for making electric isolution between described induction chip 301 and external environment condition.
In other embodiments; the plastic packaging layer surrounding described induction chip 301 can also be formed on described substrate 300 surface; described plastic packaging layer exposes the induction zone 311 of described induction chip 301; described plastic packaging layer for the protection of described induction chip 301, and makes electric isolution between induction chip 301 and external environment condition.
To sum up, in the present embodiment, cover layer is positioned at the first surface of induction chip, and described cover layer is used for substituting traditional glass substrate, can directly and user's finger contacts, for the protection of described induction chip.And, compared to traditional glass substrate, described cover layer can thinner thickness, adopt described cover layer can reduce the distance of first surface to cover surface of induction chip, induction chip is made to be easy to user fingerprints be detected, correspondingly, described encapsulating structure reduces the requirement to induction chip sensitivity, makes the application of the encapsulating structure of fingerprint recognition chip more extensive.In addition, also there is plug structure in described induction chip, one end of described plug structure is electrically connected with described induction zone, the second surface of described induction chip exposes the other end of described plug structure, therefore by plug structure that described induction chip second surface exposes, described induction chip can be made to be fixed on described substrate surface, and the electrical connection that can realize between induction zone and substrate, described encapsulating structure is simple and be easy to assembling, the manufacturing cost of described encapsulating structure reduces, and output capacity improves.
Although the utility model discloses as above, the utility model is not defined in this.Any those skilled in the art, not departing from spirit and scope of the present utility model, all can make various changes or modifications, and therefore protection range of the present utility model should be as the criterion with claim limited range.
Claims (16)
1. a wafer scale fingerprint recognition chip-packaging structure, is characterized in that, comprising:
Substrate, described substrate comprises some induction chip districts, and described substrate has first surface and the second surface relative with described first surface, and the first surface in described induction chip district comprises induction zone;
Be positioned at the cover layer of substrate first surface;
Be positioned at the plug structure in the induction chip district of described substrate, one end of described plug structure is electrically connected with described induction zone, and the second surface of described substrate exposes the other end of described plug structure.
2. wafer scale fingerprint recognition chip-packaging structure as claimed in claim 1, it is characterized in that, described plug structure comprises: the through hole being positioned at described substrate, and the top of described through hole is positioned at the second surface of described substrate; Be positioned at the insulating barrier on described through-hole side wall surface; Be positioned at the conductive layer on described surface of insulating layer and via bottoms surface, the conductive layer being positioned at described via bottoms is electrically connected with described induction zone; Be positioned at the welding resisting layer of described conductive layer surface, described welding resisting layer fills full described through hole.
3. wafer scale fingerprint recognition chip-packaging structure as claimed in claim 2, it is characterized in that, also comprise: the wiring layer and the metal coupling that are positioned at substrate second surface, described wiring layer is connected with described conductive layer and metal coupling, and described wiring layer and metal coupling are positioned at induction chip district.
4. wafer scale fingerprint recognition chip-packaging structure as claimed in claim 1, it is characterized in that, described plug structure comprises: the through hole being positioned at described substrate, and the top of described through hole is positioned at the second surface of described substrate; Be positioned at the insulating barrier on described through-hole side wall surface; Be positioned at the conductive plunger on described surface of insulating layer and via bottoms surface, described conductive plunger fills full described through hole.
5. wafer scale fingerprint recognition chip-packaging structure as claimed in claim 4, is characterized in that, also comprise: the metal coupling being positioned at the conductive plunger top that described substrate second surface exposes.
6. wafer scale fingerprint recognition chip-packaging structure as claimed in claim 1, it is characterized in that, the first surface in described induction chip district also comprises the external zones surrounding described induction zone.
7. wafer scale fingerprint recognition chip-packaging structure as claimed in claim 6, it is characterized in that, be positioned at chip circuit and first weld pad of described external zones, described chip circuit is electrically connected with described induction zone and described first weld pad.
8. wafer scale fingerprint recognition chip-packaging structure as claimed in claim 7, it is characterized in that, one end of described plug structure is connected with described first weld pad.
9. wafer scale fingerprint recognition chip-packaging structure as claimed in claim 1, it is characterized in that, described substrate also comprises the Cutting Road district between adjacent induction chip district.
10. wafer scale fingerprint recognition chip-packaging structure as claimed in claim 1, is characterized in that, also comprise:
Substrate;
Be coupled in the induction chip of substrate surface, described induction chip is by cutting described substrate and cover layer, make some induction chip districts mutually discrete and formed, described induction chip has first surface and the second surface relative with described first surface, the first surface of described induction chip comprises induction zone, and the second surface of described induction chip is positioned at substrate surface;
Be positioned at the cover layer of described induction chip first surface;
Be positioned at the plug structure of described induction chip, one end of described plug structure is electrically connected with described induction zone, the second surface of described induction chip exposes the other end of described plug structure, and the plug structure that described induction chip second surface exposes is connected with described substrate.
11. wafer scale fingerprint recognition chip-packaging structures as claimed in claim 10, it is characterized in that, described substrate has first surface, and the first surface of described substrate has some second weld pads, and described induction chip is coupled in the first surface of described substrate.
12. wafer scale fingerprint recognition chip-packaging structures as claimed in claim 11, it is characterized in that, the plug structure that described induction chip second surface exposes is electrically connected with described second weld pad.
13. wafer scale fingerprint recognition chip-packaging structures as claimed in claim 10, it is characterized in that, one end of described substrate has connecting portion, and described connecting portion is used for induction chip is electrically connected with external circuit.
14. wafer scale fingerprint recognition chip-packaging structures as claimed in claim 10, it is characterized in that, also comprise: the guard ring being positioned at substrate surface, described guard ring surrounds described induction chip and cover layer.
15. wafer scale fingerprint recognition chip-packaging structures as claimed in claim 14, it is characterized in that, also comprise: the shell surrounding described induction chip, cover layer and guard ring, described shell exposes the cover layer on surface, induction zone.
16. wafer scale fingerprint recognition chip-packaging structures as claimed in claim 10, is characterized in that, also comprise: surround described induction chip and tectal shell, described shell exposes the cover layer on surface, described induction zone.
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| CN201420525192.3U CN204179071U (en) | 2014-09-12 | 2014-09-12 | Wafer scale fingerprint recognition chip-packaging structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI604385B (en) * | 2016-09-14 | 2017-11-01 | Primax Electronics Ltd | Method for fabricating fingerprint identifying module and method for cutting fingerprint identifying sensing element |
| CN108346639A (en) * | 2017-09-30 | 2018-07-31 | 中芯集成电路（宁波）有限公司 | A kind of wafer scale system packaging method and encapsulating structure |
| CN108701208A (en) * | 2016-11-07 | 2018-10-23 | 深圳市汇顶科技股份有限公司 | Fingerprint recognition module and fingerprint recognition chip-packaging structure |
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2014
- 2014-09-12 CN CN201420525192.3U patent/CN204179071U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI604385B (en) * | 2016-09-14 | 2017-11-01 | Primax Electronics Ltd | Method for fabricating fingerprint identifying module and method for cutting fingerprint identifying sensing element |
| CN108701208A (en) * | 2016-11-07 | 2018-10-23 | 深圳市汇顶科技股份有限公司 | Fingerprint recognition module and fingerprint recognition chip-packaging structure |
| CN108346639A (en) * | 2017-09-30 | 2018-07-31 | 中芯集成电路（宁波）有限公司 | A kind of wafer scale system packaging method and encapsulating structure |
| CN108346639B (en) * | 2017-09-30 | 2020-04-03 | 中芯集成电路（宁波）有限公司 | Wafer level system packaging method and packaging structure |
| US10930617B2 (en) | 2017-09-30 | 2021-02-23 | Ningbo Semiconductor International Corporation | Packaging method and package structure of wafer-level system-in-package |
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