CN204142916U - Chip - Google Patents
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- Publication number
- CN204142916U CN204142916U CN201420587779.7U CN201420587779U CN204142916U CN 204142916 U CN204142916 U CN 204142916U CN 201420587779 U CN201420587779 U CN 201420587779U CN 204142916 U CN204142916 U CN 204142916U
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- Prior art keywords
- chip
- logic circuit
- circuit
- solidification
- wire jumper
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Abstract
The utility model relates to a kind of chip, comprise solidification memory circuit, switching logic circuit and chip logic circuit, described solidification memory circuit connects described switching logic circuit, described switching logic circuit connects described chip logic circuit, store solidification test vector in described solidification memory circuit, described solidification test vector is matched with described chip logic circuit.Adopt integrated solidification memory circuit and switching logic circuit together on the logical circuit of chip, save the peripheral board in conventional test methodologies, save vector location, cost-saving, shorten the test duration, and test environment miniaturization can be made.Solidification memory circuit and switching logic circuit and chip logic circuit are integrated in chip, realize directly transmitting in test vector electric signal to chip logic circuit carrying out chip testing, transfer rate enters chip logic circuit far above in classic method by chip pin.
Description
Technical field
The utility model relates to chip processor field, espespecially a kind of chip.
Background technology
Chip always designs according to function during design and technical parameter, the chip manufacturing and designing out, tests technical parameter when whether its performance reaches design always, such as electric current, voltage, resistance, sequential, the test vectors such as cycle.But this kind of digital circuit test of chip gets up very difficult, because including the logical circuit of thousands of logic gate compositions in chip, simple functional test in the past can not meet the test needs of chip, existing chip detecting method, as shown in Figure 1, build peripheral circuit to chip, the test vector electric signal produced by peripheral board is by the pin input chip of chip, reach the object of test chip, but there is following defect in such way:
One, need peripheral board to generate test vector electric signal, peripheral board increases development task, lengthens the chip development time;
Two, test vector electric signal is very restricted by chip pin speed, causes test vector electric signal to input the time of chip to be measured well beyond internal chip enable signal speed more than ten times orders of magnitude;
Three, there is the existence of peripheral board, and also needing, the outside coaming plate of vector location is set inculcate test vector, make it cannot realize test environment miniaturization.
Utility model content
The purpose of this utility model is the defect overcoming prior art, there is provided a kind of chip, solving the lengthening development time, the pin speed that exist in existing chip detecting method, to limit test vector electric signal input time of causing long and cannot realize the problem of test environment miniaturization.
The technical scheme realizing above-mentioned purpose is:
A kind of chip of the utility model, comprises
Chip logic circuit;
Solidification memory circuit, store solidification test vector, described solidification test vector is matched with described chip logic circuit;
For the switching logic circuit described solidification test vector being sent to described chip logic circuit and carrying out testing, described switching logic circuit connects described chip logic circuit and described solidification memory circuit.
Adopt integrated solidification memory circuit and switching logic circuit together on chip logic circuit, save the peripheral board in conventional test methodologies, save vector location, cost-saving, shorten the test duration, and test environment miniaturization can be made.Solidification memory circuit and switching logic circuit and chip logic circuit are integrated in chip, realize directly transmitting in test vector electric signal to chip logic circuit carrying out chip testing, transfer rate enters chip logic circuit far above in classic method by chip pin.
The further improvement of the utility model chip is, also comprise the chip wire jumper pin be connected between described switching logic circuit and described solidification memory circuit, control the break-make between described solidification memory circuit and described switching logic circuit by described chip wire jumper pin.
The further improvement of the utility model chip is, described chip also comprises the wire jumper control circuit being located at described chip periphery, chip wire jumper pin described in described wire jumper control circuit control linkage.
The further improvement of the utility model chip is, described wire jumper control circuit is provided with high level terminal and low level terminal, and described chip wire jumper pin connects described high level terminal and described low level terminal by a change-over switch.
The further improvement of the utility model chip is, described change-over switch controls described chip wire jumper pin and connects described high level terminal, describedly to state between switching logic circuit and described solidification memory circuit conducting and connect, described change-over switch controls described chip wire jumper pin and connects described low level terminal, disconnects between described switching logic circuit and described solidification memory circuit.
Accompanying drawing explanation
Fig. 1 is the structural representation of the method for testing of prior art chips;
Fig. 2 is the internal circuit configuration schematic diagram of the utility model chip;
Fig. 3 is the circuit diagram of switching logic circuit in the utility model chip.
Embodiment
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.
Consult Fig. 2, show the internal circuit configuration schematic diagram of the utility model chip.The utility model chip is provided with solidification memory circuit, switching logic circuit and chip logic circuit, compare in existing chip circuit structure and add solidification memory circuit and switching logic circuit structure, the test vector of chip logic circuit is adapted to by the storage of solidification memory circuit, again by switching logic circuit read test vector, and then test vector is sent to chip logic circuit, chip logic circuit is tested.Increase solidification memory circuit and switching logic circuit is adopted to test chip logic circuit, the exploitation of existing peripheral board can be reduced, save the chip development time, chip arranges wire jumper, controlling the transmission of test vector, generating peripheral board without the need to designing complicated vector; Test vector electric signal chip circuit storage inside and transmit, transfer rate is higher than more than ten when being transmitted by chip pin times; Only be provided with wire jumper in the periphery of chip, without the need to arranging peripheral board, the volume of huge compression peripheral board, can make full use of the test space.Below in conjunction with accompanying drawing, the utility model chip is described.
Consult Fig. 2, show the internal circuit configuration schematic diagram of the utility model chip, below in conjunction with Fig. 2, the utility model chip is described.
As shown in Figure 2, the utility model chip 10 comprises solidification memory circuit 101, switching logic circuit 102, chip logic circuit 103, chip wire jumper pin one 04 and functional mode input circuit 105.Store solidification test vector in solidification memory circuit 101, this solidification test vector is matched with chip logic circuit 103, for testing chip logic circuit 103, mainly carries out logic function test to the thousands of gate circuits in chip logic circuit 103.This solidification test vector is generated by chip logic circuit 103, when making solidification memory circuit 101, the solidification test vector of generation is stored in solidification memory circuit 101, solidification memory circuit 101 and chip logic circuit 103 is connected by switching logic circuit 102, solidification test vector in solidification memory circuit 101 is delivered in chip logic circuit 103, the logic function of chip is tested.
Chip wire jumper pin one 04 is located at chip 10 and extraneous intersection, can control its high level or low level by the wire jumper control circuit 106 of chip exterior.Chip wire jumper pin one 04, by switching logic circuit 102, controls to switch the break-make between chip logic circuit 102 and solidification memory circuit 101, and controls to switch the break-make between chip logic circuit 102 and functional mode input circuit 105.When switching logic circuit 102 is communicated with solidification memory circuit 101, chip 10 switches to test pattern, switching logic circuit 102, by the solidification test vector electric signal in solidification memory circuit 101, is sent to chip logic circuit 103, tests chip logic circuit 103.When switching logic circuit 102 connectivity capabilities pattern input circuit 105, chip 10 switches to functional mode, and switching logic circuit 102, by functional mode input electrical signal, is sent to chip logic circuit 103, is operated in functional mode to chip logic circuit 103.
The utility model chip also comprises wire jumper control circuit 106, this wire jumper control circuit 106 connects chip wire jumper pin one 04, this wire jumper control circuit 106 is provided with high level terminal and low level terminal, wire jumper control circuit 106 is by connecting high level terminal and low level terminal, and control chip wire jumper pin one 04 is communicated with high level terminal or low level terminal.
Illustrate, such as, wire jumper control circuit 106 control chip wire jumper pin one 04 connects high level terminal, chip wire jumper pin one 04 is made to be in high level, between switching logic circuit 102 and solidification memory circuit 101, conducting connects, switching logic circuit 102, by the solidification test vector electric signal in solidification memory circuit 101, sends chip logic circuit 103 to and tests; Wire jumper control circuit 106 control chip wire jumper pin one 04 connects low level terminal, chip wire jumper pin one 04 is made to be in low level, disconnect between switching logic circuit 102 and solidification memory circuit 101, be communicated with between functional mode input circuit 105 with switching logic circuit 102, switching logic circuit 102 makes chip logic circuit 103 be in functional mode.
Consult Fig. 3, what show switching logic circuit 102 can a kind of scheme of realizing circuit.As shown in Figure 3, wherein S is selecting side, A and B is respectively input, and Y exports.The Boolean expression of its Y is:
when S is low level, namely 0 time,
namely Y equals A, and circuit disconnects B and connects between Y, and Y is switched to A.When S is high level, namely 1 time,
namely Y equals B, and circuit disconnects A and connects between Y, and Y is switched to B.In the present embodiment, solidification memory circuit 101 and functional mode input circuit 105 can be connected by corresponding for A with B end, Y end connects chip logic circuit 103, S selecting side connects chip wire jumper pin one 04, just achieves the chip with self-test function, when this chip normally works, connectivity capabilities pattern input circuit and chip logic circuit, during test, be communicated with solidification memory circuit and chip logic circuit, the selection of above-mentioned connection is realized by switching logic circuit and chip wire jumper pin.
The beneficial effect of the utility model chip is:
Adopt the solidification memory circuit, switching logic circuit and the chip logic circuit that integrate, realize transmitting solidification test vector electric signal to chip logic circuit, very big reduction peripheral board exploitation, the test that wire jumper gets final product control chip logical circuit is arranged to chip, saves the chip development time;
Solidification test vector electric signal transmits between chip internal circuits, and transfer rate enters chip logic circuit far above by chip pin, speed more than high ten times;
Only there is wire jumper the periphery of chip, and 26S Proteasome Structure and Function is simple, can the peripheral volume of huge compression, makes chip to make full use of the test space;
The utility model chip has and saves peripheral board, vector location, cost-saving, shortens the advantages such as test duration.
Below embodiment has been described in detail the utility model by reference to the accompanying drawings, and those skilled in the art can make many variations example to the utility model according to the above description.Thus, some details in embodiment should not formed restriction of the present utility model, the utility model by the scope that defines using appended claims as protection domain of the present utility model.
Claims (4)
1. a chip, is characterized in that, comprising:
Chip logic circuit;
Solidification memory circuit, store solidification test vector, described solidification test vector is matched with described chip logic circuit;
For the switching logic circuit described solidification test vector being sent to described chip logic circuit and carrying out testing, described switching logic circuit connects described chip logic circuit and described solidification memory circuit; And
Be connected to the chip wire jumper pin between described switching logic circuit and described solidification memory circuit, control the break-make between described solidification memory circuit and described switching logic circuit by described chip wire jumper pin.
2. chip as claimed in claim 1, it is characterized in that, described chip also comprises the wire jumper control circuit being located at described chip periphery, chip wire jumper pin described in described wire jumper control circuit control linkage.
3. chip as claimed in claim 2, it is characterized in that, described wire jumper control circuit is provided with high level terminal and low level terminal, and described chip wire jumper pin connects described high level terminal and described low level terminal by a change-over switch.
4. chip as claimed in claim 3, it is characterized in that, described change-over switch controls described chip wire jumper pin and connects described high level terminal, and between described switching logic circuit and described solidification memory circuit, conducting connects; Described change-over switch controls described chip wire jumper pin and connects described low level terminal, disconnects between described switching logic circuit and described solidification memory circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420587779.7U CN204142916U (en) | 2014-10-11 | 2014-10-11 | Chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420587779.7U CN204142916U (en) | 2014-10-11 | 2014-10-11 | Chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204142916U true CN204142916U (en) | 2015-02-04 |
Family
ID=52419596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420587779.7U Expired - Fee Related CN204142916U (en) | 2014-10-11 | 2014-10-11 | Chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204142916U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104316866A (en) * | 2014-11-20 | 2015-01-28 | 上海华力创通半导体有限公司 | Testing structure and method for chip |
| CN112782551A (en) * | 2019-11-04 | 2021-05-11 | 珠海零边界集成电路有限公司 | Chip and test system of chip |
-
2014
- 2014-10-11 CN CN201420587779.7U patent/CN204142916U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104316866A (en) * | 2014-11-20 | 2015-01-28 | 上海华力创通半导体有限公司 | Testing structure and method for chip |
| CN112782551A (en) * | 2019-11-04 | 2021-05-11 | 珠海零边界集成电路有限公司 | Chip and test system of chip |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150204 Termination date: 20161011 |