CN104316866B - The test structure and method of testing of chip - Google Patents
The test structure and method of testing of chip Download PDFInfo
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- CN104316866B CN104316866B CN201410667831.4A CN201410667831A CN104316866B CN 104316866 B CN104316866 B CN 104316866B CN 201410667831 A CN201410667831 A CN 201410667831A CN 104316866 B CN104316866 B CN 104316866B
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Abstract
The present invention relates to a kind of method of testing of chip, including：Test vector is generated according to the logic function of processing unit in chip；Test vector solidification is stored in the chip；The processing unit is controlled to be switched in mode of operation and test pattern by handover operation；In the test pattern, transfer the test vector and the test vector is sent to the processing unit, and then control the test of the processing unit progress logic function.Memory cell and switching logic unit are solidified using core Embedded, the peripheral board in conventional test methodologies is saved, saves vector location, it is cost-effective, shorten the testing time.
Description
Technical field
The present invention relates to chip processor field, the test structure and method of testing of espespecially a kind of chip.
Background technology
Chip is the chip for manufacturing and designing out come what is designed according to function during design and technical parameter, is always tested
Whether its performance reaches technical parameter during design, such as the test vector such as electric current, voltage, resistance, sequential, cycle.But chip
This kind of digital circuit test get up it is extremely difficult, because including the logic circuit of thousands of individual gates compositions in chip,
Simple functional test can not meet the test needs of chip, existing chip detecting method, as shown in figure 1, sharp in the past
Software 101 is produced with vector and generates test vector, test vector is write in peripheral board 102, test vector passes through chip pipe again
Pin inputs chip 103 so that chip 103 enters test module, and chip logic 104 is tested, and reaches test chip 103
Purpose, but following defect be present in such way：
First, need peripheral board to generate test vector electric signal, peripheral board increase development task, lengthen the chip development time；
2nd, test vector electric signal is very restricted by chip pin speed, causes test vector electric signal defeated
Enter time of chip to be measured well beyond more than ten times orders of magnitude of chip internal signal speed；
3rd, there is the presence of peripheral board, and also need to set the outside coaming plate implantation test vector of vector location so that its
It can not realize that test environment minimizes.
The content of the invention
The defects of it is an object of the invention to overcome prior art, there is provided the test structure and method of testing of a kind of chip,
Solve test vector electric signal caused by lengthening development time, pin rate limitation present in existing chip detecting method to input
Overlong time and can not realize test environment miniaturization the problem of.
Realizing the technical scheme of above-mentioned purpose is：
A kind of method of testing of chip of the present invention, including：
According to the logic function of processing unit in chip, production test is vectorial；
Test vector solidification is stored in the chip；
The processing unit is controlled to be switched in mode of operation and test pattern by handover operation；In the survey
In die trial formula, transfer the test vector and the test vector is sent to the processing unit, and then control the processing
Unit carries out the test of the logic function.
Test vector is stored in chip, when carrying out logic function test to chip, directly transfers test vector,
The peripheral board in conventional test methodologies is saved, avoids the exploitation of peripheral board, saves vector location, it is cost-effective,
Shorten the testing time, and test environment can be minimized.Using integration testing vector in chip, realize that directly transmission is surveyed
Try vectorial electric signal and chip testing is carried out into processing unit, transfer rate is higher than in conventional method and enters core by chip pin
More than ten times of piece logic circuit, greatly shorten the testing time of chip.
Chip of the present invention method of testing further improvement is that, control the processing unit to exist by handover operation
Switched in mode of operation and test pattern, including：The external control signal outside the chip is received, and according to institute
State external signal and switch over operation.
Chip of the present invention method of testing further improvement is that, the external signal includes high level signal and low electricity
Ordinary mail number, when the external signal is high level signal, the processing unit is controlled to be in test pattern, when the outside letter
When number being low level signal, the processing unit is controlled to be in mode of operation.
A kind of test structure of chip of the present invention, including：
Processing unit in chip, there is logic function to be achieved；
Solidification memory cell in the chip, the solidification memory cell, which contains, adapts to the logic work(
The test vector of energy；And
Switching logic unit in the chip, the switching logic unit control connect the processing unit and institute
Solidification memory cell is stated, the switching logic unit is used to control the processing unit to carry out in mode of operation and test pattern
Switching；In the test pattern, the switching logic unit reads the test vector in the solidification memory cell, and transmits
To the processing unit, and then the processing unit is controlled to carry out logic function test.
Solidification memory cell storage test vector is set on chip, and is controlled by switching logic unit and completes chip
Test, saves the peripheral board in conventional test methodologies, avoids the exploitation of peripheral board, save vector location, saves
Cost, shorten the testing time, and test environment can be minimized.Memory cell and switching are solidified using core Embedded
Logic unit, realize that directly transmission test vector electric signal carries out chip testing into processing unit, transfer rate is higher than tradition
More than ten times in method by chip pin into chip logic circuit, greatly shorten the testing time of chip.
Chip of the present invention test structure further improvement is that, the switching logic unit includes functional module and survey
Die trial block, the switching logic unit realize control by switching the working condition of the functional module and the test module
The processing unit switches in mode of operation and test pattern.
Chip of the present invention test structure further improvement is that, in addition to wire jumper circuit board, the wire jumper circuit board
High level end and low level end are provided with, the switching logic unit is by switching the height on the switch connection wire jumper circuit board
Level terminal and low level end, the switching logic unit is controlled to connect the high level end or the low level by switching switch
End, realizes the switching of the working condition between the functional module in the switching logic unit and the test module.
Chip of the present invention test structure further improvement is that, when the switching switch connects the high level end,
Test module in the switching logic unit is in running order, and then controls the processing unit to be in test pattern；Institute
When stating the switching switch connection low level end, the functional module in the switching logic unit is in running order, and then controls
Make the processing unit and be in mode of operation.
Brief description of the drawings
Fig. 1 is the structural representation of the method for testing of prior art chips；
Fig. 2 is the schematic diagram of the test structure of chip of the present invention；And
Fig. 3 is the circuit diagram of switching logic unit in chip of the present invention.
Embodiment
The invention will be further described with specific embodiment below in conjunction with the accompanying drawings.
Refering to Fig. 2, it is shown that the schematic diagram of the test structure of chip of the present invention.The test structure of chip of the present invention and test
Method, solidification memory cell is additionally arranged in the chips and is used to store test vector, is controlled by switching logic unit and completes chip
Test, the switching logic unit includes functional module and test module, passes through working condition between functional module and test module
Switching, realize switching of the processing unit between mode of operation and test pattern.Switching logic unit passes through handoff functionality module
Work, control chip processing unit be in mode of operation, realizes that the processing unit of chip normally works operation, realizes and handle singly
The design logic function of member；Switching logic unit is worked by switch test module, and the processing unit of control chip is in test
Pattern, the test of logic function is carried out, the test vector that the test module is read in solidification memory cell transmits test vector
To processing unit, and control process unit carries out the test of logic function.The test structure and method of testing of the chip of the present invention,
The exploitation of existing peripheral board can be reduced, saves the chip development time, wire jumper circuit board is set on chip, control switching is patrolled
The work switching of the functional module and test module of unit is collected, the vector generation peripheral board without complex designing；Test vector exists
The storage inside of chip and transmission, transfer rate are higher than more than ten times when being transmitted by chip pin；In the periphery of chip only
Provided with wire jumper, without setting peripheral board, the volume of huge compression peripheral board, the test space can be made full use of.With reference to attached
Figure illustrates to the test structure and method of testing of chip of the present invention.
Refering to Fig. 2, it is shown that the schematic diagram of the test structure of chip of the present invention, with reference to Fig. 2, to chip of the present invention
Test structure illustrates.
As shown in Fig. 2 the test structure of chip of the present invention includes processing unit 201, the solidification storage being located in chip 20
Unit 202 and switching logic unit 203, processing unit 201 have logic function to be achieved, solidify in memory cell 202
It is stored with the test vector for the logic function for adapting to processing unit 201, the control connection processing unit of switching logic unit 203
201 are carried out with solidification memory cell 202, the control process unit 201 of switching logic unit 203 in mode of operation and test pattern
Switching, in test pattern, switching logic unit 203 transfers the test vector of the solidification memory storage of memory cell 202, and sends to
Processing unit 201, control process unit 201 carry out logic function test.
Include functional module 2031 and test module 2032 in the switching logic unit 203, switching logic unit 203 is logical
The switching of the working condition of control function module 2031 and test module 2032 is crossed, realizes the mode of operation to processing unit 201
With the handover operation of test pattern.The control process unit 201 of functional module 2031 is in mode of operation, realizes processing unit
201 logic functions of itself, the control process unit 201 of test module 2032 are in test pattern, and the test module 2032 is read
The test vector in solidification memory cell 202 is taken, and the test vector of reading is sent to processing unit 201, and then at control
Manage unit 201 and carry out logic function test.
The test structure of chip of the present invention also includes wire jumper circuit board 21, and wire jumper circuit board 21 is provided with high level end 211
With low level end 212, switching logic unit 203 is by switching the He of high level end 211 on 213 tie jumper circuit boards 21 of switch
Low level end 212, the control switching logic unit 203 of switching switch 213 connect high level end 211 or switching logic unit
203 connection low level ends 212, when the control switching logic unit 203 of switching switch 213 connects high level end 211, switch logic list
Test module 2032 in member 203 works, and control process unit 201 is in test pattern, and the test module 2032 reads solidification
Test vector in memory cell 202, the test vector of reading is sent to processing unit 201, and then control process unit 201
Carry out logic function test.When the control switching logic unit 203 of switching switch 213 connects low level end 212, switching logic unit
Functional module 2031 in 203 works, and control process unit 201 is in mode of operation, the control process list of functional module 2031
Member 201 is in running order, realizes the logic function of itself of processing unit 201.Functional module is realized by switching switch 213
The switching of working condition between 2031 and test module 2032.As shown in Figure 3, it is shown that switch logic list in chip of the present invention
The circuit diagram of member.Wherein S is selection end, and A and B are respectively to input, and Y is output.Its Y Boolean expression is：When S is low level, i.e., when 0,
That is Y is equal to A, and circuit disconnects B and connected between Y, and Y is switched into A.When S is high level, i.e., when 1,That is Y is equal to B, and circuit disconnects A and connected between Y, and by Y
It is switched to B.In the present embodiment, by A ends linkage function module 2031, by B ends connecting test module 2032, Y ends junction
Unit 201 is managed, S selections end connection switching switch 213, the low and high level at the control S selections end of switching switch 213, is controlled defeated
Go out to hold Y linkage functions module 2031 or test module 2032, realize the work of handoff functionality module 2031 and test module 2032
Make state, and then the processing unit 201 for controlling chip is in mode of operation or test pattern.
The method of testing of chip of the present invention is illustrated below.
The method of testing of chip of the present invention includes：
As shown in Fig. 2 generating test vector according to the logic function of processing unit in chip 201, processing unit 201 has
There is logic function to be achieved, the test vector is matched with the logic function；
Test vector solidification is stored in chip, solidification memory cell 202 can be set on chip 20, for storing this
Test vector；
Switched over by handover operation and control process unit 201 in mode of operation and test pattern；In test mould
In formula, transfer test vector and test vector is sent to processing unit 201, and then control process unit 201 carries out logic work(
The test of energy.Switching logic unit 203 can be set on chip 20, to processing unit 201 between mode of operation and test module
Switching is controlled, and switching logic unit 203 is controlled into connection solidification memory cell 202 and processing unit 201, switch logic list
First 203 control process units 201 switch in mode of operation and test pattern, and control process unit 201 is switched to test
During pattern, the test vector that switching logic unit 203 is transferred in solidification memory cell 202 sends processing unit 201 to, and controls
Processing unit 201 carries out logic function test.
Wherein：Switched over by handover operation and control process unit in mode of operation and test pattern, including：Connect
The external control signal outside chip is received, and operation is switched over according to external signal.The external signal includes high level
Signal and low level signal, when external signal is high level signal, control process unit is in test pattern, works as external signal
For low level signal when, control process unit is in mode of operation.The He of functional module 2031 is set in switching logic unit 203
Test module 2032, by the handoff functionality module 2031 of switching logic unit 203 and the working condition of test module 2032, realize
Switching of the processing unit 201 between mode of operation and test pattern.Control the He of functional module 2031 in switching logic unit 203
The switching of the working condition of test module 2032, wire jumper circuit board 21, the wire jumper circuit board 21 can be set in the outside of chip 20
On be provided with high level end 211 and low level end 212, switching logic unit 203, which passes through, switches 213 tie jumper circuit boards of switch
High level end 211 or low level end 212 on 21, the control switching logic unit 203 of switching switch 213 connect high level end 211,
Test module 2032 in switching logic unit 203 works, and the test module 2032 reads the test in solidification memory cell 202
Vector, and the test vector of reading is sent to processing unit 201, and then control process unit 201 carries out logic function test.
Switch and switch the 213 control connection low level ends 212 of switching logic units 203, the functional module 2031 in switching logic unit 203
Work, the control process unit 201 of functional module 2031 are in mode of operation, realize the logic function of itself of processing unit 201.
The test structure of chip of the present invention and having the beneficial effect that for method of testing：
Using solidification memory cell and switching logic unit is integrated on chip, realize that the processing unit on chip can be easily
Logic function test is carried out, the peripheral board in conventional test methodologies is saved, avoids the exploitation of peripheral board, save vector and deposit
Storage unit, it is cost-effective, shorten the testing time, and test environment can be minimized.
Memory cell and switching logic unit are solidified using core Embedded, realizes and directly transmits test vector electric signal extremely
Chip testing is carried out in processing unit, transfer rate is higher than in conventional method and enters the ten of chip logic circuit by chip pin
More than times, the testing time of chip is greatly shortened.
The triggering control of switching logic unit only needs the low and high level of wire jumper circuit board to control, simple in construction, operation side
Just.
The present invention is described in detail above in association with accompanying drawing embodiment, those skilled in the art can be according to upper
State and bright many variations example is made to the present invention.Thus, some details in embodiment should not form limitation of the invention, this
Invention will be used as protection scope of the present invention using the scope that appended claims define.
Claims (4)
- A kind of 1. method of testing of chip, it is characterised in that including：Test vector is generated according to the logic function of processing unit in chip；Test vector solidification is stored in the chip；The processing unit is controlled to be switched in mode of operation and test pattern by handover operation, including：Receive and External control signal from outside the chip, and operation is switched over according to the external control signal；In the test mould In formula, transfer the test vector and the test vector is sent to the processing unit, and then control the processing unit Carry out the test of the logic function；Also include：In setting switching logic unit on the chip, by the switching logic unit to the processing unit in mode of operation Switch between test pattern and be controlled, functional module and test module are set in the switching logic unit；The switching logic unit is passed through into the high level on the switching switch tie jumper circuit board of the chip exterior End or low level end, when the switching switch control switching logic unit connection high level end, in the switching logic unit Test module work, the test module reads the test vector and is sent to the processing unit；When the switching is opened When closing control switching logic unit connection low level end, the functional module work in switching logic unit, control the processing single Member is in mode of operation.
- 2. the method for testing of chip as claimed in claim 1, it is characterised in that the external signal include high level signal and Low level signal, when the external signal is high level signal, the processing unit is controlled to be in test pattern, when described outer When portion's signal is low level signal, the processing unit is controlled to be in mode of operation.
- A kind of 3. test structure of chip, it is characterised in that including：Processing unit in chip, there is logic function to be achieved；Solidification memory cell in the chip, the solidification memory cell, which contains, adapts to the logic function Test vector；AndSwitching logic unit in the chip, switching logic unit control connect the processing unit and described solid Change memory cell, the switching logic unit is used to control the processing unit to be cut in mode of operation and test pattern Change；In the test pattern, the switching logic unit reads the test vector in the solidification memory cell, and is sent to The processing unit, and then control the processing unit to carry out logic function test；The switching logic unit includes function mould Block and test module, the switching logic unit are real by switching the working condition of the functional module and the test module The processing unit is now controlled to be switched in mode of operation and test pattern；The test structure of the chip also includes wire jumper Circuit board, the wire jumper circuit board are provided with high level end and low level end, and the switching logic unit is connected by switching switch The high level end on the wire jumper circuit board and low level end are connect, controls the switching logic unit to connect institute by switching switch State high level end or the low level end, realize the functional module in the switching logic unit and the test module it Between working condition switching.
- 4. the test structure of chip as claimed in claim 3, it is characterised in that the switching switch connects the high level end When, the test module in the switching logic unit is in running order, and then controls the processing unit to be in test pattern； When the switching switch connects the low level end, the functional module in the switching logic unit is in running order, and then The processing unit is controlled to be in mode of operation.
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| CN106405373B (en) * | 2016-08-29 | 2019-06-21 | 北京自动测试技术研究所 | A kind of active test vector matching process |
| CN108333497A (en) * | 2017-11-28 | 2018-07-27 | 上海华力微电子有限公司 | A kind of method of chip testing |
| CN109581199A (en) * | 2019-01-22 | 2019-04-05 | 上海艾为电子技术股份有限公司 | Digital volume production test machine, pumping signal acquisition methods and testing data comparative approach |
| CN109901051A (en) * | 2019-03-01 | 2019-06-18 | 马鞍山创久科技股份有限公司 | A kind of chip Dynamic Current Testing system |
| CN112782551A (en) * | 2019-11-04 | 2021-05-11 | 珠海零边界集成电路有限公司 | Chip and test system of chip |
| CN111307420A (en) * | 2020-01-23 | 2020-06-19 | 珠海荣邦智能科技有限公司 | Infrared quality testing device and method for infrared transmitting tube product |
| CN113393892A (en) | 2020-03-11 | 2021-09-14 | 长鑫存储技术有限公司 | Control chip test method and related equipment |
| CN113391184A (en) | 2020-03-11 | 2021-09-14 | 长鑫存储技术有限公司 | Control chip test method and related equipment |
| CN112802538A (en) * | 2021-01-06 | 2021-05-14 | 上海华岭集成电路技术股份有限公司 | Method for increasing vector depth of test machine |
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| JP3200565B2 (en) * | 1996-12-10 | 2001-08-20 | 松下電器産業株式会社 | Microprocessor and inspection method thereof |
| CN1536486A (en) * | 2003-04-04 | 2004-10-13 | 上海华园微电子技术有限公司 | Intelligent card chip with microprocessor capable of making automatic test |
| US9384108B2 (en) * | 2012-12-04 | 2016-07-05 | International Business Machines Corporation | Functional built-in self test for a chip |
| KR20140112135A (en) * | 2013-03-11 | 2014-09-23 | 삼성전자주식회사 | Semiconductor Device on DIB and Test System |
| CN204142916U (en) * | 2014-10-11 | 2015-02-04 | 上海华力创通半导体有限公司 | Chip |
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Effective date of registration: 20211115 Address after: 610000 China (Sichuan) pilot Free Trade Zone, Chengdu, Sichuan 301, 302, 401 and 402, building 4, No. 715, north section of Hupan Road, Zhengxing street, Tianfu new area, Chengdu Patentee after: Hualizhi core (Chengdu) integrated circuit Co., Ltd Address before: 201702 room 133, Zone C, floor 1, building 1, No. 1362, Huqingping highway, Qingpu District, Shanghai Patentee before: Shanghai Huali chuangtong Semiconductor Co., Ltd |