CN206149239U - Chip measurability port circuit - Google Patents
Chip measurability port circuit Download PDFInfo
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- CN206149239U CN206149239U CN201621264850.3U CN201621264850U CN206149239U CN 206149239 U CN206149239 U CN 206149239U CN 201621264850 U CN201621264850 U CN 201621264850U CN 206149239 U CN206149239 U CN 206149239U
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Abstract
Chip measurability port circuit includes: normal output circuit and test output end normal output circuit includes high level acquisition circuit, low level acquisition circuit and signal output signal output circuit includes pull -up circuit, pull -up protection circuit, pull -down circuit and drop -down protection the test output end circuit includes first transfer gate, second transfer gate and ladder switch, and the P control oil pipe end and the first test selected signal end of the P control oil pipe end of first, second transfer gate link to each other, and N control oil pipe end and second test selected signal end first, the second transfer gate link to each other, the input of test signal transmission to first transfer gate, and the output of first transfer gate links to each other with the input of second transfer gate, and the output of second transfer gate is continuous with the data output end of chip, the source electrode of ladder switch links to each other with the output of first transfer gate, the grounded drain, and the grid links to each other with first test selected signal end. The utility model discloses can go on fast the chip, make things convenient for, reliable test.
Description
Technical field
This utility model belongs to electronic circuit technology field, more particularly to a kind of chip measurability output port circuit.
Background technology
With the development of integrated circuit technique, the design of chip becomes increasingly complex, in order that testing cost is maintained at reasonable
Limit in, design for Measurability technology can be adopted when chip is designed, the every test of chip how is quickly and easily obtained
Vector is one of urgent problem in the industry.
Utility model content
The purpose of this utility model is to provide one kind to test chip with fast and reliable and be exported test volume
Measurability port circuit.
To achieve these goals, this utility model takes following technical solution：
Chip measurability port circuit, including：Normal output circuit and test output circuit；The normal output circuit bag
High level Acquisition Circuit, low level Acquisition Circuit and signal output apparatus are included, wherein, the high level Acquisition Circuit includes that two is defeated
NAND gate, the first reverser and the second reverser for entering, an input of the NAND gate receive the data signal of chip, separately
One input receives test pattern control signal, and outfan is connected with the first reverser, the outfan of the first reverser and the
The input of two reversers is connected；The low level Acquisition Circuit includes that the nor gate of two inputs, the 3rd reverser and the 4th are anti-
To device, an input of the nor gate receives the data signal of chip, and another input receives test pattern control letter
Number, outfan is connected with the 3rd reverser, and the outfan of the 3rd reverser is connected with the input of the 4th reverser；The signal
Output circuit includes pull-up circuit, pull-up protection circuit, pull-down circuit and drop-down protection circuit, and the pull-up protection circuit includes
First PMOS, the second PMOS and the first NMOS tube, the source electrode of first PMOS and grid connection power supply, drain electrode and the
The source electrode of two PMOSs is connected；The grid of the second PMOS is connected with the data output end of chip, is drained and a NMOS
The source electrode of pipe is connected；The grid of first NMOS tube is connected with power supply, grounded drain；The pull-up circuit includes the 4th PMOS
Pipe and the 5th PMOS, the grid of the 4th PMOS are connected with the outfan of the second reverser, and source electrode is connected with power supply, leakage
Pole is connected with the source electrode of the 5th PMOS；The grid of the 5th PMOS is connected with the drain electrode of the second PMOS, is drained and core
The data output end of piece is connected；The drop-down protection circuit includes the 3rd PMOS, the second NMOS tube and the 3rd NMOS tube, described
The source electrode of the 3rd PMOS is connected with power supply, grounded-grid, and drain electrode is connected with the source electrode of the second NMOS tube；Second NMOS tube
Grid be connected with the data output end of chip, drain electrode be connected with the source electrode of the 3rd NMOS tube；The grid of the 3rd NMOS tube
And grounded drain；The pull-down circuit includes the 4th NMOS tube and the 5th NMOS tube, the source electrode and the 5th of the 4th NMOS tube
The drain electrode of PMOS is connected, and grid is connected with the drain electrode of the 3rd PMOS, and drain electrode is connected with the source electrode of the 5th NMOS tube, and the 4th
The drain electrode of NMOS tube is connected with the data output end of chip；The grid of the 5th NMOS tube and the outfan phase of the 4th reverser
Even, grounded drain；The test output circuit includes the first transmission gate, the second transmission gate and ladder switch, first transmission
The P pipe control ends of door, the P pipes control end of the second transmission gate are connected with the first test selection signal end, the N of first transmission gate
Pipe control end, the N pipes control end of the second transmission gate are connected with the second test selection signal end, data signal under test TEST_DATA
Transmit to the input of the first transmission gate, the outfan of first transmission gate is connected with the input of the second transmission gate, described
The outfan of the second transmission gate is connected with the data output end of chip；The source electrode and first transmission gate of the ladder switch
Outfan is connected, grounded drain, and grid is connected with the first test selection signal end.
More specifically, pull-up esd protection circuit and drop-down esd protection circuit are connected with the data output end, wherein,
The pull-up esd protection circuit includes the 6th PMOS, the 7th PMOS, the 8th PMOS and the 7th NMOS tube, the described 8th
The drain electrode of PMOS is connected with the data output end of chip, and source electrode is connected with the drain electrode of the 7th PMOS, and grid is connected with power supply；
The grid and source electrode of the 7th PMOS is connected with power supply；The source electrode of the 6th PMOS is connected with power supply, grounded-grid,
Drain electrode be connected with the data output end of chip, the drain electrode of the 7th NMOS tube is connected with the data output end of chip, source electrode with
Grid is connected with power supply；The drop-down ESD protections include the 8th NMOS tube and the 9th NMOS tube, the grid of the 8th NMOS tube
The 5th resistance of Jing is connected with power supply, and source electrode is connected with the drain electrode of the 9th NMOS tube, and drain electrode is connected with the data output end of chip；Institute
The grid for stating the 9th NMOS tube is grounded Jing after the 6th resistance, source ground.
More specifically, the second resistance and first resistor that the grid of second NMOS tube is concatenated is defeated with the data of chip
Go out end to be connected, and the capacity earth formed by the 6th NMOS tube.
More specifically, the outfan of second transmission gate is concatenated the 4th resistance and the data of 3rd resistor and chip
Outfan is connected.
More specifically, the data signal of chip is input into high level Acquisition Circuit and low level after first-level buffer device
In Acquisition Circuit.
From above technical scheme, output port circuit of the present utility model has normal output circuit and test output
Circuit, controls normal output circuit or test output circuit by test pattern control signal, in the port number for not increasing chip
Chip design for Measurability is realized on the basis of mesh and area, is made chip that there is quick, convenient, reliable test function, is reduced
The testing cost of chip, improves the reliability and stability of chip.
Description of the drawings
In order to be illustrated more clearly that this utility model embodiment, below will be to wanting needed for embodiment or description of the prior art
The accompanying drawing for using does simple introduction, it should be apparent that, drawings in the following description are only some embodiments of the present utility model,
For those of ordinary skill in the art, on the premise of not paying creative work, can be with according to these accompanying drawings acquisitions
Other accompanying drawings.
Circuit block diagrams of the Fig. 1 for this utility model embodiment；
Fig. 2 is utility model works flow chart.
Specific embodiment of the present utility model is described in more detail below in conjunction with accompanying drawing.
Specific embodiment
As shown in figure 1, chip measurability port circuit of the present utility model includes normal output circuit I and test output electricity
Road II, performance data of the normal output circuit I in the case where chip does not enter into test pattern during pio chip normal work
Signal, after chip enters test pattern, exports corresponding test vector data by test output circuit II, test data is believed
Number output completes the test to chip on test machine.The switching of normal output circuit I and test output circuit II is by testing mould
Formula control signal is controlled.
Normal output circuit I includes high level Acquisition Circuit, low level Acquisition Circuit and signal output apparatus, the number of chip
It is believed that number after first-level buffer device B1, being input into into high level Acquisition Circuit and low level Acquisition Circuit.High level collection electricity
Road includes NAND gate A1, the first reverser I2 and the second reverser I3, NAND gate A1 of the present embodiment be one two input with
Not gate, an input of NAND gate A1 receive the data signal of chip, and another input receives test pattern control signal,
The outfan of NAND gate A1 is connected with the first reverser I2, the input of the outfan of the first reverser I2 and the second reverser I3
It is connected.Low level Acquisition Circuit includes nor gate A2, the 3rd reverser I4 and the 4th reverser I5, nor gate A2 be two inputs or
Not gate, an input of nor gate A2 receive the data signal of chip, and another input receives test pattern control signal,
The outfan of nor gate A2 is connected with the 3rd reverser I4, the input of the outfan and the 4th reverser I5 of the 3rd reverser I4
It is connected.
Signal output apparatus are made up of pull-up circuit, pull-up protection circuit, pull-down circuit and drop-down protection circuit, high level
Acquisition Circuit exports data signal in pull-up circuit, and low level Acquisition Circuit is input to data signal in pull-down circuit.
Pull-up protection circuit includes the first PMOS P1, the second PMOS P2 and the first NMOS tube N1, the source electrode of the first PMOS P1 and
Grid connects power vd D, and drain electrode is connected with the source electrode of the second PMOS P2.The grid of the second PMOS P2 is defeated with the data of chip
Go out to hold OUT to be connected, form a feedback, the drain electrode of the second PMOS P2 is connected with the source electrode of the first NMOS tube N1, the 2nd PMOS
The drain electrode of pipe P2 is connected with pull-up circuit simultaneously.The grid of the first NMOS tube N1 is connected with power vd D, the leakage of the first NMOS tube N1
Pole is grounded.Pull-up circuit includes the 4th PMOS P4 and the 5th PMOS P5, the grid of the 4th PMOS and the second reverser I3
Outfan be connected, source electrode is connected with power vd D, drain be connected with the source electrode of the 5th PMOS P5.The grid of the 5th PMOS P5
Pole is connected with the drain electrode of the second PMOS P2, and the drain electrode of the 5th PMOS P5 is connected with the data output end OUT of chip.Pull-up electricity
The digital signal of road output strong " 1 ".
Drop-down protection circuit includes the 3rd PMOS P3, the second NMOS tube N2 and the 3rd NMOS tube N3.3rd PMOS P3
Source electrode be connected with power vd D, grounded-grid, drain electrode be connected with the source electrode of the second NMOS tube N2.The grid of the second NMOS tube N2
It is connected with the data output end OUT of chip, forms a feedback, drain electrode is connected with the source electrode of the 3rd NMOS tube N3.3rd NMOS
The grid and grounded drain of pipe N3.Pull-down circuit includes the 4th NMOS tube N4 and the 5th NMOS tube N5, the source of the 4th NMOS tube N4
Pole is connected with the drain electrode of the 5th PMOS, and grid is connected with the drain electrode of the 3rd PMOS P3, the source of drain electrode and the 5th NMOS tube N5
Extremely it is connected, the drain electrode of the 4th NMOS tube N4 is also connected with the data output end OUT of chip simultaneously, i.e. the grid with the second NMOS tube N2
Extremely it is connected.The grid of the 5th NMOS tube N5 is connected with the outfan of the 4th reverser I5, grounded drain.Pull-down circuit output is strong
The digital signal of " 0 ".More specifically, the grid of the second NMOS tube N2 is concatenated second resistance R2 and first resistor R1 and chip
Data output end OUT be connected, formed one feedback, and by the 6th NMOS tube N6 formed capacity earth.
Further, it is also associated with pulling up esd protection circuit and drop-down esd protection circuit on data output end OUT, can
With transient current caused by chip exterior electrostatic of releasing, protect chip not disturbed by electrostatic.Pull-up esd protection circuit bag
Include the 6th PMOS P6, the 7th PMOS P7, the 8th PMOS P8 and the 7th NMOS tube N7.7th PMOS P7 and the 8th PMOS
Pipe P8 composition pull-up, the drain electrode of the 8th PMOS P8 are connected with the data output end OUT of chip, the leakage of source electrode and the 7th PMOS
Extremely it is connected, grid is connected with power vd D.The grid and source electrode of the 7th PMOS P7 is connected with power vd D.6th PMOS P6
Source electrode is connected with power vd D, grounded-grid, and drain electrode is connected with the data output end OUT of chip.The drain electrode of the 7th NMOS tube N7 with
The data output end OUT of chip is connected, and source electrode and grid are connected with power vd D.
Drop-down ESD protections are by including the 8th NMOS tube N8 and the 9th NMOS tube N9, the grid Jing the 5th of the 8th NMOS tube N8
Resistance R5 is connected with power vd D, and source electrode is connected with the drain electrode of the 9th NMOS tube N9, the data output end OUT phases drained with chip
Even.The grid of the 9th NMOS tube N9 is grounded Jing after the 6th resistance R6, source ground.
Test output circuit II is made up of the first transmission gate A3, the second transmission gate A4 and ladder switch N10.First transmission gate
The P pipe control ends of A3, the P pipes control end of the second transmission gate A4 are connected with the first test selection signal end TEST_N, the first transmission
The N pipe control ends of door A3, the N pipes control end of the second transmission gate A4 are connected with the second test selection signal end TEST, test data
Signal TEST_DATA is transmitted to the input of the first transmission gate A3, the outfan of the first transmission gate A3 and the second transmission gate A4
Input is connected, and the source electrode that the outfan of the first transmission gate A3 also switchs N10 with ladder simultaneously is connected.Ladder switchs the leakage of N10
Pole is grounded, and grid is connected with the first test selection signal end TEST_N.The outfan of the second transmission gate A4 is defeated with the data of chip
Go out to hold OUT to be connected.More specifically, the outfan of the second transmission gate A4 is concatenated the 4th resistance R4 and 3rd resistor R3 and chip
Data output end OUT be connected.The signal TEST of the second test selection signal end output is used for the enable signal control of test chip
Whether circuit processed is converted into test pattern state, and the signal TEST_N of the first test selection signal end TEST_N outputs is used to test
Inverted signal is enabled with TEST signals whether conversely, being equally used for whether test circuit is converted into test pattern state, signal TEST_
DATA is data signal under test, and the test item data needed for output test, this three groups of signals collectively constitute control test mode
Test pattern control signal.
Normal output circuit I and test output circuit II are all connected with the data output end OUT of chip.As shown in Fig. 2 defeated
Exit port circuit passes through test pattern control signal selection port output item.Chip is after working on power, if detecting test mould
Formula control signal is low level, and chip enters normal operating conditions, and normal output circuit I is started working, if detecting test mould
Formula control signal is high level, and chip enters test mode, and test output circuit II is started working, and concrete principle is as follows：
Chip work on power after read test mode control signal TEST, if test pattern control signal be low level if
Chip normal work, output function signal；Function signal includes high level signal and low level signal, and high level signal is by height
Level Acquisition Circuit reads high level signal, and by the grid of the signal output for reading to pull-up control pipe, pulls up control pipe
Data output end OUT is drawn high by the pull-up PMOS of two series connection, is exported by the PMOS conducting of control pull-up protection circuit
The high level signal of " 1 " by force；Low level signal reads low level signal by low level Acquisition Circuit, and will be the signal for reading defeated
Go out on the grid of drop-down control pipe, drop-down control pipe controls the NMOS tube conducting of drop-down protection circuit, by two series connection
Data output end OUT is dragged down by pull-down NMOS pipe, the high level signal of output strong " 0 ", drop-down guarantor when high level is exported
Protection circuit is closed, and when exporting low level, pull-up protection circuit is closed.
If test pattern control signal is high level, chip enters test pattern, and normal output circuit I cuts out, test
Output circuit II, exports test volume by two transmission gates, while ladder switch cuts out, the test volume of output is connected by isolation resistance
It is connected to data output end OUT, output to test machine test chip.Conducting is grounded ladder switch in the normal mode, can fall
The current drain of filling is protected test port circuit not have reverse irrigated current and has influence on chip internal to ground.
Above example only to illustrate the technical solution of the utility model rather than a limitation, although with reference to above-mentioned enforcement
Example has been described in detail to this utility model, it should be understood by a person of ordinary skill in the art that still can be to this reality
Modified with new specific embodiment or equivalent, and repaiied without departing from any of this utility model spirit and scope
Change or equivalent, which all should be covered among scope of the present utility model.
Claims (5)
1. chip measurability port circuit, it is characterised in that include：Normal output circuit and test output circuit；It is described normal
Output circuit includes high level Acquisition Circuit, low level Acquisition Circuit and signal output apparatus, wherein,
The high level Acquisition Circuit includes the NAND gate of two inputs, the first reverser and the second reverser, the NAND gate
One input receives the data signal of chip, and another input receives test pattern control signal, and outfan is anti-with first
It is connected to device, the outfan of the first reverser is connected with the input of the second reverser；
The low level Acquisition Circuit includes the nor gate of two inputs, the 3rd reverser and the 4th reverser, the nor gate
One input receives the data signal of chip, and another input receives test pattern control signal, and outfan is anti-with the 3rd
It is connected to device, the outfan of the 3rd reverser is connected with the input of the 4th reverser；
The signal output apparatus include pull-up circuit, pull-up protection circuit, pull-down circuit and drop-down protection circuit, the pull-up
Protection circuit includes the first PMOS, the second PMOS and the first NMOS tube, the source electrode of first PMOS and grid connection
Power supply, drain electrode are connected with the source electrode of the second PMOS；The grid of the second PMOS is connected with the data output end of chip, leakage
Pole is connected with the source electrode of the first NMOS tube；The grid of first NMOS tube is connected with power supply, grounded drain；
The pull-up circuit includes the 4th PMOS and the 5th PMOS, the grid and the second reverser of the 4th PMOS
Outfan is connected, and source electrode is connected with power supply, and drain electrode is connected with the source electrode of the 5th PMOS；The grid of the 5th PMOS and
The drain electrode of two PMOSs is connected, and drain electrode is connected with the data output end of chip；
The drop-down protection circuit includes the 3rd PMOS, the second NMOS tube and the 3rd NMOS tube, the source of the 3rd PMOS
Pole is connected with power supply, grounded-grid, and drain electrode is connected with the source electrode of the second NMOS tube；The grid of second NMOS tube and chip
Data output end is connected, and drain electrode is connected with the source electrode of the 3rd NMOS tube；The grid and grounded drain of the 3rd NMOS tube；
The pull-down circuit includes the 4th NMOS tube and the 5th NMOS tube, the source electrode and the 5th PMOS of the 4th NMOS tube
Drain electrode is connected, and grid is connected with the drain electrode of the 3rd PMOS, and drain electrode is connected with the source electrode of the 5th NMOS tube, the leakage of the 4th NMOS tube
Pole is connected with the data output end of chip；The grid of the 5th NMOS tube is connected with the outfan of the 4th reverser, and drain electrode connects
Ground；
The test output circuit includes the first transmission gate, the second transmission gate and ladder switch, the P management and control of first transmission gate
End processed, the P pipes control end of the second transmission gate are connected with the first test selection signal end, the N pipe control ends of first transmission gate,
The N pipes control end of the second transmission gate is connected with the second test selection signal end, and data signal under test TEST_DATA is transmitted to first
The input of transmission gate, the outfan of first transmission gate are connected with the input of the second transmission gate, second transmission gate
Outfan be connected with the data output end of chip；The source electrode of the ladder switch and the outfan phase of first transmission gate
Even, grounded drain, grid are connected with the first test selection signal end.
2. chip measurability port circuit as claimed in claim 1, it is characterised in that：It is connected with the data output end
Esd protection circuit and drop-down esd protection circuit are drawn, wherein,
The pull-up esd protection circuit includes the 6th PMOS, the 7th PMOS, the 8th PMOS and the 7th NMOS tube, described
The drain electrode of the 8th PMOS is connected with the data output end of chip, and source electrode is connected with the drain electrode of the 7th PMOS, grid and power supply
It is connected；The grid and source electrode of the 7th PMOS is connected with power supply；The source electrode of the 6th PMOS is connected with power supply, grid
Ground connection, drain electrode are connected with the data output end of chip, and the drain electrode of the 7th NMOS tube is connected with the data output end of chip, source
Pole and grid are connected with power supply；
The drop-down ESD protections include the 8th NMOS tube and the 9th NMOS tube, the 5th resistance of grid Jing of the 8th NMOS tube
It is connected with power supply, source electrode is connected with the drain electrode of the 9th NMOS tube, drain electrode is connected with the data output end of chip；9th NMOS
The grid of pipe is grounded Jing after the 6th resistance, source ground.
3. chip measurability port circuit as claimed in claim 1, it is characterised in that：The grid Jing strings of second NMOS tube
The second resistance and first resistor of connection is connected with the data output end of chip, and the capacity earth formed by the 6th NMOS tube.
4. chip measurability port circuit as claimed in claim 1, it is characterised in that：The outfan Jing of second transmission gate
4th resistance and 3rd resistor of series connection is connected with the data output end of chip.
5. chip measurability port circuit as claimed in claim 1, it is characterised in that：The data signal of chip is slow through one-level
After rushing device, it is input into into high level Acquisition Circuit and low level Acquisition Circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621264850.3U CN206149239U (en) | 2016-11-22 | 2016-11-22 | Chip measurability port circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621264850.3U CN206149239U (en) | 2016-11-22 | 2016-11-22 | Chip measurability port circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206149239U true CN206149239U (en) | 2017-05-03 |
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ID=58626740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN201621264850.3U Active CN206149239U (en) | 2016-11-22 | 2016-11-22 | Chip measurability port circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107612530A (en) * | 2017-09-14 | 2018-01-19 | 博为科技有限公司 | A kind of high-speed differential signal switching switch |
| CN109031097A (en) * | 2018-07-25 | 2018-12-18 | 天地融电子（天津）有限公司 | A kind of chip-detecting apparatus |
| CN109188250A (en) * | 2018-10-08 | 2019-01-11 | 北方电子研究院安徽有限公司 | A kind of chip I/O port circuit being able to carry out static parameter test |
-
2016
- 2016-11-22 CN CN201621264850.3U patent/CN206149239U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107612530A (en) * | 2017-09-14 | 2018-01-19 | 博为科技有限公司 | A kind of high-speed differential signal switching switch |
| CN107612530B (en) * | 2017-09-14 | 2023-11-28 | 博为科技有限公司 | High-speed differential signal change-over switch |
| CN109031097A (en) * | 2018-07-25 | 2018-12-18 | 天地融电子（天津）有限公司 | A kind of chip-detecting apparatus |
| CN109188250A (en) * | 2018-10-08 | 2019-01-11 | 北方电子研究院安徽有限公司 | A kind of chip I/O port circuit being able to carry out static parameter test |
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