CN203799408U - Power supply circuit and power management device of double-interface intelligent card input/output unit - Google Patents
Power supply circuit and power management device of double-interface intelligent card input/output unit Download PDFInfo
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- CN203799408U CN203799408U CN201420138104.4U CN201420138104U CN203799408U CN 203799408 U CN203799408 U CN 203799408U CN 201420138104 U CN201420138104 U CN 201420138104U CN 203799408 U CN203799408 U CN 203799408U
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Abstract
The utility model provides a power supply circuit and a power management device of a double-interface intelligent card input/output unit, relating to the field of power management. A signal input end is connected with the anode of a first electrostatic release protective circuit, the cathode of a second electrostatic release protective circuit and one end of a current-limiting resistor, the cathode of the first electrostatic release protective circuit is connected with a contact type power supply, the anode of the second electrostatic release protective circuit is connected with a grounding power supply, the other end of the current-limiting resistor is connected with one end of a switch of a pull-up circuit, one end of a switch of a pull-down circuit and the input end of a Schmitt circuit, one end of a resistor of the pull-up circuit is connected with a selective power supply, one end of a resistor of the pull-down circuit is connected with the grounding power supply, the selective power supply supplies power to the Schmitt circuit, the grounding end of the Schmitt circuit is connected with the grounding power supply, the output end of the Schmitt circuit is connected with the input end of a level switch circuit, an internal power supply supplies power to the level switch circuit, and the grounding end of the level switch circuit is connected with the grounding power supply.
Description
Technical field
The utility model relates to field of power management, relates in particular to a kind of feed circuit and electric power controller of double-interface smart card input-output unit.
Background technology
Increasingly extensive along with the application of domestic double-interface smart card product, the designing technique of domestic double-interface smart card product is also reaching its maturity, is progressively marching toward the commercialization stage.The design of double-interface smart card product input-output unit guides the designing technique of pin PAD is a comparatively crucial technology in double-interface smart card product introduction volume production stage, directly has influence on the commercialization process of double-interface smart card product.
In existing double-interface smart card product, PAD design technology project mainly contains two kinds:
1) ISO7816PAD continues to use contact intelligent card product P AD designing technique completely,
2) ISO7816PAD is designed again, change ISO7816PAD supply path, power supply is changed into the out-put supply of two interface chip power management modules by ISO7816 power supply VCC PAD.
Wherein, mode 1) as Fig. 1, PAD is by the discharge path of contact power supply VCC and earthing power supply VSS being formed to power supply and ESD(Electro-Static discharge over the ground in input, static discharges) holding circuit (ESD1, ESD2); Effective solution while forming the floating sky of input PAD by upper and lower puller circuit again after current-limiting resistance; Then pass through the noise on the effective filtering input signal of Schmidt circuit, cleaner input signal is sent to chip internal through level shifting circuit.
Mode 1) can solve the ESD performance of ISO7816PAD and the problem of port electrical specification in contact application, but under non-contact application condition, the floating sky of ISO7816 power supply VCC PAD, the floating sky of signal port may produce electric leakage problem and cause extra power consumption, may sacrifice to a certain extent the performance of non-contact application.
Mode 2) can efficient solution contact by no means floating empty, the floating empty problem of signal port of ISO7816VCC PAD under application conditions, but owing to having changed esd discharge path under contact application conditions, aspect the ESD of ISO7816PAD performance and terminal electrical, be difficult to secure.
Utility model content
The technical problems to be solved in the utility model is to provide a kind of feed circuit and electric power controller of double-interface smart card input-output unit, can meet the requirement of contact intelligent card product to ESD performance and port electrical specification, power problems and the electric leakage problem that in the time of can solving again as noncontact product, due to the floating sky of ISO7816 power supply, the floating sky of port, may cause.
In order to address the above problem, the utility model provides a kind of feed circuit of double-interface smart card input-output unit, comprises the first static release protection circuit ESD1, the second static release protection circuit ESD2, current-limiting resistance, pull-up circuit, pull-down circuit, Schmidt circuit, level shifting circuit, signal input part and signal output part;
Described signal input part respectively with the positive terminal of the first static release protection circuit ESD1, the second negative pole end of static release protection circuit ESD2 and one end of current-limiting resistance are connected, the negative pole end of described the first static release protection circuit ESD1 is connected with contact power supply VCC, the positive terminal of described the second static release protection circuit ESD2 is connected with earthing power supply VSS, the other end of described current-limiting resistance respectively with one end of pull-up circuit switch, one end of pull-down circuit switch is connected with the input end of Schmidt circuit, one end of the resistance of described pull-up circuit is connected with selecting power supply VSEL, one end of the resistance of described pull-down circuit is connected with earthing power supply VSS, the power supply of described Schmidt circuit is by selecting power supply VSEL to provide, the earth terminal of described Schmidt circuit is connected with earthing power supply VSS, the output terminal of described Schmidt circuit is connected with the input end of level shifting circuit, the power supply of described level shifting circuit is provided by internal electric source VDD, the earth terminal of described level shifting circuit is connected with earthing power supply VSS.
Preferably, described contact power supply VCC is the contact supply voltage of outside input, what described selection power supply VSEL was that contact power supply and non-contact electric power select through Power Management Unit be the outer power voltage of chip power supply, and described internal electric source VDD is the supply voltage of powering to chip internal that chip internal mu balanced circuit generates.
Preferably, described the first static release protection circuit ESD1 and the second static release protection circuit ESD2 are grid coupling metal-oxide-semiconductor.
What preferably, described pull-up circuit, pull-down circuit comprised series connection enables gauge tap and resistance.
Preferably, described Schmidt circuit comprises a PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, a NMOS pipe N1, the 2nd NMOS pipe N2, the 3rd NMOS pipe N3 and the phase inverter consisting of the 4th PMOS pipe P4, the 4th NMOS pipe N4.
Preferably, described level shifting circuit is the impact damper that high voltage domain forwards low voltage domain to, described impact damper comprises first order phase inverter and second level phase inverter, described first order phase inverter comprises the 5th PMOS pipe P5 and the 5th NMOS pipe N5, and described second level phase inverter comprises the 6th PMOS pipe P6 and the 6th NMOS pipe N6;
Preferably, described level shifting circuit is the impact damper that low voltage domain forwards high voltage domain to, and described impact damper comprises the 7th PMOS pipe P7, the 8th PMOS pipe P8, the 7th NMOS pipe N7, the 8th NMOS pipe N8 and forms rear class phase inverter by the 9th PMOS pipe P9 and the 9th NMOS pipe N9.
In order to address the above problem, the utility model also provides a kind of electric power controller of double-interface smart card input-output unit, comprises the first noncontact antenna port ANT1, the second noncontact antenna port ANT2, rectification and amplitude limiter circuit, earthing power supply GND, contact power supply VCC, Power Management Unit;
Described Power Management Unit comprises connected power selection circuit and mu balanced circuit,
Described the first noncontact antenna port ANT1, the second noncontact antenna port ANT2 are connected with the input end of rectification and amplitude limiter circuit respectively, the non-contact electric power VRF output terminal of described rectification and amplitude limiter circuit is connected with the first input end of power selection circuit, described contact power supply VCC is connected with the second input end of power selection circuit, the output end voltage of described power selection circuit is as selecting power supply VSEL, and the output end voltage of described mu balanced circuit is as internal electric source VDD.
Preferably, rectification and amplitude limiter circuit comprise rectification circuit and amplitude limiter circuit, described rectification circuit comprises commutator tube and switching tube, and described switching tube comprises that the tenth NMOS pipe N10, the 11 NMOS pipe N11 form, and described commutator tube comprises the 12 NMOS pipe N12, the 13 NMOS pipe N13;
Or,
Described rectification circuit comprises commutator tube and switching tube, described switching tube comprises that the 14 NMOS pipe N14 and the 15 NMOS pipe N15 form, described commutator tube comprises the tenth PMOS pipe P10, the 11 PMOS pipe P11, and described rectification circuit also comprises the 12 PMOS pipe P12, the 13 PMOS pipe P13, the 14 PMOS pipe P14 and the 15 PMOS pipe P15 for regulating substrate;
Described amplitude limiter circuit comprises voltage sense circuit, sampling decision circuit and bleeder pipe, described voltage sense circuit comprises the first resistance R 1 and the second resistance R 2, sampling decision circuit comprises comparer, and sampled voltage and reference voltage VREF export the grid control signal of bleeder pipe Nshunt after relatively through comparer;
Or,
Described amplitude limiter circuit comprises rectification circuit, voltage sense circuit, sampling decision circuit and leadage circuit, and described rectification circuit comprises the 16 NMOS pipe N16, the 17 NMOS pipe N17; Voltage sense circuit comprises the 3rd resistance R 3 and the 4th resistance R 4; Voltage sense circuit and the 18 NMOS pipe N18, the 19 NMOS pipe N19 form sampling decision circuit, and the threshold value of sampled voltage and the 18 NMOS pipe N18, the 19 NMOS pipe N19 compares, forms the gate control signal of leadage circuit; The 18 NMOS pipe N18, the 5th resistance R 5 and the 19 NMOS pipe N19, the 6th resistance R 6 form respectively the branch road of releasing to first day line end ANT1, second day line end ANT2; The first capacitor C 1, the 7th resistance R 7 form high-pass filtering circuit; The second capacitor C 2 is filter capacitor;
Power selection circuit comprises power change-over switch and control switching circuit, and the first interrupteur SW 1 is controlled the output of noncontact rectification out-put supply VRF, and second switch SW2 controls the output of contact input power VCC;
Mu balanced circuit is low voltage difference mu balanced circuit, comprise voltage sampling circuit and error comparator, sample circuit comprises the first sampling resistor Rf1 and the second sampling resistor Rf2, sampled voltage and reference voltage VREF through error comparator EA relatively after the output of Modulating Power pipe, power tube is PMOS pipe or NMOS pipe.
Preferably, the first interrupteur SW 1 of power selection circuit is the 16 PMOS pipe P16, second switch SW2 is the 17 PMOS pipe P17, the 18 PMOS pipe P18, the 19 PMOS pipe P19 and the 20 PMOS pipe P20, the 21 PMOS pipe P21 is used for respectively adjusting the 16 PMOS pipe P16, the substrate electric potential of the 17 PMOS pipe P17, the output signal of the voltage detecting circuit of rectification out-put supply VRF, the output signal of the voltage detecting circuit of contact power supply VCC will be used for generating PMOS switch the 16 PMOS pipe P16 by electrical source exchange steering logic, the grid control signal of the 17 PMOS pipe P17.
In sum, application the utility model, can be by the designing technique success of ripe ISO7816PAD, be effectively transplanted in the PAD design of double-interface smart card product, guarantee that it can either meet the requirement of contact intelligent card product to ESD performance and port electrical specification, power problems and the electric leakage problem that in the time of can solving again as noncontact product, due to the floating sky of ISO7816 power supply, the floating sky of port, may cause.
Accompanying drawing explanation
Fig. 1 is the structural representation of conventional smart card input block;
Fig. 2 is the structural representation of the double-interface smart card input block electricity circuit of the utility model embodiment;
Fig. 3 is the structural representation of electric power controller of the double-interface smart card input-output unit of the utility model embodiment;
Fig. 4 is the Schmidt circuit structural representation of the utility model embodiment;
Fig. 5 a is that the high pressure of the utility model embodiment turns low voltage level change-over circuit;
Fig. 5 b is that the low pressure of the utility model embodiment turns high voltage level change-over circuit;
Fig. 6 a is the rectification circuit consisting of high pressure NMOS switch and high pressure NMOS commutator tube of the utility model embodiment;
Fig. 6 b is the rectification circuit consisting of high pressure NMOS switch and high voltage PMOS commutator tube of the utility model embodiment.
Fig. 7 a is the amplitude limiter circuit of the utility model embodiment;
Fig. 7 b is the another kind of amplitude limiter circuit of the utility model embodiment;
Fig. 8 a is the power selection circuit schematic diagram of the utility model embodiment;
Fig. 8 b is the circuit structure diagram of the power selection circuit of the utility model embodiment;
Fig. 9 is the low voltage difference mu balanced circuit of the utility model embodiment.
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearer, hereinafter in connection with accompanying drawing, embodiment of the present utility model is elaborated.It should be noted that, in the situation that not conflicting, the embodiment in the application and the feature in embodiment be combination in any mutually.
As shown in Figure 2, the feed circuit of a kind of double-interface smart card input-output unit that the utility model enforcement provides, comprise the first static release protection circuit ESD1, the second static release protection circuit ESD2, current-limiting resistance, pull-up circuit, pull-down circuit, Schmidt circuit, level shifting circuit, signal input part and signal output part;
Described signal input part respectively with the positive terminal of the first static release protection circuit ESD1, the second negative pole end of static release protection circuit ESD2 and one end of current-limiting resistance are connected, the negative pole end of described the first static release protection circuit ESD1 is connected with contact power supply VCC, the positive terminal of described the second static release protection circuit ESD2 is connected with earthing power supply VSS, the other end of described current-limiting resistance respectively with one end of pull-up circuit switch, one end of pull-down circuit switch is connected with the input end of Schmidt circuit, one end of the resistance of described pull-up circuit is connected with selecting power supply VSEL, one end of the resistance of described pull-down circuit is connected with earthing power supply VSS, the power supply of described Schmidt circuit is by selecting power supply VSEL to provide, the earth terminal of described Schmidt circuit is connected with earthing power supply VSS, the output terminal of described Schmidt circuit is connected with the input end of level shifting circuit, the power supply of described level shifting circuit is provided by internal electric source VDD, the earth terminal of described level shifting circuit is connected with earthing power supply VSS.
As shown in Figure 3, described contact power supply VCC is the contact supply voltage of outside input, what described selection power supply VSEL was that contact power supply VCC and non-contact electric power VRF select through Power Management Unit be the outer power voltage of chip power supply, and described internal electric source VDD is the supply voltage of powering to chip internal that chip internal mu balanced circuit generates.
The ground of chip internal circuit is GND, and the ground of input-output unit is VSS, in practical application, can these two kinds of ground be linked together with certain form according to the requirement of concrete chip.
Described the first static release protection circuit ESD1 and the second static release protection circuit ESD2 can adopt various structures to realize, and the ESD1 in the present embodiment and ESD2 adopt grid coupling metal-oxide-semiconductor to realize.
As shown in Figure 2, described pull-up circuit, pull-down circuit enable gauge tap (control signal PU_EN and PD_EN are provided by chip system internal circuit) and resistance series connection by band, utilize pull-up circuit and the pull-down circuit can be so that input-output unit can be more flexible in application.
As shown in Figure 4, described Schmidt circuit comprises a PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, a NMOS pipe N1, the 2nd NMOS pipe N2, the 3rd NMOS pipe N3 and the phase inverter consisting of the 4th PMOS pipe P4, the 4th NMOS pipe N4.
Adopting Schmidt circuit is herein mainly to utilize the hesitation of this circuit to carry out the noise (or perturbation) on filtering input signal.
As shown in Figure 5 a, described level shifting circuit is the impact damper that high voltage domain forwards low voltage domain to, described impact damper comprises first order phase inverter and second level phase inverter, described first order phase inverter comprises the 5th PMOS pipe P5 and the 5th NMOS pipe N5, and described second level phase inverter comprises the 6th PMOS pipe P6 and the 6th NMOS pipe N6;
As shown in Figure 5 b, described level shifting circuit is the impact damper that low voltage domain forwards high voltage domain to, and described impact damper comprises that the 7th PMOS pipe P7, the 8th PMOS pipe P8, the 7th NMOS pipe N7, the 8th NMOS pipe N8 and the 9th PMOS pipe P9 and the 9th NMOS pipe N9 form rear class phase inverter.
Level shifting circuit of the present utility model adopts buffer structure to realize.For input signal, its effect is that the input signal that converts the input signal of 1.62～5.5V of chip exterior input the 1.8V of internal electric source VDD power domain to is sent to chip internal, corresponding level shifting circuit is relatively simple, and the impact damper that common phase inverter forms can be realized; For output signal, its effect is that the output signal that converts the output signal of the 1.8V of the internal electric source VDD power domain of chip internal output 1.62～5.5V of external power source VCC power domain to outputs on chip pin, the buffer structure that corresponding level shifting circuit adopts six common pipe units to form.
As shown in Figure 3, the electric power controller of a kind of double-interface smart card input-output unit that the utility model provides, comprises the first noncontact antenna port ANT1, the second noncontact antenna port ANT2, rectification and amplitude limiter circuit, earthing power supply GND, contact power supply VCC, Power Management Unit;
Described Power Management Unit comprises connected power selection circuit and mu balanced circuit, and power selection circuit comprises power change-over switch and control switching circuit.
Described the first noncontact antenna port ANT1, the second noncontact antenna port ANT2 are connected with the input end of rectification and amplitude limiter circuit respectively, the non-contact electric power VRF output terminal of described rectification and amplitude limiter circuit is connected with the first input end of power selection circuit, described contact power supply VCC is connected with the second input end of power selection circuit, the output end voltage of described power selection circuit is as selecting power supply VSEL, the power supply VSEL selecting is as the input power of mu balanced circuit, and the output end voltage of described mu balanced circuit is as internal electric source VDD.
As shown in Figure 6 a, described rectification circuit comprises commutator tube and switching tube, and described switching tube comprises that the tenth NMOS pipe N10, the 11 NMOS pipe N11 form, and described commutator tube comprises the 12 NMOS pipe N12, the 13 NMOS pipe N13;
Or,
As shown in Figure 6 b, described rectification circuit comprises commutator tube and switching tube, described switching tube comprises that the 14 NMOS pipe N14 and the 15 NMOS pipe N15 form, described commutator tube comprises the tenth PMOS pipe P10, the 11 PMOS pipe P11, and described rectification circuit also comprises the 12 PMOS pipe P12, the 13 PMOS pipe P13, the 14 PMOS pipe P14 and the 15 PMOS pipe P15 for regulating substrate;
As shown in Figure 7a, described amplitude limiter circuit comprises voltage sense circuit, sampling decision circuit and bleeder pipe, described voltage sense circuit comprises the first resistance R 1 and the second resistance R 2, sampling decision circuit comprises comparer, and sampled voltage and reference voltage VREF export the grid control signal of bleeder pipe Nshunt after relatively through comparer;
Or,
As shown in Figure 7b, described amplitude limiter circuit comprises rectification circuit, voltage sense circuit, sampling decision circuit and leadage circuit, and described rectification circuit comprises the 16 NMOS pipe N16, the 17 NMOS pipe N17; Voltage sense circuit comprises the 3rd resistance R 3 and the 4th resistance R 4; Voltage sense circuit and the 18 NMOS pipe N18, the 19 NMOS pipe N19 form sampling decision circuit, and the threshold value of sampled voltage and the 18 NMOS pipe N18, the 19 NMOS pipe N19 compares, forms the gate control signal of leadage circuit; The 18 NMOS pipe N18, the 5th resistance R 5 and the 19 NMOS pipe N19, the 6th resistance R 6 form respectively the branch road of releasing to first day line end ANT1, second day line end ANT2; The first capacitor C 1, the 7th resistance R 7 form high-pass filtering circuit; The second capacitor C 2 is filter capacitor;
As shown in Figure 8 a, power selection circuit comprises power change-over switch and control switching circuit, and the first interrupteur SW 1 is controlled the output of noncontact rectification out-put supply VRF, and second switch SW2 controls the output of contact input power VCC;
As shown in Figure 8 b, the first interrupteur SW 1 of power selection circuit is the 16 PMOS pipe P16, second switch SW2 is the 17 PMOS pipe P17, the 18 PMOS pipe P18, the 19 PMOS pipe P19 and the 20 PMOS pipe P20, the 21 PMOS pipe P21 is used for respectively adjusting the 16 PMOS pipe P16, the substrate electric potential of the 17 PMOS pipe P17, the output signal of the voltage detecting circuit of rectification out-put supply VRF, the output signal of the voltage detecting circuit of contact power supply VCC will be used for generating PMOS switch the 16 PMOS pipe P16 by electrical source exchange steering logic, the grid control signal of the 17 PMOS pipe P17.
As shown in Figure 9, mu balanced circuit is low voltage difference mu balanced circuit, comprise voltage sampling circuit and error comparator, sample circuit comprises the first sampling resistor Rf1 and the second sampling resistor Rf2, sampled voltage and reference voltage VREF through error comparator EA relatively after the output of Modulating Power pipe, power tube is PMOS pipe or NMOS pipe.
Rectification circuit adopts four pipe rectification units conventionally, two switching tubes add two commutator tubes, can consist of four NMOS pipe, also can consist of four PMOS, can also consist of two nmos switch pipes and two PMOS commutator tubes (can adopt two PMOS pipes to carry out substrate adjusting when generally PMOS is as commutator tube).Rectification circuit mainly consists of commutator tube and switching tube, and specific implementation form is more, and the embodiment of the present invention only provides two kinds of typical structures.Rectification circuit in Fig. 6 a, switching tube by NMOS manage N10, N11 forms, commutator tube by NMOS manage N12, N13 forms; Rectification circuit in Fig. 6 b, switching tube by NMOS manage N14, N15 forms, commutator tube by PMOS manage P10, P11 forms, PMOS pipe P12, P13, P14, P15 are used for regulating substrate, guarantee that the substrate of commutator tube is in noble potential; These two kinds of rectifier structures can both be realized exchanging the full-wave rectification of aerial signal ANT1, ANT2 input, and rectification output VRF is direct current signal.
Amplitude limiter circuit mainly comprises voltage sense circuit, sampling decision circuit and leadage circuit, and voltage sense circuit is voltage sampling circuit, can consist of resistance string, also can consist of active pull-up string; Sampling decision circuit relatively consists of voltage sense circuit output and the threshold voltage of bleeder pipe, also can relatively consist of sampled voltage and reference voltage; The output of sampled voltage output or comparer is as the grid-control voltage of bleeder pipe, the duty of controlled discharge pipe.The Main Function of amplitude limiter circuit be by rectifier output voltage VRF clamper in certain voltage range, after in realization, the vent position of amplitude limiter circuit can be placed on rectification circuit, before also can being placed on rectification circuit, so specific implementation form also has difference.Amplitude limiter circuit shown in Fig. 7 a, it is released is after rectification circuit, resistance R 1, R2 form voltage sense circuit sampling commutating voltage VRF; Comparer forms sampling decision circuit, and sampled voltage and reference voltage VREF export the grid control signal of bleeder pipe Nshunt after relatively through comparer; NMOS pipe Nshunt forms the leadage circuit to rectification output VRF.Amplitude limiter circuit shown in Fig. 7 b, its release be a little before rectification, directly release antenna end ANT1, ANT2, NMOS pipe N16, N17 are commutator tube, the sampling of voltage induced branch road be rectification output herein; Resistance R 3, R4 form voltage sense circuit; Resistance R 3, R4 and NMOS pipe N18, N19 form sampling decision circuit, and the threshold value of sampled voltage and NMOS pipe N18, N19 compares, forms the gate control signal of the branch road of releasing; NMOS pipe N18, resistance R 5 and NMOS pipe N19, resistance R 6 be the branch road of releasing of structure twin aerial ANT1, ANT2 respectively; Capacitor C 1, resistance R 7 form high-pass filtering circuit; Capacitor C 2 is filter capacitor, filter away high frequency noise.
Power selection circuit is Power Management Unit, mainly two power change-over switchs, consists of, and conventionally with larger-size PMOS pipe, realizes; The control signal of switch is that power supply is selected control signal, conventionally comes from the output of power supply comparator circuit or the output of voltage detecting circuit.Power selection circuit mainly consists of power change-over switch and control switching circuit thereof, as shown in Figure 8 a, interrupteur SW 1 is controlled the output of noncontact rectification out-put supply VRF, interrupteur SW 2 is controlled the output of contact input power VCC, and control switching circuit is for guaranteeing that (contact application, non-contact application, two interface application) can both be according to application requirements, the reliable power supply VSEL of stable output under various application conditions.
By reliable Power Management Unit (Power Management Unit), realize chip to contact power supply VCC and non-contact power supply VRF(is non-meets the more stable non-contact power supply VRF that antenna port Ant1 and Ant2 export after rectification and amplitude limiter circuit) electrical source exchange, according to current power environment, select stable, reliable VSEL power supply, select according to depending on the requirement of system applies to power supply and communication mode, can be that both get large person, can be also that contact is preferential; The power supply VSEL selecting passes through mu balanced circuit (Voltage Regulator) again and generates stable internal electric source VDD and offer whole chip system.
The specific implementation structure of power selection circuit as shown in Figure 8 b, change-over switch consists of PMOS pipe P16, P17 respectively, PMOS pipe P18, P19 and P20, P21 are used for respectively adjusting the substrate electric potential of P16, P17, the output signal of the voltage detecting circuit of the output signal of the voltage detecting circuit of rectification out-put supply VRF, contact power supply VCC will be used for generating by electrical source exchange steering logic the grid control signal of PMOS switch P 16, P17, to guarantee the normal realization of electrical source exchange function.
Mu balanced circuit adopts LDO circuit (low voltage difference mu balanced circuit) conventionally, and main body circuit comprises voltage sampling circuit and error comparator, the stable builtin voltage that output does not change with input supply voltage.
Above embodiment is only unrestricted in order to the technical solution of the utility model to be described, only with reference to preferred embodiment, the utility model is had been described in detail.Those of ordinary skill in the art should be appreciated that and can modify or be equal to replacement the technical solution of the utility model, and do not depart from the spirit and scope of technical solutions of the utility model, all should be encompassed in the middle of claim scope of the present utility model.
Claims (10)
1. the feed circuit of a double-interface smart card input-output unit, it is characterized in that, comprise the first static release protection circuit ESD1, the second static release protection circuit ESD2, current-limiting resistance, pull-up circuit, pull-down circuit, Schmidt circuit, level shifting circuit, signal input part and signal output part;
Described signal input part respectively with the positive terminal of the first static release protection circuit ESD1, the second negative pole end of static release protection circuit ESD2 and one end of current-limiting resistance are connected, the negative pole end of described the first static release protection circuit ESD1 is connected with contact power supply VCC, the positive terminal of described the second static release protection circuit ESD2 is connected with earthing power supply VSS, the other end of described current-limiting resistance respectively with one end of pull-up circuit switch, one end of pull-down circuit switch is connected with the input end of Schmidt circuit, one end of the resistance of described pull-up circuit is connected with selecting power supply VSEL, one end of the resistance of described pull-down circuit is connected with earthing power supply VSS, the power supply of described Schmidt circuit is by selecting power supply VSEL to provide, the earth terminal of described Schmidt circuit is connected with earthing power supply VSS, the output terminal of described Schmidt circuit is connected with the input end of level shifting circuit, the power supply of described level shifting circuit is provided by internal electric source VDD, the earth terminal of described level shifting circuit is connected with earthing power supply VSS.
2. feed circuit as claimed in claim 1, it is characterized in that: described contact power supply VCC is the contact supply voltage of outside input, what described selection power supply VSEL was that contact power supply and non-contact electric power select through Power Management Unit be the outer power voltage of chip power supply, and described internal electric source VDD is the supply voltage of powering to chip internal that chip internal mu balanced circuit generates.
3. feed circuit as claimed in claim 1, is characterized in that: described the first static release protection circuit ESD1 and the second static release protection circuit ESD2 are grid coupling metal-oxide-semiconductor.
4. feed circuit as claimed in claim 1, is characterized in that: what described pull-up circuit, pull-down circuit comprised series connection enables gauge tap and resistance.
5. feed circuit as claimed in claim 1, is characterized in that: described Schmidt circuit comprises a PMOS pipe P1, the 2nd PMOS pipe P2, the 3rd PMOS pipe P3, a NMOS pipe N1, the 2nd NMOS pipe N2, the 3rd NMOS pipe N3 and the phase inverter consisting of the 4th PMOS pipe P4, the 4th NMOS pipe N4.
6. feed circuit as claimed in claim 1, it is characterized in that: described level shifting circuit is the impact damper that high voltage domain forwards low voltage domain to, described impact damper comprises first order phase inverter and second level phase inverter, described first order phase inverter comprises the 5th PMOS pipe P5 and the 5th NMOS pipe N5, and described second level phase inverter comprises the 6th PMOS pipe P6 and the 6th NMOS pipe N6.
7. feed circuit as claimed in claim 1, it is characterized in that: described level shifting circuit is the impact damper that low voltage domain forwards high voltage domain to, described impact damper comprises the 7th PMOS pipe P7, the 8th PMOS pipe P8, the 7th NMOS pipe N7, the 8th NMOS pipe N8 and forms rear class phase inverter by the 9th PMOS pipe P9 and the 9th NMOS pipe N9.
8. the electric power controller of a double-interface smart card input-output unit, it is characterized in that, comprise the first noncontact antenna port ANT1, the second noncontact antenna port ANT2, rectification and amplitude limiter circuit, earthing power supply GND, contact power supply VCC, Power Management Unit;
Described Power Management Unit comprises connected power selection circuit and mu balanced circuit,
Described the first noncontact antenna port ANT1, the second noncontact antenna port ANT2 are connected with the input end of rectification and amplitude limiter circuit respectively, the non-contact electric power VRF output terminal of described rectification and amplitude limiter circuit is connected with the first input end of power selection circuit, described contact power supply VCC is connected with the second input end of power selection circuit, the output end voltage of described power selection circuit is as selecting power supply VSEL, and the output end voltage of described mu balanced circuit is as internal electric source VDD.
9. electric power controller as claimed in claim 8, it is characterized in that: rectification and amplitude limiter circuit comprise rectification circuit and amplitude limiter circuit, described rectification circuit comprises commutator tube and switching tube, described switching tube comprises that the tenth NMOS pipe N10, the 11 NMOS pipe N11 form, and described commutator tube comprises the 12 NMOS pipe N12, the 13 NMOS pipe N13;
Or,
Described rectification circuit comprises commutator tube and switching tube, described switching tube comprises that the 14 NMOS pipe N14 and the 15 NMOS pipe N15 form, described commutator tube comprises the tenth PMOS pipe P10, the 11 PMOS pipe P11, and described rectification circuit also comprises the 12 PMOS pipe P12, the 13 PMOS pipe P13, the 14 PMOS pipe P14 and the 15 PMOS pipe P15 for regulating substrate;
Described amplitude limiter circuit comprises voltage sense circuit, sampling decision circuit and bleeder pipe, described voltage sense circuit comprises the first resistance R 1 and the second resistance R 2, sampling decision circuit comprises comparer, and sampled voltage and reference voltage VREF export the grid control signal of bleeder pipe Nshunt after relatively through comparer;
Or,
Described amplitude limiter circuit comprises rectification circuit, voltage sense circuit, sampling decision circuit and leadage circuit, and described rectification circuit comprises the 16 NMOS pipe N16, the 17 NMOS pipe N17; Voltage sense circuit comprises the 3rd resistance R 3 and the 4th resistance R 4; Voltage sense circuit and the 18 NMOS pipe N18, the 19 NMOS pipe N19 form sampling decision circuit, and the threshold value of sampled voltage and the 18 NMOS pipe N18, the 19 NMOS pipe N19 compares, forms the gate control signal of leadage circuit; The 18 NMOS pipe N18, the 5th resistance R 5 and the 19 NMOS pipe N19, the 6th resistance R 6 form respectively the branch road of releasing to first day line end ANT1, second day line end ANT2; The first capacitor C 1, the 7th resistance R 7 form high-pass filtering circuit; The second capacitor C 2 is filter capacitor;
Power selection circuit comprises power change-over switch and control switching circuit, and the first interrupteur SW 1 is controlled the output of noncontact rectification out-put supply VRF, and second switch SW2 controls the output of contact input power VCC;
Mu balanced circuit is low voltage difference mu balanced circuit, comprise voltage sampling circuit and error comparator, sample circuit comprises the first sampling resistor Rf1 and the second sampling resistor Rf2, sampled voltage and reference voltage VREF through error comparator EA relatively after the output of Modulating Power pipe, power tube is PMOS pipe or NMOS pipe.
10. electric power controller as claimed in claim 9, it is characterized in that: the first interrupteur SW 1 of power selection circuit is the 16 PMOS pipe P16, second switch SW2 is the 17 PMOS pipe P17, the 18 PMOS pipe P18, the 19 PMOS pipe P19 and the 20 PMOS pipe P20, the 21 PMOS pipe P21 is used for respectively adjusting the 16 PMOS pipe P16, the substrate electric potential of the 17 PMOS pipe P17, the output signal of the voltage detecting circuit of rectification out-put supply VRF, the output signal of the voltage detecting circuit of contact power supply VCC will be used for generating PMOS switch the 16 PMOS pipe P16 by electrical source exchange steering logic, the grid control signal of the 17 PMOS pipe P17.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420138104.4U CN203799408U (en) | 2014-03-25 | 2014-03-25 | Power supply circuit and power management device of double-interface intelligent card input/output unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420138104.4U CN203799408U (en) | 2014-03-25 | 2014-03-25 | Power supply circuit and power management device of double-interface intelligent card input/output unit |
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| Publication Number | Publication Date |
|---|---|
| CN203799408U true CN203799408U (en) | 2014-08-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420138104.4U Expired - Lifetime CN203799408U (en) | 2014-03-25 | 2014-03-25 | Power supply circuit and power management device of double-interface intelligent card input/output unit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105262245A (en) * | 2015-11-11 | 2016-01-20 | 苏州博恩特智能科技有限公司 | Passive intelligent IC card capable of carrying out wireless charging and charging method thereof |
| CN105958986A (en) * | 2016-05-30 | 2016-09-21 | 清华大学 | Power source management circuit of double-interface IC card |
| CN107248861A (en) * | 2017-06-06 | 2017-10-13 | 上海华力微电子有限公司 | A kind of imput output circuit with LPF function |
-
2014
- 2014-03-25 CN CN201420138104.4U patent/CN203799408U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105262245A (en) * | 2015-11-11 | 2016-01-20 | 苏州博恩特智能科技有限公司 | Passive intelligent IC card capable of carrying out wireless charging and charging method thereof |
| CN105958986A (en) * | 2016-05-30 | 2016-09-21 | 清华大学 | Power source management circuit of double-interface IC card |
| CN105958986B (en) * | 2016-05-30 | 2019-02-22 | 清华大学 | A kind of electric power management circuit of double-interface IC card |
| CN107248861A (en) * | 2017-06-06 | 2017-10-13 | 上海华力微电子有限公司 | A kind of imput output circuit with LPF function |
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Granted publication date: 20140827 |