CN109031097A - A kind of chip-detecting apparatus - Google Patents
A kind of chip-detecting apparatus Download PDFInfo
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- CN109031097A CN109031097A CN201810827085.9A CN201810827085A CN109031097A CN 109031097 A CN109031097 A CN 109031097A CN 201810827085 A CN201810827085 A CN 201810827085A CN 109031097 A CN109031097 A CN 109031097A
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- 238000001514 detection method Methods 0.000 claims abstract description 25
- 238000005259 measurement Methods 0.000 claims abstract description 20
- 239000003990 capacitor Substances 0.000 claims abstract description 12
- 229910044991 metal oxide Inorganic materials 0.000 claims description 8
- 150000004706 metal oxides Chemical class 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000012360 testing method Methods 0.000 abstract description 18
- 238000012544 monitoring process Methods 0.000 abstract 2
- 238000000034 method Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
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- 230000004075 alteration Effects 0.000 description 1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
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- General Physics & Mathematics (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
The present invention provides a kind of chip-detecting apparatus, comprising: simulated battery circuit, slowdown monitoring circuit to be checked, charging chip and charging current measuring circuit；Simulated battery circuit includes: supply port, the first control port, the first PMOS tube, the first NMOS tube, first resistor, second resistance, 3rd resistor, rectifier diode, simulated battery internal resistance and first capacitor；Slowdown monitoring circuit to be checked includes: the second control port, testing resistance, the second PMOS tube, the second NMOS tube, the 4th resistance, the 5th resistance, the 6th resistance and second output terminal；Charging chip is connected between second output terminal and ground, is charged for simulated battery circuit；First detection incoming end of charging current measurement chip and the second detection incoming end are electrically connected to the both ends of circuit under test；The output end output voltage measured value of charging current measurement chip.It is whether normal that charging chip work can be monitored by the voltage measuring value of output.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a chip detection device.
Background
In order to ensure the safety of the online banking transaction of the user, the bank can issue intelligent password equipment to the user when transacting the bank card for the user, so as to assist the user transacting the online banking transaction. When the user carries out online banking transaction, various money transactions can be completed only by using the intelligent password device, otherwise, the client prompts the user to insert the intelligent password device.
With the rapid development of the intelligent password device and the dependence of the online banking transaction on the intelligent password device, the intelligent password device is frequently used by users, especially users who often handle large-amount online banking transactions. However, since the smart password device is not detachable, the battery cannot be replaced, and in order to increase the service life of the smart password device, a charging chip is often used in the industry to charge the battery of the smart password device.
The charging chips are produced in large batches by a production line of a factory, and before the charging chips are put into use, a simple test mode for testing whether the charging chips work normally is urgently needed in order to ensure that the charging chips used in the intelligent password equipment can achieve good charging capacity.
Disclosure of Invention
The present invention aims to solve one of the above problems.
The invention mainly aims to provide a chip detection device.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
one aspect of the present invention provides a chip detecting apparatus, including: the device comprises an analog battery circuit, a circuit to be detected, a charging chip and a charging current measuring chip; wherein the analog battery circuit comprises at least: the power supply circuit comprises a power supply port, a first control port, a first PMOS (P-channel metal oxide semiconductor) tube, a first NMOS (N-channel metal oxide semiconductor) tube, a first resistor, a second resistor, a third resistor, a rectifier diode, an analog battery internal resistance and a first capacitor; wherein: the power supply port is electrically connected with a power supply; the source electrode of the first PMOS tube is electrically connected with the power supply port, the drain electrode of the first PMOS tube is electrically connected with the forward access end of the rectifier diode, and the grid electrode of the first PMOS tube is electrically connected with the drain electrode of the first NMOS tube; the source electrode of the first NMOS tube is electrically connected with the ground end of the power supply, the grid electrode of the first NMOS tube is electrically connected with one end of the third resistor, the other end of the third resistor is connected to the first control port, and the first PMOS tube is switched on or switched off under the control of a control signal output by the first control port; the first resistor is electrically connected between the power supply port and the grid electrode of the first PMOS tube; the second resistor is electrically connected between the grid electrode of the first NMOS tube and the ground end of the power supply; the analog battery internal resistance is connected with the first capacitor in parallel and is electrically connected between the reverse access end of the rectifier diode and the ground end of the power supply; the circuit to be detected at least comprises: the device comprises a second control port, a resistor to be tested, a second PMOS (P-channel metal oxide semiconductor) tube, a second NMOS (N-channel metal oxide semiconductor) tube, a fourth resistor, a fifth resistor, a sixth resistor and a second output end; wherein: one end of the resistor to be tested is electrically connected with the reverse access end of the rectifier diode, the other end of the resistor to be tested is electrically connected with the drain electrode of the second PMOS tube, the source electrode of the second PMOS tube is electrically connected with the second output end, and the grid electrode of the second PMOS tube is electrically connected with the drain electrode of the second NMOS tube; a source electrode of the second NMOS transistor is electrically connected to a ground terminal of the power supply, a gate electrode of the second NMOS transistor is electrically connected to one end of the sixth resistor, and the other end of the sixth resistor is connected to the second control port, so that the second PMOS transistor is turned on or off under the control of a control signal output by the second control port; the fourth resistor is electrically connected between the grid electrode of the second NMOS tube and the ground end of the power supply; the fifth resistor is electrically connected between the grid electrode of the second PMOS tube and the second output end; the charging chip is connected between the second output end and the ground end of the power supply to charge the analog battery circuit, and when the charging chip charges the analog battery circuit, current flows through the resistor to be tested; the first detection access end and the second detection access end of the charging current measurement chip are electrically connected to two ends of the circuit to be detected; and the output end of the charging current measuring chip outputs a voltage measured value, and the voltage measured value is obtained according to the current flowing through the resistor to be measured.
Optionally, the chip detection apparatus further includes: a first gain adjustment resistor and a second gain adjustment resistor;
the first gain adjusting resistor is electrically connected between the output end of the charging current measuring chip and the feedback end of the charging current measuring chip, the second gain adjusting resistor is electrically connected between the feedback end of the charging current measuring chip and the reference end of the charging current measuring chip, and the reference end is electrically connected with the ground end of the power supply.
Optionally, the chip detection apparatus further includes: a second capacitor; the second capacitor is connected in parallel with the first gain adjusting resistor and is connected between the output end of the charging current measuring chip and the feedback end of the charging current measuring chip.
Alternatively to this, the first and second parts may,wherein, VOUTIs the voltage measurement value IsampleFor the current flowing through the resistor to be measured, R22Is the resistance to be measured, Ra1For the first gain adjustment resistor, Ra2Adjusting a resistance for the second gain.
Optionally, the charging current measuring chip is a MAX9922 chip.
According to the technical scheme provided by the invention, the chip detection device provided by the invention can monitor whether the charging chip is in a normal working state or not through the voltage measurement value output by the charging current measurement circuit, and can timely find the charging chip with a problem.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a chip detection apparatus provided in embodiment 1 of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or quantity or location.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
Example 1
The embodiment provides a chip detection device. Fig. 1 is a schematic structural diagram of a chip detection apparatus provided in this embodiment, and as shown in fig. 1, the test circuit includes: the device comprises an analog battery circuit 10, a circuit to be detected 20, a charging chip 30 and a charging current measuring circuit 40; wherein:
the analog battery circuit 10 includes: the power supply circuit comprises a power supply port VBAT-OUT, a first control port CHAR-TEST _ EN, a first PMOS tube Q1, a first NMOS tube Q2, a first resistor R1, a second resistor R2, a third resistor R3, a rectifier diode D1, an analog battery internal resistance R11 and a first capacitor C1; the first switch circuit 104 is composed of a first PMOS transistor Q1, a first NMOS transistor Q2, a first resistor R1, a second resistor R2, and a third resistor R3, the first PMOS transistor Q1 is a first switch unit 1041, and the first NMOS transistor Q2 is a second switch unit 1042. Wherein: the power supply port VBAT-OUT is electrically connected to a power supply source; a source electrode (S) of the first PMOS tube Q1 is electrically connected with the power supply port, a drain electrode (D) of the first PMOS tube Q1 is electrically connected with a forward access end (1) of the rectifying diode D1, and a grid electrode (G) of the first PMOS tube Q1 is electrically connected with a drain electrode (D) of the first NMOS tube Q2; a source (S) of the first NMOS transistor Q2 is electrically connected to a ground GND of the power supply, a gate (G) of the first NMOS transistor Q2 is electrically connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to the first control port CHAR-TEST _ EN, and the first PMOS transistor Q1 is turned on or off under the control of a control signal output from the first control port CHAR-TEST _ EN; the first resistor R1 is electrically connected between the power supply port VBAT-OUT and the grid (G) of the first PMOS tube; the second resistor R2 is electrically connected between the gate (G) of the first NMOS transistor Q2 and the ground GND of the power supply; the reverse access end (2) of the rectifier diode D1 is electrically connected to one end of the resistor R22 to be tested; the analog battery internal resistance R11 is connected with the first capacitor C1 in parallel and is electrically connected between the reverse access end (2) of the rectifier diode D1 and the ground end GND of the power supply; when the charging chip to be tested needs to be tested, the analog battery circuit 10 needs to work, so when the control signal is at a high level, the first NMOS transistor Q2 is conducted with the first PMOS transistor Q1, the first switch circuit 104 is conducted, and the analog battery circuit 10 works normally. When the control signal is at a low level, the first NMOS transistor Q2 and the first PMOS transistor Q1 are turned off, the first switch circuit 104 is turned off, and the analog battery circuit 10 stops working. When the test is not needed, the analog battery circuit can be controlled to stop working through the control signal, so that the loss of the circuit can be reduced.
The circuit 20 to be tested comprises: the device comprises a second control port CHAR-TEST _ EN, a resistor R22 to be tested, a second PMOS tube Q3, a second NMOS tube Q4, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a second output end VBAT-OUT 1; wherein: the reverse access end (2) of the rectifier diode D1 is electrically connected to one end of the resistor R22 to be tested; the other end of the resistor R22 to be tested is electrically connected with the drain (D) of a second PMOS tube Q3, the source (S) of the second PMOS tube Q3 is electrically connected with a second output end VBAT-OUT1, and the gate (G) of the second PMOS tube Q3 is electrically connected with the drain (D) of a second NMOS tube Q4; a source (S) of the second NMOS transistor Q4 is electrically connected with a ground end GND of the power supply, a gate (G) of the second NMOS transistor Q4 is electrically connected with one end of a sixth resistor R6, the other end of the sixth resistor R6 is connected to a second control port CHAR-TEST _ EN, and a second PMOS transistor is switched on or off under the control of a control signal output by the second control port CHAR-TEST _ EN; the fourth resistor R4 is electrically connected between the gate (G) of the second NMOS transistor Q4 and the ground GND of the power supply; the fifth resistor R5 is connected between the gate (G) of the second PMOS transistor Q3 and the second output terminal VBAT-OUT 1. Only when the charging chip to be tested needs to be tested, the circuit to be tested 20 needs to work, so when the control signal output by the second control port CHAR-TEST _ EN is at a high level, the second NMOS transistor Q4 is conducted with the second PMOS transistor Q3, the second switch circuit 204 is conducted, and the circuit to be tested 20 works normally. When the control signal is at a low level, the second NMOS transistor Q4 and the second PMOS transistor Q3 are turned off, the second switch circuit 204 is turned off, and the circuit 20 to be detected stops working. When the test is not needed, the circuit to be tested 20 can be controlled to stop working through the control signal, so that the loss of the circuit can be reduced.
The charging chip 30 is connected between the second output terminal VBAT-OUT1 and the ground GND of the power supply to charge the analog battery circuit 10, and when the charging chip 30 charges the analog battery circuit 10, a current is generated to flow through the resistor R22 to be tested. As shown in fig. 1, the charging chip 30, the resistor R22 to be tested, the analog battery internal resistance R11, and the ground GND of the power supply form a loop. When the charging chip 30 detects that the voltage value of the analog battery circuit 10 is smaller than the preset value, the charging mode is turned on, and the current flows from VBAT-OUT1 through R22, R11 and finally flows into the ground GND. At this time, a current flows through the resistor R22 to be tested, the charging current measuring circuit 40 obtains an output voltage measurement value by detecting the current of the circuit R22 to be tested, and whether the charging chip is a qualified chip can be tested by detecting whether the voltage measurement value conforms to the voltage range of the charging chip for charging the internal battery of the product to normally work.
The charging current measuring chip comprises a first detection access end RS +, a second detection access end RS-and an output end OUT, the first detection access end RS + and the second detection access end RS-are electrically connected to two ends of a resistor R22 to be measured, the output end OUT outputs a voltage measured value, and the voltage measured value is obtained according to current flowing through the resistor to be measured.
Therefore, the chip detection device provided by the embodiment of the invention can monitor whether the charging chip is in a normal working state or not through the voltage measurement value output by the charging current measurement circuit, and can find the charging chip with a problem in time.
As an optional implementation, the test circuit further includes: first gain adjustment resistor Ra1And a second gain adjustment resistor Ra2(ii) a Wherein the first gain adjusting resistor Ra1A second gain adjusting resistor R electrically connected between the output terminal OUT of the charging current measuring chip and the feedback terminal FB of the charging current measuring chipa2The reference terminal REF is electrically connected between the feedback terminal FB of the charging current measuring chip and the reference terminal REF of the charging current measuring chip, and the reference terminal REF is electrically connected with the ground terminal GND of the power supply. In this embodiment, the high-side current detection amplifier may optionally use a MAX9922 chip. The voltage measurement is obtained by the following equation:wherein, VOUTAs a voltage measurement value, IsampleFor the current flowing through the resistor to be measured, R22To the resistance to be measured, Ra1For the first gain adjustment resistor, Ra2A resistance is adjusted for the second gain. The amplification factor of the output voltage is determined by the first gain adjusting resistor and the second gain adjusting resistorSo that the voltage measurement value output by the output terminal OUT is convenient to observe.
As an optional implementation, the test circuit further includes: a second capacitance C2, wherein: a second capacitor C2 and a first gain adjusting resistor Ra1Connected in parallel and connected to the output terminal OUT of the charging current measuring chip and the charging powerBetween feedback terminals FB of the current measurement chip, the functions of isolating direct current signals and returning residual alternating current and harmonic components in a power supply input by a power supply port VBAT-OUT into the ground are achieved.
In this embodiment, during normal operation, the control terminal CHAR-TEST _ EN outputs a high level to turn on Q1, Q2, Q3, and Q4, when the charging chip detects that the analog battery circuit needs to be charged, the charging chip charges the analog battery circuit, a current flows through the circuit to be tested R22, and the measurement chip outputs a voltage measurement value according to the current flowing through R22, so that a technician can analyze whether the charging chip operates in a normal charging voltage range. When the operation is not needed, the control terminal CHAR-TEST _ EN outputs low level, so that Q1, Q2, Q3 and Q4 are all turned off, and the voltage measurement value output by the measurement chip is zero.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made in the above embodiments by those of ordinary skill in the art without departing from the principle and spirit of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (5)
1. A chip detection apparatus, comprising: the device comprises an analog battery circuit, a circuit to be detected, a charging chip and a charging current measuring chip; wherein,
the analog battery circuit includes at least: the power supply circuit comprises a power supply port, a first control port, a first PMOS (P-channel metal oxide semiconductor) tube, a first NMOS (N-channel metal oxide semiconductor) tube, a first resistor, a second resistor, a third resistor, a rectifier diode, an analog battery internal resistance and a first capacitor; wherein: the power supply port is electrically connected with a power supply; the source electrode of the first PMOS tube is electrically connected with the power supply port, the drain electrode of the first PMOS tube is electrically connected with the forward access end of the rectifier diode, and the grid electrode of the first PMOS tube is electrically connected with the drain electrode of the first NMOS tube; the source electrode of the first NMOS tube is electrically connected with the ground end of the power supply, the grid electrode of the first NMOS tube is electrically connected with one end of the third resistor, the other end of the third resistor is connected to the first control port, and the first PMOS tube is switched on or switched off under the control of a control signal output by the first control port; the first resistor is electrically connected between the power supply port and the grid electrode of the first PMOS tube; the second resistor is electrically connected between the grid electrode of the first NMOS tube and the ground end of the power supply; the analog battery internal resistance is connected with the first capacitor in parallel and is electrically connected between the reverse access end of the rectifier diode and the ground end of the power supply;
the circuit to be detected at least comprises: the device comprises a second control port, a resistor to be tested, a second PMOS (P-channel metal oxide semiconductor) tube, a second NMOS (N-channel metal oxide semiconductor) tube, a fourth resistor, a fifth resistor, a sixth resistor and a second output end; wherein: one end of the resistor to be tested is electrically connected with the reverse access end of the rectifier diode, the other end of the resistor to be tested is electrically connected with the drain electrode of the second PMOS tube, the source electrode of the second PMOS tube is electrically connected with the second output end, and the grid electrode of the second PMOS tube is electrically connected with the drain electrode of the second NMOS tube; a source electrode of the second NMOS transistor is electrically connected to a ground terminal of the power supply, a gate electrode of the second NMOS transistor is electrically connected to one end of the sixth resistor, and the other end of the sixth resistor is connected to the second control port, so that the second PMOS transistor is turned on or off under the control of a control signal output by the second control port; the fourth resistor is electrically connected between the grid electrode of the second NMOS tube and the ground end of the power supply; the fifth resistor is electrically connected between the grid electrode of the second PMOS tube and the second output end;
the charging chip is connected between the second output end and the ground end of the power supply to charge the analog battery circuit, and when the charging chip charges the analog battery circuit, current flows through the resistor to be tested;
the first detection access end and the second detection access end of the charging current measurement chip are electrically connected to two ends of the circuit to be detected; and the output end of the charging current measuring chip outputs a voltage measured value, and the voltage measured value is obtained according to the current flowing through the resistor to be measured.
2. The chip detection apparatus according to claim 1, further comprising: a first gain adjustment resistor and a second gain adjustment resistor;
the first gain adjusting resistor is electrically connected between the output end of the charging current measuring chip and the feedback end of the charging current measuring chip, the second gain adjusting resistor is electrically connected between the feedback end of the charging current measuring chip and the reference end of the charging current measuring chip, and the reference end is electrically connected with the ground end of the power supply.
3. The chip detection apparatus according to claim 2, further comprising: a second capacitor;
the second capacitor is connected in parallel with the first gain adjusting resistor and is connected between the output end of the charging current measuring chip and the feedback end of the charging current measuring chip.
4. The chip detection apparatus according to claim 2 or 3,
wherein, VOUTIs the voltage measurement value IsampleFor the current flowing through the resistor to be measured, R22Is the resistance to be measured, Ra1For the first gain adjustment resistor, Ra2Adjusting a resistance for the second gain.
5. The chip detecting apparatus according to any one of claims 1 to 3,
the charging current measuring chip adopts a MAX9922 chip.
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| CN201810827085.9A CN109031097A (en) | 2018-07-25 | 2018-07-25 | A kind of chip-detecting apparatus |
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| CN112147484A (en) * | 2020-08-28 | 2020-12-29 | 珠海市一微半导体有限公司 | Test system based on charging chip and charging test system |
| CN112147484B (en) * | 2020-08-28 | 2024-06-14 | 珠海一微半导体股份有限公司 | Test system based on charging chip and charging test system |
| CN115015286A (en) * | 2022-06-13 | 2022-09-06 | 中大智能科技股份有限公司 | Chip detection method and system based on machine vision |
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