CN204090300U - Bury and hold pcb board structure - Google Patents
Bury and hold pcb board structure Download PDFInfo
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- CN204090300U CN204090300U CN201420562084.3U CN201420562084U CN204090300U CN 204090300 U CN204090300 U CN 204090300U CN 201420562084 U CN201420562084 U CN 201420562084U CN 204090300 U CN204090300 U CN 204090300U
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Abstract
The utility model discloses one to bury and hold pcb board structure, comprise multiple circuit layer with circuitous pattern, also comprise: bury described in being arranged at and hold in pcb board and run through the first metal layer of at least two-layer described circuit layer; Be adjacent to described the first metal layer and run through the second metal level of at least two-layer described circuit layer; And the dielectric layer be filled between described the first metal layer and described second metal level, described dielectric layer and the first metal layer and the second metal level form electric capacity.The utility model proposes one and bury appearance pcb board structure, by realizing utilizing coaxial configuration to bury appearance in the longitudinal direction of pcb board, it is comparatively simple that it realizes technique, the use of the patch capacitor device on pcb board surface can be reduced, this buries capacitance type, and to take pcb board surface area minimum, and then also can realize larger capacity and bury and be installed with meter.
Description
Technical field
The utility model relates to a kind of pcb board structure, particularly relates to a kind of novel burying and holds burying of structure and hold pcb board structure.
Background technology
Along with PCB (Printed Circuit Board, printed circuit board (PCB)) plate realizes increasing function, on pcb board, corresponding electronic device also gets more and more, and on pcb board, available remaining space is more and more less.If pcb board also will increase New function, often drop because of the limited space on pcb board, or increase new function on pcb board after, make the volume of pcb board excessive, be unfavorable for the assembling of product.
Present electronic product all toward miniaturized future development, also has same requirement to pcb board, that is: makes the additional electronic component densification of pcb board, or reduces the electronic device number that PCB installs, thus can obtain the high pcb board of integrated level.In prior art, larger area on the PCB usually using patch capacitor this patch capacitor to need to take on the surface of pcb board, is unfavorable for the development of pcb board to miniaturization.
Utility model content
In view of this, the utility model proposes a kind of pcb board structure realizing burying in a large number appearance to make pcb board miniaturized.
In order to achieve the above object, the technical scheme that the utility model adopts is:
One is buried and is held pcb board structure, comprises multiple circuit layer with circuitous pattern, also comprises:
Bury described in being arranged at and hold in pcb board and run through the first metal layer of at least two-layer described circuit layer;
Be adjacent to described the first metal layer and run through the second metal level of at least two-layer described circuit layer; And
Be filled in the dielectric layer between described the first metal layer and described second metal level, described dielectric layer and the first metal layer and the second metal level form electric capacity.
Bury as the utility model and hold being further of pcb board structure, described at least two-tier circuit layer comprises the first circuit layer and second circuit layer, described the first metal layer connects described first circuit layer, described second metal level connects second circuit layer, wherein, there is voltage difference between described first circuit layer and described second circuit layer.
Bury as the utility model and hold being further of pcb board structure, the described appearance pcb board that buries also comprises bus plane and the stratum corresponding with described bus plane, multiple described circuit layer is between described bus plane and described stratum, wherein, described the first metal layer and described bus plane are electrically connected, and described second metal level and described stratum are electrically connected; Or described the first metal layer and described stratum are electrically connected, described second metal level and described bus plane are electrically connected.
Bury as the utility model and hold being further of pcb board structure, the radial section of described the first metal layer and described second metal level is close-shaped; Described the first metal layer is provided with multilayer, coaxially arranges between the described the first metal layer of each layer, and the described the first metal layer of each layer is intervally installed, and wherein, connects between adjacent described the first metal layer; Described second metal level is provided with multilayer, and correspondence is arranged between adjacent two-layer described the first metal layer respectively, wherein, connects between adjacent described second metal level.
Bury as the utility model and hold being further of pcb board structure, the radial section of described the first metal layer and described second metal level is circular, square or polygon.
Bury as the utility model and hold being further of pcb board structure, described the first metal layer and/or described second metal level axial length are equal to or less than the thickness of described pcb board.
Bury as the utility model and hold being further of pcb board structure, the thickness of described dielectric layer is for being less than or equal to 50 μm.
Compared with prior art, the utility model proposes one and bury appearance pcb board structure, by realizing burying appearance in the longitudinal direction of pcb board, it is comparatively simple that it realizes technique, the use of the patch capacitor device on pcb board surface can be reduced, this buries capacitance type, and to take pcb board surface area minimum, and then also can realize larger capacity and bury and be installed with meter.
Accompanying drawing explanation
Fig. 1 is the vertical view of the utility model pcb board structure one execution mode;
Fig. 2 is that the utility model buries the cutaway view holding pcb board structure one execution mode;
Fig. 3 is that the utility model buries the cutaway view holding the another execution mode of pcb board structure;
Fig. 4 is that the utility model buries the vertical view holding the another execution mode of pcb board structure; And
Fig. 5 is that the utility model buries the cutaway view holding the another execution mode of pcb board structure.
Embodiment
Below with reference to embodiment shown in the drawings, the utility model is described in detail.But these execution modes do not limit the utility model, the structure that those of ordinary skill in the art makes according to these execution modes, method or conversion functionally are all included in protection range of the present utility model.
Please coordinate shown in Fig. 1 and Fig. 2, wherein, Fig. 1 is that the utility model buries the vertical view holding pcb board structure one execution mode; Fig. 2 is that the utility model buries the cutaway view holding pcb board structure one execution mode.Of the present utility model burying is held pcb board structure and is utilized printed circuit board (PCB) coaxial aperture structure to achieve pcb board 1 to bury appearance, do not have special material requirements, coordinate by means of only specific printed circuit board arrangement and technique, just can realize pcb board 1 and bury and be installed with meter.
The utility model buries and holds in pcb board 1 structural implementation, and this buries appearance pcb board 1 and comprises: bus plane 3, stratum 4 and the multiple circuit layers 2 with circuitous pattern between bus plane 3 and stratum 4.In pcb board 1 course of processing, first complete the making of the internal layer circuit layer 2 of pcb board 1, and multilayer circuit layer 2 pressing is formed a multi-layer PCB board 1, especially, in the present embodiment, the position of burying appearance is needed can to leave a blank in advance or retain and a wherein internal layer porose disc (not shown) be extremely connected.
In the utility model, this buries and holds pcb board 1 and also comprise: be arranged to bury and hold in pcb board 1 and run through the first metal layer 11 of at least two-tier circuit layer 2, be adjacent to the first metal layer 11 and run through the second metal level 13 of at least two-tier circuit layer 2, and the dielectric layer 12 be filled between the first metal layer 11 and the second metal level 13, this dielectric layer 12 forms electric capacity with the first metal layer 11 and the second metal level 13.As shown in Figure 3, in an execution mode of the present utility model, this at least two-tier circuit layer comprise the first circuit layer and second circuit layer, the first metal layer 11 connects the first circuit layer, second 13 layers, metal connects second circuit layer, wherein, there is voltage difference between the first circuit layer and second circuit layer.In addition, it should be noted that, the first circuit layer in the utility model and second circuit layer are not limited to specific double-layer structure, but represent the two-tier circuit layer being positioned at different layers in multilayer circuit layer 12.
As shown in Figure 2, in another execution mode of the present utility model, the first metal layer 11 and bus plane are electrically connected, and the second metal level 13 is electrically connected with stratum; Or the first metal layer 11 and stratum are electrically connected, the second metal level 13 is electrically connected with bus plane.
Preferably, as shown in Figures 4 and 5, in another execution mode of the present utility model, the radial section of the first metal layer 11 and the second metal level 12 is close-shaped; The first metal layer 11 is provided with multilayer, coaxially arranges between each layer the first metal layer 11, and each layer the first metal layer 11 is intervally installed, and wherein, connects between adjacent the first metal layer 11; Second metal level 13 is set to multilayer, and correspondence is arranged between adjacent two-layer the first metal layer 11 respectively, wherein, connects between the second adjacent metal level 13; In addition, between adjacent the first metal layer 11 and the second metal level 13, be filled with dielectric layer 12, so arrange to make the first metal layer 11 form multiple coaxial annulus with the second metal level 13.Briefly, by the first metal layer 11 as odd-level and as a pole of electric capacity, using the second metal level 13 as even level and as another pole of electric capacity, by the first metal layer 11 and the second metal level 13 interval are arranged, and by techniques such as Graphic transitions, filler, nog plates, coaxial the first metal layer 11 is communicated with respectively, the second coaxial metal level 13 is communicated with respectively, thus as burying the two poles of the earth holding structure.
Preferably, in the utility model, the first metal layer 11 and/or the second metal level 13 axial length are equal to or less than the thickness of pcb board 1.Wherein, the first metal layer 11 and the second metal level 13, respectively as the capacitor anode circle of electric capacity and capacitance cathode circle, so arrange and can realize carrying out jumbo burying at pcb board 1 and be installed with meter.
Further, the first metal layer 11 in present embodiment and the second metal level 13 are processed to form on pcb board 1 by other techniques such as plating, sputtering, autoreduction technique, plasma cleaning or etchings, the nonmetallic materials that the material forming this first metal layer 11 and the second metal level 13 is selected from the metal materials such as copper, gold, nickel, silver or can meets technique and electric property.As a preferred embodiment of the present utility model, the radial section of the first metal layer 11 and the second metal level 13 is circular, and this first metal layer 11 and the second metal level 13 are coaxial configuration, and the diameter of the second metal level 13 is greater than the diameter of the first metal layer 11.Setting like this is minimum with the material making this first metal layer 11 and the second metal level 13 and use, and the area taken is also relatively little.When the axial length of the first metal layer 11 and the second metal level 13 is less than the thickness of pcb board 1, this buries and holds structure for together collar structure.Certainly, in other execution modes of the present utility model, the radial section of the first metal layer 11 and the second metal level 13 also can be square or polygon etc.
In the present embodiment, the formation of the dielectric layer 12 between the first metal layer 11 and the second metal level 13, except using cladding process, also can adopt other techniques such as comprising sputtering, plasma cleaning to realize.This dielectric layer 12 adjusts capacitance by control medium thickness and different dielectric properties materials, and preferably, the thickness of dielectric layer 12 is for being less than or equal to 50 μm.
Bury appearance technique compared to prior art midplane, the utility model, without the need to designing ultra-thin Core layer, is convenient to the processing of pcb board.Pcb board structure of the present utility model, by realizing utilizing coaxial configuration to bury appearance in the longitudinal direction of pcb board, it is comparatively simple that it realizes technique, the use of the patch capacitor device on pcb board surface can be reduced, this buries capacitance type, and to take pcb board surface area minimum, and then also can realize larger capacity and bury and be installed with meter.
Below embodiment has been described in detail the utility model by reference to the accompanying drawings, and those skilled in the art can make many variations example to the utility model according to the above description.Thus, some details in embodiment should not formed restriction of the present utility model, the utility model by the scope that defines using appended claims as protection range of the present utility model.
Claims (7)
1. bury and hold a pcb board structure, comprise multiple circuit layer with circuitous pattern, it is characterized in that, also comprise:
Bury described in being arranged at and hold in pcb board and run through the first metal layer of at least two-layer described circuit layer;
Be adjacent to described the first metal layer and run through the second metal level of at least two-layer described circuit layer; And
Be filled in the dielectric layer between described the first metal layer and described second metal level, described dielectric layer and the first metal layer and the second metal level form electric capacity.
2. according to claim 1 burying holds pcb board structure, it is characterized in that, described at least two-tier circuit layer comprises the first circuit layer and second circuit layer, described the first metal layer connects described first circuit layer, described second metal level connects second circuit layer, wherein, there is voltage difference between described first circuit layer and described second circuit layer.
3. according to claim 1 burying holds pcb board structure, it is characterized in that, the described appearance pcb board that buries also comprises bus plane and the stratum corresponding with described bus plane, multiple described circuit layer is between described bus plane and described stratum, wherein, described the first metal layer and described bus plane are electrically connected, and described second metal level and described stratum are electrically connected; Or described the first metal layer and described stratum are electrically connected, described second metal level and described bus plane are electrically connected.
4. according to claim 1 burying holds pcb board structure, and it is characterized in that, the radial section of described the first metal layer and described second metal level is close-shaped; Described the first metal layer is provided with multilayer, coaxially arranges between the described the first metal layer of each layer, and the described the first metal layer of each layer is intervally installed, and wherein, connects between adjacent described the first metal layer; Described second metal level is provided with multilayer, and correspondence is arranged between adjacent two-layer described the first metal layer respectively, wherein, connects between adjacent described second metal level.
5. according to claim 4 burying holds pcb board structure, and it is characterized in that, the radial section of described the first metal layer and described second metal level is circular, square or polygon.
6. according to claim 5 burying holds pcb board structure, and it is characterized in that, described the first metal layer and/or described second metal level axial length are equal to or less than the thickness of described pcb board.
7. according to claim 1 burying holds pcb board structure, and it is characterized in that, the thickness of described dielectric layer is for being less than or equal to 50 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420562084.3U CN204090300U (en) | 2014-09-26 | 2014-09-26 | Bury and hold pcb board structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420562084.3U CN204090300U (en) | 2014-09-26 | 2014-09-26 | Bury and hold pcb board structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204090300U true CN204090300U (en) | 2015-01-07 |
Family
ID=52182963
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420562084.3U Active CN204090300U (en) | 2014-09-26 | 2014-09-26 | Bury and hold pcb board structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204090300U (en) |
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2014
- 2014-09-26 CN CN201420562084.3U patent/CN204090300U/en active Active
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 310052 Binjiang District Changhe Road, Zhejiang, China, No. 466, No. Patentee after: Xinhua three Technology Co., Ltd. Address before: 310052 Binjiang District Changhe Road, Zhejiang, China, No. 466, No. Patentee before: Huasan Communication Technology Co., Ltd. |