CN204067349U - A kind of chip operator guards - Google Patents
A kind of chip operator guards Download PDFInfo
- Publication number
- CN204067349U CN204067349U CN201420434868.8U CN201420434868U CN204067349U CN 204067349 U CN204067349 U CN 204067349U CN 201420434868 U CN201420434868 U CN 201420434868U CN 204067349 U CN204067349 U CN 204067349U
- Authority
- CN
- China
- Prior art keywords
- chip
- operator guards
- utility
- model
- corner
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Abstract
The utility model provides a kind of chip operator guards, and described chip operator guards is the right-angled intersection region that criss-cross construction is formed between chip, and with the turning close proximity of each chip.The utility model forms the chip operator guards with the turning close proximity of each chip by right-angled intersection region between the chips, greatly can strengthen the resistance to stress cracking intensity of chip corner, thus improves performance and the yield of chip.The utility model structure is simple, and Be very effective, is applicable to semi-conductor industry manufacture.
Description
Technical field
The utility model belongs to semiconductor applications, particularly relates to a kind of chip operator guards.
Background technology
Along with the develop rapidly of electronics industry, the range of application of semiconductor chip is increasing, and the processing of chip more and more receives publicity and payes attention to.Chip cutting, encapsulation and assembling are the important procedures of semiconductor machining, and it directly has influence on the cost of chip, quality and various performance.
As shown in Figure 1, it comprises the following steps the manufacturing process of existing a kind of semiconductor chip:
First step S11, semiconductor crystal wafer processing procedure, manufactures various device architecture on semiconductor crystal wafer;
Second step S12, the grinding of wafer, is thinned to certain thickness by wafer, to facilitate cutting splitting;
3rd step S13, the cutting of wafer, the information such as the geomery of foundation chip carry out cutting splitting to wafer, obtain independently semiconductor chip;
4th step S14, paster, adopts the technology such as metal welding to be affixed on substrate by semiconductor chip;
5th step S15, bonding semiconductor gold thread, with the interface of High Purity Gold bundle of lines chip and the interface bonding of substrate;
6th step S16, encapsulated moulding, adopts as the polymer such as silica gel encapsulate semiconductor chip, packaged semiconductor chip is solidified into required form;
7th step S17, test assembling, tests semiconductor chip, and assembles the semiconductor chip by test, to complete the manufacture of semiconductor chip.
Find in test process, by the part semiconductor chip 10 made in above-mentioned manufacture process, there is crackle 101 in its corner, as shown in Figure 2, having a strong impact on performance and the yield of semiconductor chip, and, can be found out by test, this crack defect is often positioned at the same position of each chip, and has similar shape.
Occur that the reason of above-mentioned defect may be that the cutting of wafer, encapsulation or assembling process cause the generation of defect, but reason of searching to the bottom is because the ability to bear of semiconductor chip corner counter stress is too caused by weakness.
In view of the defect of above prior art, the utility model provides a kind of chip operator guards, to strengthen the ability to bear of semiconductor chip corner counter stress, thus improves performance and the yield of chip.
Utility model content
The shortcoming of prior art in view of the above, the purpose of this utility model is to provide a kind of chip operator guards, occurs the problems such as Corner crack for solving in prior art in the semiconductor chip course of processing because stress ability to bear is weak.
For achieving the above object and other relevant objects, the utility model provides a kind of chip operator guards, and described chip operator guards is the right-angled intersection region that criss-cross construction is formed between chip, and with the turning close proximity of each chip.
As a kind of preferred version of chip operator guards of the present utility model, described chip periphery is also formed with chip sealing ring, and described chip operator guards and described chip sealing ring close proximity.
As a kind of preferred version of chip operator guards of the present utility model, described chip operator guards part extends to the passage between each chip.
As a kind of preferred version of chip operator guards of the present utility model, the shape of described chip comprises quadrangle that corner is right angle or corner is the octagon on inclined-plane.
As a kind of preferred version of chip operator guards of the present utility model, the material of described chip operator guards is metal material.
Further, described metal material comprises copper.
As a kind of preferred version of chip operator guards of the present utility model, the distance between two adjacent chips is 80um ~ 150um.
As mentioned above, the utility model provides a kind of chip operator guards, and described chip operator guards is the right-angled intersection region that criss-cross construction is formed between chip, and with the turning close proximity of each chip.The utility model has following beneficial effect: the utility model forms the chip operator guards with the turning close proximity of each chip by right-angled intersection region between the chips; greatly can strengthen the resistance to stress cracking intensity of chip corner, thus improve performance and the yield of chip.The utility model structure is simple, and Be very effective, is applicable to semi-conductor industry manufacture.
Accompanying drawing explanation
Fig. 1 is shown as the manufacturing process schematic diagram of a kind of semiconductor chip of the prior art.
Fig. 2 is shown as semiconductor chip structure schematic diagram of the prior art.
Fig. 3 is shown as the structural representation of a kind of chip operator guards of the present utility model, wherein, and the quadrangle to be turning the be right angle of the chip form in figure.
Fig. 4 is shown as the structural representation of another kind of chip operator guards of the present utility model, wherein, and the octagon on to be corner the be inclined-plane of the chip form in figure.
Element numbers explanation
10 chips
20 chip sealing rings
30 chip operator guards
Embodiment
Below by way of specific instantiation, execution mode of the present utility model is described, those skilled in the art the content disclosed by this specification can understand other advantages of the present utility model and effect easily.The utility model can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present utility model.
Refer to Fig. 3 ~ 4.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present utility model in a schematic way, then only the assembly relevant with the utility model is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
Embodiment 1
As shown in Figure 3, the present embodiment provides a kind of chip operator guards 30, and described chip operator guards 30 is formed at the right-angled intersection region between chip 10 in criss-cross construction, and with the turning close proximity of each chip 10.
As shown in Figure 3, exemplarily, the quadrangle at the shape of described chip 10 to be corner be right angle, two sidewalls of chip 10 corner of this shape are often more fragile, need to reinforce.
Exemplarily, described chip 10 periphery is also formed with chip sealing ring 20, and described chip operator guards 30 and described chip sealing ring 20 close proximity.Described chip sealing ring 20 is made in the periphery of chip 10, and the stress spread produced in the processes such as cutting for preventing chip 10 damages to chip 10 inside chip 10.In general, described chip sealing ring 20 comprises the metal level of two alternate settings, and the dielectric layer composition of filling between two metal levels, and the material of described metal level can be copper etc., and described dielectric layer can be silicon dioxide etc.In the present embodiment, the height of described chip operator guards 30 is equal with the height of described chip sealing ring 20.
Described right-angled intersection region is formed by 4 rectangular dies 10, between two adjacent chips 10, there is passage, for each chip 10 is kept apart, in addition, distance between two adjacent chips 10 is 80um ~ 150um, distance between chip 10 can fluctuate within the scope of this, and the distance between chip 10 can be identical, also can be different.
In the present embodiment, described chip operator guards 30 part extends to the passage between each chip 10, to strengthen the protection to chip 10.
Particularly, two sidewall close contacts of described chip operator guards 30 and each chip 10 corner.Exemplarily, the material of described chip operator guards 30 is metal material.In the present embodiment, described metal material is copper, certainly, as other the metal material such as Ti, Al also may be applicable to the utility model, is not limited thereto.
The utility model forms the chip operator guards 30 with the turning close proximity of each chip by right-angled intersection region between the chips, greatly can strengthen the resistance to stress cracking intensity of chip corner, thus improves performance and the yield of chip.
Embodiment 2
As shown in Figure 4, the present embodiment provides a kind of chip operator guards 30, and described chip operator guards 30 is formed at the right-angled intersection region between chip 10 in criss-cross construction, and with the turning close proximity of each chip 10.
As shown in Figure 4, exemplarily, the octagon on the shape of described chip 10 to be corner be inclined-plane, chip 10 corner (in fact comprising two turnings and an inclined-plane) of this shape is more fragile equally, needs to reinforce.
Exemplarily, described chip 10 periphery is also formed with chip sealing ring 20, and described chip operator guards 30 and described chip sealing ring 20 close proximity.Described chip sealing ring 20 is made in the periphery of chip 10, and the stress spread produced in the processes such as cutting for preventing chip 10 damages to chip 10 inside chip 10.In general, described chip sealing ring 20 comprises the metal level of two alternate settings, and the dielectric layer composition of filling between two metal levels, and the material of described metal level can be copper etc., and described dielectric layer can be silicon dioxide etc.In the present embodiment, the height of described chip operator guards 30 is equal with the height of described chip sealing ring 20.
Described right-angled intersection region is formed by 4 octagon chips 10, between two adjacent chips 10, there is passage, for each chip 10 is kept apart, in addition, distance between two adjacent chips 10 is 80um ~ 150um, distance between chip 10 can fluctuate within the scope of this, and the distance between chip 10 can be identical, also can be different.
In the present embodiment, described chip operator guards 30 part extends to the passage between each chip 10, to strengthen the protection to chip 10.
Particularly, the inclined-plane at described chip operator guards 30 and each chip corners place and adjacent with this inclined-plane two sidewall close contacts.Exemplarily, the material of described chip operator guards 30 is metal material.In the present embodiment, described metal material is copper, certainly, as other the metal material such as Ti, Al also may be applicable to the utility model, is not limited thereto.
The utility model forms the chip operator guards 30 with the turning close proximity of each chip by right-angled intersection region between the chips, greatly can strengthen the resistance to stress cracking intensity of chip corner, thus improves performance and the yield of chip.
As mentioned above, the utility model provides a kind of chip operator guards 30, and described chip operator guards 30 is formed at the right-angled intersection region between chip 10 in criss-cross construction, and with the turning close proximity of each chip 10.The utility model has following beneficial effect: the utility model forms the chip operator guards 30 with the turning close proximity of each chip by right-angled intersection region between the chips; greatly can strengthen the resistance to stress cracking intensity of chip corner, thus improve performance and the yield of chip.The utility model structure is simple, and Be very effective, is applicable to semi-conductor industry manufacture.So the utility model effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present utility model and effect thereof only, but not for limiting the utility model.Any person skilled in the art scholar all without prejudice under spirit of the present utility model and category, can modify above-described embodiment or changes.Therefore, such as have in art and usually know that the knowledgeable modifies or changes not departing from all equivalences completed under the spirit and technological thought that the utility model discloses, must be contained by claim of the present utility model.
Claims (7)
1. a chip operator guards, is characterized in that, described chip operator guards is the right-angled intersection region that criss-cross construction is formed between chip, and with the turning close proximity of each chip.
2. chip operator guards according to claim 1, is characterized in that: described chip periphery is also formed with chip sealing ring, and described chip operator guards and described chip sealing ring close proximity.
3. chip operator guards according to claim 1, is characterized in that: described chip operator guards part extends to the passage between each chip.
4. chip operator guards according to claim 1, is characterized in that: the shape of described chip comprises quadrangle that corner is right angle or corner is the octagon on inclined-plane.
5. chip operator guards according to claim 1, is characterized in that: the material of described chip operator guards is metal material.
6. chip operator guards according to claim 5, is characterized in that: described metal material comprises copper.
7. chip operator guards according to claim 1, is characterized in that: the distance between two adjacent chips is 80um ~ 150um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420434868.8U CN204067349U (en) | 2014-08-04 | 2014-08-04 | A kind of chip operator guards |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420434868.8U CN204067349U (en) | 2014-08-04 | 2014-08-04 | A kind of chip operator guards |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204067349U true CN204067349U (en) | 2014-12-31 |
Family
ID=52208804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420434868.8U Expired - Fee Related CN204067349U (en) | 2014-08-04 | 2014-08-04 | A kind of chip operator guards |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204067349U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021052125A1 (en) * | 2019-09-20 | 2021-03-25 | 天津大学 | Multiplexer |
| CN117709285A (en) * | 2024-02-05 | 2024-03-15 | 宁波联方电子科技有限公司 | Seal ring drawing method, seal ring drawing system, electronic equipment and storage medium |
-
2014
- 2014-08-04 CN CN201420434868.8U patent/CN204067349U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021052125A1 (en) * | 2019-09-20 | 2021-03-25 | 天津大学 | Multiplexer |
| CN117709285A (en) * | 2024-02-05 | 2024-03-15 | 宁波联方电子科技有限公司 | Seal ring drawing method, seal ring drawing system, electronic equipment and storage medium |
| CN117709285B (en) * | 2024-02-05 | 2024-05-07 | 宁波联方电子科技有限公司 | Seal ring drawing method, seal ring drawing system, electronic equipment and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI267927B (en) | Method for wafer level package | |
| CN204067349U (en) | A kind of chip operator guards | |
| US9029195B2 (en) | Leadframe, semiconductor device, and method of manufacturing the same | |
| CN104752252A (en) | Crystal back defect representation method | |
| CN203941897U (en) | A kind of chip seal ring structure | |
| CN103824787A (en) | Wafer bonding method based on bonding agent | |
| TW201448058A (en) | Method of manufacturing a semiconductor device | |
| CN110364442B (en) | The bonding method and system of chip | |
| CN103972185A (en) | Integrated device and fabrication process thereof | |
| CN205016497U (en) | Survey test structure of chip layering | |
| CN105374765B (en) | A kind of chip seal ring structure and preparation method thereof | |
| CN102856227A (en) | Mixed scanning method of wafer device unit | |
| CN105424240A (en) | IC plastic packaging residual stress observation and comparison method | |
| CN105448857B (en) | A kind of chip seal ring structure and preparation method thereof | |
| JP5566433B2 (en) | Manufacturing method of semiconductor device | |
| CN101471320A (en) | Substrate encapsulation structure | |
| TW201519403A (en) | Packaged integrated circuit (IC) structure, wafer level package structure, and wafer packaging method | |
| CN106409714B (en) | Bare die test method and wafer | |
| CN106006547B (en) | The cutting method of MEMS wafer | |
| CN106442562B (en) | A method of breaking through open defect board detectable limit | |
| CN104992927A (en) | Sawing method for making wafer contain dies of a variety of different sizes | |
| CN104217975A (en) | Method for measuring IC (integrated circuit) plastic package gold wire offset | |
| CN104766808A (en) | Wafer defect density acquisition method, testing method and semiconductor device forming method | |
| JP3144633U (en) | Lead frame and semiconductor device | |
| CN204596773U (en) | A kind of structure preventing chip cutting layering |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141231 Termination date: 20190804 |