JP3144633U - Lead frame and semiconductor device - Google Patents

Lead frame and semiconductor device Download PDF

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Publication number
JP3144633U
JP3144633U JP2008004327U JP2008004327U JP3144633U JP 3144633 U JP3144633 U JP 3144633U JP 2008004327 U JP2008004327 U JP 2008004327U JP 2008004327 U JP2008004327 U JP 2008004327U JP 3144633 U JP3144633 U JP 3144633U
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chip mounting
wire
lead frame
mounting portion
semiconductor device
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秀和 谷澤
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Sanken Electric Co Ltd
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Sanken Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

【課題】リードフレームのチップ搭載部において、接着材の流れ広がりや接着材同士の干渉現象等を防ぐための構造を、簡単に任意位置に設定できるリードフレームおよび半導体装置を提供する。
【解決手段】リードフレームおよび半導体装置において、チップ搭載部上の隣接する各チップ搭載領域間に、ワイヤーボンディングを施している。このワイヤーにより、接着材の流れ広がりや干渉現象等を防止する。あらかじめ溝等の加工を必要としない汎用性のあるリードフレームを用いて、ワイヤーボンディング位置は任意に設定し、安価に信頼性の高いリードフレームおよび半導体装置を提供することを可能とする。また、ワイヤー上面に平坦部を形成することによって、チップ搭載部上とワイヤー間の隙間を無くしまたは隙間を狭めることで、流れ性の良い接着材に対しても、流れ広がりを防止することが可能である。
【選択図】図１The present invention provides a lead frame and a semiconductor device that can easily set a structure for preventing a spread of an adhesive material, an interference phenomenon between adhesive materials, and the like at an arbitrary position in a chip mounting portion of the lead frame.
In a lead frame and a semiconductor device, wire bonding is performed between adjacent chip mounting areas on a chip mounting portion. This wire prevents the spread of adhesive material and interference phenomenon. Using a versatile lead frame that does not require processing of grooves or the like in advance, the wire bonding position can be arbitrarily set, and a highly reliable lead frame and semiconductor device can be provided at low cost. In addition, by forming a flat part on the upper surface of the wire, it is possible to prevent the spread of flow even for adhesives with good flowability by eliminating or narrowing the gap between the chip mounting part and the wire. It is.
[Selection] Figure 1

Description

本考案は、リードフレームおよび半導体装置に関する。   The present invention relates to a lead frame and a semiconductor device.

以下、図３、図４を参照して背景技術を説明する。一般的に、リードフレームはリード端子２とチップ搭載部１からなっている。このチップ搭載部１の一方の主面には複数のチップ搭載領域が設けられており各チップ搭載領域にはトランジスタチップ３とＩＣチップ５がそれぞれ接着材４、６で固着されている。そして、リード端子２とトランジスタチップ３、ＩＣチップ５がそれぞれ金ワイヤー７で結ばれている。さらに、これら全体がモールド樹脂８で覆われている。   Hereinafter, the background art will be described with reference to FIGS. In general, the lead frame includes a lead terminal 2 and a chip mounting portion 1. A plurality of chip mounting areas are provided on one main surface of the chip mounting portion 1, and a transistor chip 3 and an IC chip 5 are fixed to each chip mounting area with adhesives 4 and 6, respectively. The lead terminal 2, the transistor chip 3, and the IC chip 5 are each connected by a gold wire 7. Further, these are entirely covered with the mold resin 8.

このような半導体装置において、接着材の流れ広がりや接着材同士の干渉現象等を防ぐ手段として下記特許文献１および下記特許文献２には、チップ搭載部１上の隣接する各チップ搭載領域間に、溝９等を設けている。   In such a semiconductor device, Patent Document 1 and Patent Document 2 listed below as means for preventing the spread of the adhesive material and the interference phenomenon between the adhesive materials include between adjacent chip mounting regions on the chip mounting portion 1. , Grooves 9 and the like are provided.

また、近年、半導体装置において、多岐にわたる電気的性能が要望され、搭載する半導体チップの外形寸法は多種にわたった構成が要求される。
実開昭６３−０７９６５１号公報 特開２００６−３０３２１６号公報 In recent years, semiconductor devices are required to have a wide variety of electrical performance, and the external dimensions of the semiconductor chip to be mounted are required to have various configurations.
Japanese Utility Model Publication No. 63-077951 JP 2006-303216 A

しかしながら、上記特許文献１および上記特許文献２に記載の半導体装置では、あらかじめリードフレームの前記チップ搭載部間にチップ外形寸法に合わせて溝を形成しなければならない。このことはリードフレームを専用化してしまい、異なる外形寸法のチップを搭載する場合、チップ外形寸法ごとに溝位置を設定した、多種類のリードフレームを用意しなければならないという問題点がある。   However, in the semiconductor devices described in Patent Document 1 and Patent Document 2, grooves must be formed in advance between the chip mounting portions of the lead frame in accordance with chip outer dimensions. This leads to a problem that the lead frame is dedicated, and when a chip having a different external dimension is mounted, a variety of lead frames having groove positions set for each external dimension of the chip must be prepared.

本考案は、これらの問題を解決するリードフレームおよび半導体装置を提供することを目的とするものである。   An object of the present invention is to provide a lead frame and a semiconductor device that solve these problems.

本考案によるリードフレームは、リード端子およびチップ搭載部を備えたリードフレームにおいて、前記チップ搭載部上の隣接する各チップ搭載領域間に、ワイヤーボンディングを施したことを特徴とする。あるいは、リード端子およびチップ搭載部を備えたリードフレームにおいて、前記チップ搭載部上の隣接する各チップ搭載領域間に、ワイヤーボンディングを施し、かつ前記ワイヤー上面に平坦部が形成されていることを特徴とする。   A lead frame according to the present invention is characterized in that, in a lead frame having a lead terminal and a chip mounting portion, wire bonding is performed between adjacent chip mounting regions on the chip mounting portion. Alternatively, in a lead frame including a lead terminal and a chip mounting portion, wire bonding is performed between adjacent chip mounting regions on the chip mounting portion, and a flat portion is formed on the upper surface of the wire. And

また、本考案による半導体装置は、チップ搭載部と前記チップ搭載部上に接着材を介して固着された複数のチップとを備えた半導体装置において、前記チップ搭載部上の隣接する各チップ搭載領域間に、ワイヤーボンディングを施したことを特徴とする。あるいは、チップ搭載部と前記チップ搭載部上に接着材を介して固着された複数のチップとを備えた半導体装置において、前記チップ搭載部上の隣接する各チップ搭載領域間に、ワイヤーボンディングを施し、かつ前記ワイヤー上面に平坦部が形成されていることを特徴とする。   Further, the semiconductor device according to the present invention is a semiconductor device comprising a chip mounting portion and a plurality of chips fixed on the chip mounting portion via an adhesive, and adjacent chip mounting regions on the chip mounting portion. It is characterized by wire bonding in between. Alternatively, in a semiconductor device including a chip mounting portion and a plurality of chips fixed on the chip mounting portion via an adhesive, wire bonding is performed between adjacent chip mounting regions on the chip mounting portion. And the flat part is formed in the said wire upper surface, It is characterized by the above-mentioned.

また、ワイヤーボンディングするワイヤーはアルミから形成されることを特徴とする。   Further, the wire to be wire-bonded is formed of aluminum.

前記リードフレームはチップ搭載部間に溝などが形成されていない、汎用的なものを用いて、チップ搭載工程前に、ワイヤーボンディング装置で、ワイヤーをボンディングすれば良く、製造工程内で、簡単に準備することが可能である。そして、前記ワイヤーは、任意の位置・長さ・高さに設定することが可能であり、素線・装置治具を交換することによって、ワイヤー線径も変更することが可能である。   The lead frame is a general purpose one with no grooves between the chip mounting parts, and it is only necessary to bond the wire with a wire bonding device before the chip mounting process. It is possible to prepare. And the said wire can be set to arbitrary positions, lengths, and heights, and it is also possible to change a wire diameter by replacing | exchanging a strand and an apparatus jig | tool.

以上のことから、本考案を用いることによって、ワイヤーがチップ搭載部上の隣接する各チップ搭載領域間の接着材の流れ広がりや干渉現象等を防止して、その位置は任意の位置・長さ・高さに設定することが可能であり、リードフレームはあらかじめ加工を必要とせず、加工の無い汎用性のあるものを共用して使用することが可能であり、上述した問題点を解決することができる。   From the above, by using the present invention, the wire prevents the spread of adhesive material between adjacent chip mounting areas on the chip mounting part, interference phenomenon, etc., and the position is arbitrary position / length・ It is possible to set the height, the lead frame does not need to be processed in advance, and it can be used with a versatile one that does not need to be processed. Can do.

また、ワイヤー上面を押しつぶし加工することによって、チップ搭載部上とワイヤー間の隙間を無くしまたは隙間を狭める事で、流れ性の良い接着材に対しても、流れ広がりを防止することが可能である。   Also, by crushing the upper surface of the wire, the gap between the chip mounting part and the wire can be eliminated or the gap can be narrowed. .

さらに、接着材が流れ広がっているチップ搭載部上には、ワイヤーボンディングすることが出来ないが、ワイヤー上面に平坦部を形成し、ここにワイヤーボンディングすることによって、複雑なワイヤー結線にも対応できる。   Furthermore, wire bonding cannot be performed on the chip mounting portion where the adhesive material is spreading, but a flat portion is formed on the upper surface of the wire, and wire bonding can be used here to cope with complicated wire connection. .

以下、本考案の実施形態として一実施例を図１、図２に基づいて説明する。   Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

図１は実施例の平面図を示したものである。リードフレームはリード端子２とチップ搭載部１からなっている。このチップ搭載部１の一方の主面には複数のチップ搭載領域が設けられており各チップ搭載領域にはトランジスタチップ３とＩＣチップ５がそれぞれ接着剤４、６で固着されている。そして、チップ搭載部１上の各チップ搭載領域間にアルミワイヤー１０をワイヤーボンディングし、リード端子２とトランジスタチップ３、ＩＣチップ５がそれぞれ金ワイヤー７で結ばれている。さらに、これら全体がモールド樹脂８で覆われている。   FIG. 1 shows a plan view of the embodiment. The lead frame includes a lead terminal 2 and a chip mounting portion 1. A plurality of chip mounting areas are provided on one main surface of the chip mounting portion 1, and the transistor chip 3 and the IC chip 5 are fixed to each chip mounting area with adhesives 4 and 6, respectively. Then, an aluminum wire 10 is wire-bonded between the chip mounting areas on the chip mounting portion 1, and the lead terminal 2, the transistor chip 3, and the IC chip 5 are respectively connected by gold wires 7. Further, these are entirely covered with the mold resin 8.

図２は図１の断面を示したものである。接着材４ははんだ、Ａｇペースト等であり、流れ広がりが発生し易い材料で形成されている。一方接着材６は接着材４とは異なる材料、例えば絶縁性エポキシ樹脂等であり、接着材４より流れ広がり発生し難い材料で形成される。本実施形態では本考案に基づいてチップ搭載部１上の各チップ搭載領域間にアルミワイヤー１０がワイヤーボンディングされており、これが接着材４の流れ止めとして機能する。したがって接着材４と接着材６の干渉を防止することが出来る。   FIG. 2 shows a cross section of FIG. The adhesive material 4 is solder, Ag paste, or the like, and is formed of a material that easily generates flow spread. On the other hand, the adhesive 6 is a material different from the adhesive 4, for example, an insulating epoxy resin, and is formed of a material that is less likely to flow and generate than the adhesive 4. In this embodiment, an aluminum wire 10 is wire-bonded between the chip mounting areas on the chip mounting portion 1 based on the present invention, and this functions as a flow stopper for the adhesive 4. Therefore, the interference between the adhesive 4 and the adhesive 6 can be prevented.

製造順序としては、チップ搭載部１について、無加工の汎用リードフレームを用いて、チップ搭載部１の各チップ搭載領域間にアルミワイヤーをワイヤーボンディングする。次に、各種接着材を介して、各種チップを搭載する。その後、電気配線のワイヤーボンディング、樹脂封止をおこなう。   As a manufacturing order, an aluminum wire is wire-bonded between the chip mounting regions of the chip mounting unit 1 with respect to the chip mounting unit 1 using an unprocessed general-purpose lead frame. Next, various chips are mounted via various adhesives. Thereafter, wire bonding of electrical wiring and resin sealing are performed.

アルミワイヤーはワイヤーボンディング装置の素材交換、ツール交換、条件変更することにより、アルミワイヤーボンディングの位置、長さ、高さを自由に設定することが可能である。これにより、汎用リードフレームを一つ用意すれば良く、製造時のワイヤーボンディング装置の条件設定のみで、多品種に簡単に対応できないという問題が解決できる。   The position, length, and height of the aluminum wire bonding can be freely set by changing the material of the wire bonding apparatus, changing the tool, and changing the conditions of the aluminum wire. Thereby, it is sufficient to prepare one general-purpose lead frame, and it is possible to solve the problem that it is not possible to easily deal with a wide variety of products only by setting the conditions of the wire bonding apparatus at the time of manufacture.

また、本考案の第2の実施形態として変形例を図５に示す。図５はアルミワイヤー１０部の断面拡大図である。アルミワイヤーボンディング後にアルミワイヤー１０上面を平坦になるように叩く等加工することによって、チップ搭載部１上とアルミワイヤー１０間の隙間をつぶし、流れ性の良い接着材、はんだ等に対しても、流れ広がりを防止することが可能である。   FIG. 5 shows a modification as the second embodiment of the present invention. FIG. 5 is an enlarged cross-sectional view of the aluminum wire 10 part. After the aluminum wire bonding, the upper surface of the aluminum wire 10 is struck so as to be flattened, so that the gap between the chip mounting portion 1 and the aluminum wire 10 is crushed. It is possible to prevent flow spread.

さらに、本考案の第３の実施形態として変形例を図６に示す。図６は第２の実施形態において平坦部を形成したアルミワイヤー１０上にワイヤーボンディングした断面拡大図である。通常、接着材が流れ広がっているチップ搭載部１上には、電気的配線としてワイヤーボンディングすることが出来ない。ワイヤーボンディングするスペースをとるためには、十分なチップ搭載部の面積が必要であり、製品外形寸法も拡大してしまう。このことをすること無く、本考案の第３の実施形態においては、アルミワイヤー１０上部の平坦部に、ワイヤー１１をワイヤーボンディングすることが可能であり、これにより、チップ搭載部１とリード２又は各素子への電気的配線が可能である。また、ワイヤー１１は金、銅、アルミ細線が可能である。   Furthermore, a modification is shown in FIG. 6 as 3rd Embodiment of this invention. FIG. 6 is an enlarged cross-sectional view of wire bonding on the aluminum wire 10 having a flat portion formed in the second embodiment. Usually, wire bonding cannot be performed as electrical wiring on the chip mounting portion 1 where the adhesive material is spreading. In order to take the space for wire bonding, a sufficient area of the chip mounting portion is necessary, and the product outer dimensions are also enlarged. Without doing this, in the third embodiment of the present invention, it is possible to wire-bond the wire 11 to the flat portion on the upper portion of the aluminum wire 10, and thereby the chip mounting portion 1 and the lead 2 or Electrical wiring to each element is possible. The wire 11 can be gold, copper, or aluminum fine wire.

は本考案における半導体装置の要部平面図である。These are the principal part top views of the semiconductor device in this invention. は本考案における図１の断面図である。FIG. 2 is a cross-sectional view of FIG. 1 in the present invention. は従来技術による半導体装置の要部平面図である。These are the principal part top views of the semiconductor device by a prior art. は従来技術による図３の断面図である。FIG. 4 is a cross-sectional view of FIG. 3 according to the prior art. は本考案のおける第２の実施形態の断面拡大図である。These are the cross-sectional enlarged views of 2nd Embodiment in this invention. は本考案における第３の実施形態の断面拡大図である。These are the expanded sectional views of 3rd Embodiment in this invention.

符号の説明Explanation of symbols

１、チップ搭載部
２、リード端子
３、トランジスタチップ
４、接着材
５、ＩＣチップ
６、接着材
７、金ワイヤー
８、モールド樹脂
９、溝
１０、アルミワイヤー
１１、ワイヤー 1. Chip mounting portion 2, lead terminal 3, transistor chip 4, adhesive material 5, IC chip 6, adhesive material 7, gold wire 8, mold resin 9, groove 10, aluminum wire 11, wire

Claims (6)

リード端子およびチップ搭載部を備えたリードフレームにおいて、前記チップ搭載部上の隣接する各チップ搭載領域間に、ワイヤーボンディングを施したことを特徴とするリードフレーム。 A lead frame having a lead terminal and a chip mounting portion, wherein a lead bonding is performed between adjacent chip mounting regions on the chip mounting portion. リード端子およびチップ搭載部を備えたリードフレームにおいて、前記チップ搭載部上の隣接する各チップ搭載領域間に、ワイヤーボンディングを施し、かつ前記ワイヤー上面に平坦部が形成されていることを特徴とするリードフレーム。 In a lead frame having a lead terminal and a chip mounting portion, wire bonding is performed between adjacent chip mounting regions on the chip mounting portion, and a flat portion is formed on the upper surface of the wire. Lead frame. チップ搭載部と前記チップ搭載部上に接着材を介して固着された複数のチップとを備えた半導体装置において、前記チップ搭載部上の隣接する各チップ搭載領域間に、ワイヤーボンディングを施したことを特徴とする半導体装置。 In a semiconductor device including a chip mounting portion and a plurality of chips fixed to the chip mounting portion via an adhesive, wire bonding is performed between adjacent chip mounting regions on the chip mounting portion. A semiconductor device characterized by the above. チップ搭載部と前記チップ搭載部上に接着材を介して固着された複数のチップとを備えた半導体装置において、前記チップ搭載部上の隣接する各チップ搭載領域間に、ワイヤーボンディングを施し、かつ前記ワイヤー上面に平坦部が形成されていることを特徴とする半導体装置。 In a semiconductor device including a chip mounting portion and a plurality of chips fixed on the chip mounting portion via an adhesive, wire bonding is performed between adjacent chip mounting regions on the chip mounting portion, and A semiconductor device, wherein a flat portion is formed on the upper surface of the wire. 前記ワイヤーはアルミから形成されていることを特徴とする請求項１または２に記載のリードフレーム。 The lead frame according to claim 1, wherein the wire is made of aluminum. 前記ワイヤーはアルミから形成されていることを特徴とする請求項３または４に記載の半導体装置。 The semiconductor device according to claim 3, wherein the wire is made of aluminum.
JP2008004327U 2008-06-26 2008-06-26 Lead frame and semiconductor device Expired - Fee Related JP3144633U (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014065124A1 (en) * 2012-10-25 2014-05-01 シャープ株式会社 Semiconductor device, and electronic device
WO2015079834A1 (en) * 2013-11-29 2015-06-04 シャープ株式会社 Semiconductor device
JP2016219665A (en) * 2015-05-22 2016-12-22 シャープ株式会社 Semiconductor device and manufacturing method of the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014065124A1 (en) * 2012-10-25 2014-05-01 シャープ株式会社 Semiconductor device, and electronic device
WO2015079834A1 (en) * 2013-11-29 2015-06-04 シャープ株式会社 Semiconductor device
JP2016219665A (en) * 2015-05-22 2016-12-22 シャープ株式会社 Semiconductor device and manufacturing method of the same

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