CN203911863U - Solar photovoltaic charging control apparatus - Google Patents
Solar photovoltaic charging control apparatus Download PDFInfo
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- CN203911863U CN203911863U CN201420277306.7U CN201420277306U CN203911863U CN 203911863 U CN203911863 U CN 203911863U CN 201420277306 U CN201420277306 U CN 201420277306U CN 203911863 U CN203911863 U CN 203911863U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The utility model discloses a solar photovoltaic charging control apparatus. A PWM signal driving component (6) comprises an RC low-pass filter (61), a PWM chip (62), and a logic gate circuit (63) connected in series and is used for providing driving signals of an auxiliary switch (31), a main switch (32), and a synchronous rectification switch (33) for a DC-DC converting component (3) according to a timing sequence and a PWM duty ratio signal of a microprocessor (5). The DC-DC converting component (3) is composed of the main switch (32) connected with a first resonant capacitor (C1) in parallel, the synchronous rectification switch (33) connected with a second resonant capacitor (C2) in parallel, the auxiliary switch (31), a resonant inductor (Lr), and a filtering inductor (Lf) and is used for successively turning off the synchronous rectification switch (33) in a zero-current manner, turning off the main switch (32) in a quasi-zero-voltage manner according to time set by a duty ration after the main switch (32) is turned on in a zero-voltage manner, and turning on the synchronous rectification switch (33) in a zero-voltage manner and making the steady voltage drop of the synchronous rectification switch (33) less than or equal to 0.1V. The solar photovoltaic charging control apparatus can be widely used in a large-power photovoltaic power generation system.
Description
Technical Field
The utility model relates to a charge control device, especially a solar photovoltaic charge control device.
Background
Photovoltaic charging power generation is a technology of converting light energy into electric energy by utilizing the photovoltaic effect in a solar cell array, and storing the electric energy in a storage battery for load use. When the technology is implemented, a photovoltaic charging controller needs to be arranged between a solar cell array and a storage battery, for example, a photovoltaic power generation charging control system disclosed in the design of the photovoltaic charging controller with MPPT control (12 months in 2011, volume 33, period 6, pages 61-64). The system mainly comprises a solar cell array, a storage battery and a controller, wherein the controller mainly comprises a DC-DC converter, a charging current and battery voltage detector, a PWM (pulse width modulation) driver, a microprocessor and the like. The DC-DC converter is a BUCK BUCK converter and mainly comprises a switching element working at a duty ratio, namely a P-channel power insulated gate field effect (MOS) tube, a diode, an inductor, a capacitor and a feedback loop; the PWM driver is a triode, the base electrode of the PWM driver is electrically connected with a PWM signal output by the microprocessor, and the collector electrode of the PWM driver is electrically connected with the grid electrode of the P-channel power MOS tube. During charging, the microprocessor selects a proper charging control mode through detection of charging current and voltage of the storage battery on one hand, and judges the working state of the photovoltaic cell on the other hand to determine whether Maximum Power Point Tracking (MPPT) control is carried out or not, and achieves a control target through adjustment of the duty ratio of the DC-DC converter. However, although the photovoltaic charging controller can detect the charging voltage and the charging current of the storage battery, under the condition of sufficient illumination intensity, the intelligent control of the storage battery is completed by adopting a common constant-current, constant-voltage and floating-charging three-stage charging control method according to the characteristics of the charged storage battery, and under the condition of insufficient illumination intensity, the intelligent control is automatically switched to an MPPT control state, so that the photovoltaic battery has the maximum power output by adopting a disturbance observation control strategy, thereby improving the power generation efficiency of the photovoltaic battery, but the photovoltaic charging controller also has the defects, firstly, the photovoltaic charging controller is only suitable for a small-sized and low-power photovoltaic power generation system, and for high power, particularly for the photovoltaic power generation system which needs large-current output, the efficiency of the system is low due to the overlarge power loss of a diode in the photovoltaic power generation system; secondly, because the P-channel power MOS tube is not in a zero voltage state when being switched on, the P-channel power MOS tube has larger impact current, and particularly for a high-power photovoltaic power generation system, the P-channel power MOS tube is easy to cause early damage for a long time.
SUMMERY OF THE UTILITY MODEL
The to-be-solved technical problem of the utility model is to overcome the weak point among the prior art, provide a rational in infrastructure, be suitable for powerful photovoltaic power generation system's solar photovoltaic charging controlling means.
For solving the technical problem of the utility model, the technical scheme who adopts is: the solar photovoltaic charging control device consists of a DC-DC conversion part and a microprocessor, wherein the DC-DC conversion part is connected between a photovoltaic panel connecting terminal and a storage battery connecting terminal in series, the input end of the microprocessor is electrically connected with a voltage and current detection part, and the output end of the microprocessor is electrically connected with the control end of the DC-DC conversion part through a PWM signal driving part, particularly,
the PWM signal driving part comprises an RC low-pass filter, a PWM chip and a logic gate circuit which are connected in series and is used for providing driving signals of an auxiliary switch, a main switch and a synchronous rectification switch to the DC-DC conversion part according to a time sequence according to a PWM duty ratio signal sent by the microprocessor;
the DC-DC conversion component is basically composed of a main switch with two parallel ends connected with a first resonance capacitor and a synchronous rectifier switch with two parallel ends connected with a second resonance capacitor in series and then bridged over the positive and negative ends of a photovoltaic panel wiring terminal, an auxiliary switch with one end electrically connected with the positive electrode of the photovoltaic panel wiring terminal and the other end electrically connected with the main switch and a contact of the synchronous rectifier switch through a resonance inductor, the contact electrically connected with the positive electrode of a storage battery wiring terminal through a filter inductor, the negative electrode of the storage battery wiring terminal electrically connected with the negative electrode of the photovoltaic panel wiring terminal and used for sequentially switching off the synchronous rectifier switch at a quasi-zero voltage according to a time set by a duty ratio after the synchronous rectifier switch is switched off at zero current and the main switch is switched on at zero voltage, and the steady-state voltage drop of the synchronous rectifier switch is less than or.
As a further improvement of the solar photovoltaic charging control device:
preferably, the RC low-pass filter is composed of a fifth resistor and a fourth capacitor, and is used for converting the digital quantity PWM signal from the microprocessor into an analog quantity PWM signal.
Preferably, the PWM chip is an integrated circuit chip UC3525A, pin a, pin B and pin GND are short-circuited, and pin IN + is connected to the output terminal of the RC low-pass filter and pin VDD is connected to the input terminal of the logic gate circuit, and is configured to output a duty cycle pulse signal of 0-100%.
Preferably, the logic gate circuit is composed of a main switch signal driving circuit, an auxiliary switch signal driving circuit and a synchronous rectification switch signal driving circuit respectively, and is used for sequentially sending an auxiliary switch driving signal, a main switch driving signal and a synchronous rectification switch driving signal according to a duty ratio pulse signal sent by the microprocessor;
the main switch signal driving circuit comprises a first NAND gate, a front dead zone RCD delay network, a second NAND gate, a main switch RCD delay network and a third NAND gate which are sequentially connected in series, wherein two enabling ends of the first NAND gate are connected with a VDD pin of an integrated circuit chip UC3525A, one enabling end of the second NAND gate is connected with a microprocessor, the microprocessor is used for driving the main switch and simultaneously forbidding the driving of the main switch when the microprocessor is in standby or needs to be protected,
the auxiliary switch signal driving circuit is a fourth NAND gate, a fifth NAND gate and a sixth NAND gate which are connected in series in sequence, wherein two enable terminals of the fourth NAND gate are connected with an output end of the third NAND gate, one enable terminal of the fifth NAND gate is connected with an output end of the second NAND gate, and one enable terminal of the sixth NAND gate is connected with the microprocessor, and is used for driving the auxiliary switch to be conducted for a period of time before the main switch is conducted, and simultaneously is used for forbidding the auxiliary switch from being driven by the microprocessor when in standby or in occasions needing protection,
the synchronous rectification switch signal driving circuit comprises a seventh NAND gate, a rear dead zone RCD delay network and an eighth NAND gate which are sequentially connected in series, wherein two enabling ends of the seventh NAND gate are connected with an output end of the first NAND gate, and one enabling end of the eighth NAND gate is connected with the current detection circuit, is used for driving the synchronous rectification switch, and is simultaneously used for closing the synchronous rectification switch when the DC-DC conversion component is in a current discontinuous state.
Preferably, the main switch is a second insulated gate field effect transistor, a second diode is connected in parallel between the source electrode and the drain electrode,
preferably, a second resistor is connected in parallel between the source electrode and the grid electrode of the second insulated gate field effect transistor, so that the second insulated gate field effect transistor is ensured not to be conducted by mistake;
preferably, the synchronous rectification switch is a third insulated gate field effect transistor, a third diode is connected in parallel between the source electrode and the drain electrode,
preferably, a third resistor is connected in parallel between the source electrode and the gate electrode of the third insulated gate field effect transistor, so that the third insulated gate field effect transistor is ensured not to be conducted by mistake;
preferably, the auxiliary switch is a first insulated gate field effect transistor, a first diode is connected in parallel between the source electrode and the drain electrode,
preferably, a first resistor is connected in parallel between the source and the gate of the first insulated gate field effect transistor, so that the first insulated gate field effect transistor is ensured not to be conducted by mistake.
Preferably, a filter capacitor is connected between the positive electrode and the negative electrode of the storage battery terminal in a crossing manner, and the filter capacitor is an electrolytic capacitor with the capacitance of 470 muF; the current transmitted to the storage battery is smoother.
Preferably, the negative pole of the photovoltaic panel connection terminal is grounded via a fourth resistor.
Preferably, the microprocessor is a single chip microcomputer with the model number of PIC16F 887; has higher cost performance.
Preferably, the voltage and current detection part is composed of a photovoltaic panel end voltage detector, a storage battery end voltage detector and a storage battery charging current detector, and a sampling data conversion part is connected in series between the voltage and current detection part and the microprocessor.
Preferably, the capacitance of the first resonance capacitor and the capacitance of the second resonance capacitor are both 1 muF, and the inductance of the resonance inductor is 3.3 muH.
Preferably, the conduction time T of the auxiliary switcha＝Lr×IRC/Uin+Tr/4, wherein LrIs a resonant inductor, IRCFor outputting rated current, UinFor photovoltaic panel voltage, TrIs the resonance period.
Preferably, the inductance of the filter inductor is set to make the peak value of the output current less than or equal to 10% of the rated current.
Compared with the prior art, the beneficial effects are that:
the utility model discloses an auxiliary switch, main switch and synchronous rectifier switch, and resonant capacitor, the DC-DC transform part that resonant inductor and filter inductance built jointly, its power loss is too big and lead to the inefficiency of photovoltaic power generation system when having avoided using the diode, it is supplementary by RC low pass filter again, the PWM signal driver part that PWM chip and logic gate circuit are constituteed, make auxiliary switch, main switch and synchronous rectifier switch open and turn-off according to the chronogenesis successively, both make main switch open about the under-zero voltage, make the main switch open the back and switch off under the quasi-zero voltage according to the time of duty cycle settlement again, still make synchronous rectifier switch open about the under-zero voltage, and its steady state voltage drop is less than or equal to 0.1V, more make synchronous rectifier switch open and turn-off under the zero current. The DC-DC conversion component and the PWM signal driving component with reasonable structure and the matching relation thereof thoroughly eliminate the defect that larger impact current is generated when each switch in the DC-DC conversion component is switched on and off through actual measurement, greatly reduce the loss of the switches, improve the performance of anti-electromagnetic interference, and ensure that the DC-DC conversion component is extremely suitable for a high-power photovoltaic power generation system, is particularly suitable for a photovoltaic power generation system with single-phase power more than or equal to 500W, and can be widely applied to the field of solar photovoltaic charging.
Drawings
Fig. 1 is a schematic diagram of a basic structure of the present invention.
Fig. 2 is a circuit configuration diagram of the PWM signal driving part of fig. 1.
Fig. 3 is a waveform diagram of the present invention. Fig. 3a is a timing diagram illustrating operation of the auxiliary switch, the main switch and the synchronous rectification switch in fig. 1; fig. 3b is a comparison graph of the output current waveform of the present invention and the prior art.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention will be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the embodiment described herein is the solar photovoltaic charging control device with a single power of 500W, and is only used for explaining the present invention, and is not used to limit the present invention. The charging voltage of the battery 7 is 12V, the maximum output voltage of the DC-DC converter 3 is 14.8V, and the maximum output current is 40A.
Referring to fig. 1, 2 and 3a, the solar photovoltaic charging control apparatus is basically composed of a microprocessor 5, a voltage current detection part 2, a sampling data conversion part 4, a PWM signal driving part 6 and a DC-DC conversion part 3. The microprocessor 5 has an input terminal electrically connected to the voltage/current detection unit 2 via the sampling data conversion unit 4, and an output terminal electrically connected to the DC-DC conversion unit 3 via the PWM signal drive unit 6. Wherein,
the microprocessor 5 selects a singlechip with the model number of PIC16F887, and the existing intelligent control algorithm is embedded in the singlechip, wherein the existing intelligent control algorithm comprises a maximum power tracking and constant voltage charging control method; the device is used for calculating the maximum output power of the photovoltaic panel 1 according to the terminal voltage of the photovoltaic panel 1, the voltage and the current of the storage battery 7, generating PWM pulse control signals by combining the charging voltage of the storage battery 7, forming main, auxiliary and synchronous rectification switch driving signals through the PWM signal driving part 6 to control the on-off of each switch in the DC-DC conversion part 3, and automatically enabling the DC-DC conversion part 3 to be adaptively switched between a continuous conduction mode and a discontinuous conduction mode.
The voltage and current detection part 2 consists of a photovoltaic panel end voltage detector, a storage battery end voltage detector and a storage battery charging current detector; the analog quantity signals of the collected terminal voltage of the photovoltaic panel 1, the terminal voltage of the storage battery 7 and the charging current are sent to the microprocessor 5 through the sampling data conversion component 4 to be processed.
The sampling data conversion part 4 is an analog-to-digital converter; for converting the analog signal from the voltage/current detection part 2 into digital data for the microprocessor 5 to process.
The PWM signal driving part 6 consists of an RC low-pass filter 61, a PWM chip 62 and a logic gate circuit 63 which are connected in series; for supplying the driving signals of the auxiliary switch 31, the main switch 32 and the synchronous rectification switch 33 to the DC-DC conversion part 3 in time sequence according to the PWM duty signal from the microprocessor 5. Wherein,
the RC low-pass filter 61 is composed of a fifth resistor R5 and a fourth capacitor C4.
The PWM chip 62 is an integrated circuit chip UC3525A, and the pin a and the pin B of the integrated circuit chip are short-circuited with the pin GND, and the pin IN + is connected to the output terminal of the RC low-pass filter 61, and the pin VDD is connected to the input terminal of the logic gate circuit 63, and is configured to output a duty ratio pulse signal of 0 to 100%.
The logic gate circuit 63 is composed of a MAIN switch signal driving circuit, an auxiliary switch signal driving circuit and a synchronous rectification switch signal driving circuit respectively, and is used for sequentially sending an auxiliary switch driving signal DRV _ AUX, a MAIN switch driving signal DRV _ MAIN and a synchronous rectification switch driving signal DRV _ SYNC according to a duty ratio pulse signal sent by the microprocessor 5; therein
The main switch signal driving circuit is a first nand gate F1, a front dead zone RCD delay network QSYS, a second nand gate F2, a main switch RCD delay network ZKYS and a third nand gate F3 which are connected in series in sequence, wherein two enable terminals of the first nand gate F1 are connected with a VDD pin of an integrated circuit chip UC3525A, one enable terminal of the second nand gate F2 is connected with the microprocessor 5, and the main switch signal driving circuit is used for driving the main switch 32 and simultaneously forbidding the driving of the main switch 32 by the microprocessor 5 in standby time or occasions needing protection;
the auxiliary switch signal driving circuit is a fourth nand gate F4, a fifth nand gate F5 and a sixth nand gate F6 which are connected in series in sequence, wherein two enabling ends of the fourth nand gate F4 are connected with the output end of the third nand gate F3, one enabling end of the fifth nand gate F5 is connected with the output end of the second nand gate F2, and one enabling end of the sixth nand gate F6 is connected with the microprocessor 5, and is used for driving the auxiliary switch 31 to be conducted for a period of time before the main switch 32 is conducted, and simultaneously used for forbidding the microprocessor 5 to drive the auxiliary switch 31 when in standby or in occasions needing protection;
the synchronous rectification switch signal driving circuit comprises a seventh nand gate F7, a rear dead zone RCD delay network HSYS and an eighth nand gate F8 which are sequentially connected in series, wherein two enabling ends of the seventh nand gate F7 are connected with an output end of the first nand gate F1, one enabling end of the eighth nand gate F8 is connected with the current detection circuit 64, the synchronous rectification switch 33 is driven, and the synchronous rectification switch signal driving circuit is used for enabling the DC-DC conversion component 3 to close the synchronous rectification switch 33 when the current is in an interrupted state.
The DC-DC conversion component 3 is composed of a main switch 32 with two ends connected in parallel with a first resonance capacitor C1 and a synchronous rectifier switch 33 with two ends connected in parallel with a second resonance capacitor C2, which are connected in series and then bridged at the positive and negative ends of a photovoltaic panel wiring terminal 11; the main switch 32 is a second insulated gate field effect transistor Q2, a second diode D2 is connected in parallel between the source and the drain of the main switch, a second resistor R2 is connected in parallel between the source and the gate of the main switch, the synchronous rectification switch 33 is a third insulated gate field effect transistor Q3, a third diode D3 is connected in parallel between the source and the drain of the synchronous rectification switch, a third resistor R3 is connected in parallel between the source and the gate of the synchronous rectification switch, and the capacitances of the first resonant capacitor C1 and the second resonant capacitor C2 are all 1 muf.
One end of the auxiliary switch 31 is electrically connected with the positive electrode of the photovoltaic panel wiring terminal 11, and the other end passes through the resonant inductor LrA contact 34 electrically connected to the main switch 32 and the synchronous rectification switch 33; the auxiliary switch 31 is a first insulated gate field effect transistor Q1, a first diode D1 is connected in parallel between the source and the drain, a first resistor R1 is connected in parallel between the source and the gate, and a resonant inductor LrInductance of 3.3 muH, the conduction time T of the auxiliary switch 31a＝Lr×IRC/Uin+Tr/4, wherein LrIs a resonant inductor, IRCFor outputting rated current, UinFor photovoltaic panel voltage, TrIs the resonance period.
Contact 34 via filter inductor LfIs electrically connected with the positive electrode of the storage battery connecting terminal 71; wherein, the filter inductance LfThe inductance is set so that the peak value of the output current is less than or equal to 10% of the rated current.
The negative pole of the battery terminal 71 is electrically connected to the negative pole of the photovoltaic panel terminal 11.
The filter capacitor C3, which is an electrolytic capacitor with a capacitance of 470 μ F, is connected between the positive and negative poles of the battery terminal 71.
The negative pole of the photovoltaic panel connection terminal 11 is connected to GND via a fourth resistor R4.
After receiving the PWM pulse control signal from the microprocessor 5, the PWM signal driving unit 6 in the solar photovoltaic charging control apparatus forms an analog quantity through filtering by the RC low-pass filter 61, and sends the analog quantity as a given signal to the PWM chip 62, i.e. the dedicated pulse width modulation integrated circuit chip UC 3525A; the chip has the functions of wave-by-wave current protection, current feedback, reference voltage, slope compensation and the like, and a pulse signal with the duty ratio of 0-100%, namely a PWM _ PLS signal, is output by a VDD pin of the chip.
The PWM _ PLS signal forms driving signals PRE _ UP and PRE _ DOWN of the UP (main switch and auxiliary switch) and DOWN (synchronous rectification switch) switches through two nand gates (first nand gate F1 and seventh nand gate F7), respectively. The two signals are respectively transmitted to two NAND gates (a second NAND gate F2 and an eighth NAND gate F8) through a dead zone forming RCD network (a front dead zone RCD delay network QSYS and a rear dead zone RCD delay network HSYS) to form upper and lower switch driving signals DT _ UP and DT _ DOWN with dead zones. The two driving signals are simultaneously and respectively controlled by the enable ends of the corresponding NAND gates, and the enable ends of the two driving signals are commonly connected to the microprocessor 5, so that the microprocessor 5 can prohibit the driving of the NAND gates when in standby or in occasions needing protection. The dead time of the two paths of signals DT _ UP and DT _ DOWN depends on the time constant of the corresponding RCD network.
The upper switch driving signal DT _ UP with the dead zone is delayed by the MAIN switch RCD delay network ZKYS and shaped by the third NAND gate F3 to become the MAIN switch driving signal DRV _ MAIN. The rising edge of the auxiliary switch driving signal DRV _ AUX comes directly from the driving signal PRE _ UP of the upper switch, but is disabled by the fourth nand gate F4 connected to the MAIN switch driving signal DRV _ MAIN at the moment when the rising edge of the MAIN switch driving signal DRV _ MAIN comes, so that the auxiliary switch 31 is turned on for a while and then enters the on period of the MAIN switch 32.
The lower switch driving signal DT _ DOWN with dead zone passes through the eighth nand gate F8 to generate the synchronous rectification switch driving signal DRV _ SYNC, the enable terminal of the eighth nand gate F8 is connected to the current detection circuit 64, and the synchronous rectification switch 33 can be turned off in the current discontinuous state of the DC-DC conversion component 3, so as to ensure no circulating current.
The DC-DC conversion part 3 in the solar photovoltaic charging control device enables the auxiliary switch 31, the main switch 32 and the synchronous rectification switch 33 to work cooperatively in each switching period under the driving of the corresponding switch driving signal sent by the PWM signal driving part 6, so as to control the photovoltaic panel voltage UinCurrent I of the photovoltaic panelinAt a suitable charging current IoutConversion to battery terminal voltage UoutThe specific working process of each switching cycle is as follows:
the auxiliary switch 31 is triggered to be turned on first by the auxiliary switch driving signal DRV _ AUX, and the synchronous rectification switch 33 is still in the follow current conducting state at this time, so the photovoltaic panel voltage UinAll loaded to the resonant inductor LrMake the resonant inductor current ILrAnd (4) increasing linearly. When the resonant inductor current ILrNot less than filter inductance current ILfAt this time, the charging current of the synchronous rectification switch 33 is zero, and the synchronous rectification switch is turned off at zero current.
Resonant inductor current ILrNot only providing output filter inductor current ILfSimultaneously participate in the resonance of the first resonance capacitor C1 and the second resonance capacitor C2, so that the voltage of the node 34 is raised to the photovoltaic panel voltage Uin. The auxiliary switch 31 is then turned off, creating a zero voltage conduction condition for the main switch 32.
The resonance process is terminated as the MAIN switch 32 is triggered by the MAIN switch driving signal DRV _ MAIN to turn on for less than or equal to 3 μ s before the auxiliary switch 31 is turned off, and the photovoltaic panel 1 transmits energy through the MAIN switch 32. The on-time of the main switch 32 is determined by the duty ratio of the PWM pulse control signal from the microprocessor 5, and the filter inductor current I is outputted during the on-time of the main switch 32LfProvided directly by the main switch 32. When the time that the main switch 32 is on reaches the set PWM value, the main switch 32 is turned off. The synchronous rectification switch 33 is not turned on at this time, and is referred to as a "dead zone". In the dead time, the resonant capacitors (the first resonant capacitor C1 and the second resonant capacitor C2) provide the output filter inductor current ILfAnd the voltage across the main switch 32 is slowly increased, so that the main switch 32 is turned off at a quasi-zero voltage. At the end of the dead time period, the voltage of the first resonant capacitor C1 rises to the input voltage, the photovoltaic panel voltage UinAnd the voltage drop of the second resonant capacitor C2 is zero, so that the terminal voltage of the synchronous rectification switch 33 is zero. The main switch 32 is turned on for the longest duration of the entire switching cycle, which can be up to 90% of the switching cycle, i.e. 30 microseconds.
Via a resonant inductor LrAnd the resonance (dead time) of the resonance capacitors (the first resonance capacitor C1 and the second resonance capacitor C2), the synchronous rectification switch 33 is turned on at zero voltage triggered by the synchronous rectification switch driving signal DRV _ SYNC. The output filter inductance current ILfThe synchronous rectification switch 33 continues to flow, and meanwhile, the steady-state voltage drop of the synchronous rectification switch 33 is less than or equal to 0.1V instead of 0.7V of the prior art, namely a diode, because the synchronous rectification switch driving signal DRV _ SYNC is continuously maintained. In the process, the photovoltaic panel 1 does not provide energy for the storage battery 7, but the DC-DC conversion component 3 outputs the filter inductor LfThe stored energy of which is released to the battery 7 through the synchronous rectification switch 33.
Charging current I of accumulatoroutIs determined by the conduction ratios of the main switch 32, the auxiliary switch 31 and the synchronous rectification switch 33.
The synchronous rectification switch drive signal DRV _ SYNC that triggers the synchronous rectification switch 33 is removed at the end of the switching period inherent to the DC-DC conversion section 3. However, unless the charging current IoutThe DC-DC converter section 3 is small (less than 10% of the rated current) and it is still in a conducting state when it operates in a continuous conducting mode. At the beginning of the next switching cycle, the auxiliary switch 31 and the resonant inductor L are neededrAnd realizing the commutation.
Use the utility model discloses a charging wave form diagram is shown as the curve in fig. 3b, can see out by it, uses the utility model discloses afterwards, it charges the wave form gently, has eliminated sharp-pointed burr completely, strikes the impact of electric current to each components and parts in the device promptly.
It is apparent that those skilled in the art can make various modifications and variations to the solar photovoltaic charging control apparatus of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. The utility model provides a solar photovoltaic charging control device, by DC-DC conversion part (3) that concatenates between photovoltaic board binding post (11) and battery binding post (71) to and microprocessor (5) that its input is connected with voltage current detection part (2) electricity, output are connected with the control end electricity of DC-DC conversion part (3) through PWM signal drive part (6) are constituteed, its characterized in that:
the PWM signal driving part (6) comprises an RC low-pass filter (61), a PWM chip (62) and a logic gate circuit (63) which are connected in series, and is used for providing driving signals of an auxiliary switch (31), a main switch (32) and a synchronous rectification switch (33) to the DC-DC conversion part (3) according to a PWM duty ratio signal sent by the microprocessor (5) in a time sequence;
the DC-DC conversion component (3) basically comprises a main switch (32) with two ends connected in parallel with a first resonant capacitor (C1) and a synchronous rectifier switch (33) with two ends connected in parallel with a second resonant capacitor (C2) which are connected in series and then bridged across the positive and negative ends of a photovoltaic panel wiring terminal (11), one end of an auxiliary switch (31) is electrically connected with the positive electrode of the photovoltaic panel wiring terminal (11), and the other end of the auxiliary switch is connected with the positive electrode of the photovoltaic panel wiring terminal (11) through a resonant inductor (L)r) Is electrically connected with the contact (34) of the main switch (32) and the synchronous rectification switch (33), and the contact (34) passes through the filter inductor (L)f) The synchronous rectification switch is electrically connected with the positive electrode of the storage battery connecting terminal (71), the negative electrode of the storage battery connecting terminal (71) is electrically connected with the negative electrode of the photovoltaic panel connecting terminal (11) and is used for sequentially enabling the synchronous rectification switch (33) to be turned off at zero current, the main switch (32) to be turned on at quasi-zero voltage according to time set by a duty ratio after the zero voltage is turned on, and the synchronous rectification switch (33) to be turned on at zero voltage and the steady-state voltage drop of the synchronous rectification switch is less than or equal to 0..
2. The solar photovoltaic charging control apparatus according to claim 1, wherein the RC low pass filter (61) is composed of a fifth resistor (R5) and a fourth capacitor (C4) for converting a digital PWM signal from the microprocessor (5) into an analog PWM signal.
3. The solar photovoltaic charging control device according to claim 1, wherein the PWM chip (62) is an integrated circuit chip UC3525A, the pin a and the pin B of which are shorted with the pin GND, the pin IN + is connected to the output terminal of the RC low pass filter (61), and the pin VDD is connected to the input terminal of the logic gate circuit (63), and is configured to output a duty cycle pulse signal of 0-100%.
4. The solar photovoltaic charging control device according to claim 1, wherein the logic gate circuit (63) is composed of a MAIN switch signal driving circuit, an auxiliary switch signal driving circuit and a synchronous rectification switch signal driving circuit, respectively, and is configured to sequentially send out an auxiliary switch driving signal (DRV _ AUX), a MAIN switch driving signal (DRV _ MAIN) and a synchronous rectification switch driving signal (DRV _ SYNC) according to the duty ratio pulse signal sent from the microprocessor (5);
the main switch signal driving circuit comprises a first NAND gate (F1), a front dead zone RCD delay network (QSYS), a second NAND gate (F2), a main switch RCD delay network (ZKYS) and a third NAND gate (F3) which are sequentially connected in series, wherein two enabling ends of the first NAND gate (F1) are connected with a VDD pin of an integrated circuit chip UC3525A and one enabling end of the second NAND gate (F2) is connected with a microprocessor (5) for driving the main switch (32) and simultaneously forbidding the driving of the main switch (32) by the microprocessor (5) in standby or occasions needing protection,
the auxiliary switch signal driving circuit is a fourth NAND gate (F4), a fifth NAND gate (F5) and a sixth NAND gate (F6) which are connected in series in sequence, wherein two enabling ends of the fourth NAND gate (F4) are connected with the output end of the third NAND gate (F3), one enabling end of the fifth NAND gate (F5) is connected with the output end of the second NAND gate (F2), and one enabling end of the sixth NAND gate (F6) is connected with the microprocessor (5) for driving the auxiliary switch (31) to be conducted for a period of time before the main switch (32) is conducted, and simultaneously for the microprocessor (5) to forbid driving the auxiliary switch (31) in standby or occasions needing protection,
the synchronous rectification switch signal driving circuit comprises a seventh NAND gate (F7), a rear dead zone RCD delay network (HSYS) and an eighth NAND gate (F8) which are sequentially connected in series, wherein two enable terminals of the seventh NAND gate (F7) are connected with the output end of the first NAND gate (F1), one enable terminal of the eighth NAND gate (F8) is connected with a current detection circuit (64) for driving the synchronous rectification switch (33), and the synchronous rectification switch signal driving circuit is used for turning off the synchronous rectification switch (33) when the DC-DC conversion component (3) is in a current interrupted state.
5. The solar photovoltaic charging control device according to claim 1, wherein the main switch (32) is a second insulated gate field effect transistor (Q2) having a second diode (D2) connected in parallel between the source and drain,
the synchronous rectification switch (33) is a third insulated gate field effect transistor (Q3), a third diode (D3) is connected in parallel between the source electrode and the drain electrode,
the auxiliary switch (31) is a first insulated gate field effect transistor (Q1) with a first diode (D1) connected in parallel between the source and drain.
6. The solar photovoltaic charging control device according to claim 1, wherein a filter capacitor (C3) is connected across the positive and negative electrodes of the battery terminal (71), and is an electrolytic capacitor having a capacitance of 470 μ F.
7. The solar photovoltaic charging control device according to claim 1, wherein the voltage current detecting part (2) is composed of a photovoltaic panel terminal voltage detector, a storage battery terminal voltage detector and a storage battery charging current detector, and a sampling data converting part (4) is connected in series between the voltage current detecting part and the microprocessor (5).
8. The solar photovoltaic charging control device according to claim 1, wherein the first resonant capacitor (C1) and the second resonant capacitor (C2) each have a capacitance of 1 μ F, and the resonant inductor (L) isr) The inductance of (2) was 3.3. mu.H.
9. The solar photovoltaic charging control device according to claim 8, wherein the conduction time T of the auxiliary switch (31) isa＝Lr×IRC/Uin+Tr/4, wherein LrIs a resonant inductor, IRCFor outputting rated current, UinFor photovoltaic panel voltage, TrIs the resonance period.
10. The solar photovoltaic charging control device according to claim 9, characterized by a filter inductance (L)f) The inductance is set so that the peak value of the output current is less than or equal to 10% of the rated current.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420277306.7U CN203911863U (en) | 2014-05-27 | 2014-05-27 | Solar photovoltaic charging control apparatus |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420277306.7U CN203911863U (en) | 2014-05-27 | 2014-05-27 | Solar photovoltaic charging control apparatus |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103997295A (en) * | 2014-05-27 | 2014-08-20 | 安徽循环经济技术工程院 | Solar photovoltaic charge control device |
| CN104883120A (en) * | 2015-01-12 | 2015-09-02 | 深圳硕日新能源科技有限公司 | MPPT photovoltaic charging control circuit capable of bidirectional charging |
| CN111030241A (en) * | 2019-12-27 | 2020-04-17 | 深圳一清创新科技有限公司 | Power battery charging system of automobile and control method thereof |
-
2014
- 2014-05-27 CN CN201420277306.7U patent/CN203911863U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103997295A (en) * | 2014-05-27 | 2014-08-20 | 安徽循环经济技术工程院 | Solar photovoltaic charge control device |
| CN104883120A (en) * | 2015-01-12 | 2015-09-02 | 深圳硕日新能源科技有限公司 | MPPT photovoltaic charging control circuit capable of bidirectional charging |
| CN104883120B (en) * | 2015-01-12 | 2016-06-08 | 深圳硕日新能源科技有限公司 | A kind of can the photovoltaic charged control circuit of MPPT of two-way charging |
| CN111030241A (en) * | 2019-12-27 | 2020-04-17 | 深圳一清创新科技有限公司 | Power battery charging system of automobile and control method thereof |
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