CN203851127U

CN203851127U - Digital buffer circuit carrying out reinforcement against total ionizing dose

Info

Publication number: CN203851127U
Application number: CN201420035180.2U
Authority: CN
Inventors: 姚素英; 李渊清; 徐江涛; 高静; 史再峰
Original assignee: Tianjin University
Current assignee: Tianjin University
Priority date: 2014-01-20
Filing date: 2014-01-20
Publication date: 2014-09-24
Anticipated expiration: 2024-01-20

Abstract

The utility model relates to the field of anti-radiation integrated circuit design in microelectronics. In order to implement a digital buffer circuit carrying out reinforcement against TID, the utility model adopts the following technical scheme: the digital buffer circuit carrying out reinforcement total ionizing dose comprises four PMOS transistors MP1, MP2, MP3 and MP4 and two NMOS transistors MN1 and MN2, VIN and NVIN are two complementary input signal ports and receive reversed-phase input signals, VOUT and NVOUT are two complementary output signal ports and output two reversed-phase signals, and the output level values of the ports VOUT and NVOUT are respectively in phase with VIN and NVIN. The digital buffer circuit of the utility model is mainly applied to anti-radiation integrated circuit design.

Description

The digit buffer circuit of reinforcing for integral dose radiation effect

Technical field

The utility model relates to the radiation hardened integrated circuit design field in microelectronics, relates in particular to and uses method for designing to carry out the reinforcing of integral dose radiation effect to the buffer circuits in digital circuit.

Background technology

Integral dose radiation effect (Total Ionizing Dose, TID) is to cause the one of the main reasons of the ic failure of applying in space environment.The Main physical mechanism of TID, is that radiation (electronics, gamma ray etc.) ionizes the oxide layer of chip, and leaves positive charge in oxide layer.To the oxide layer of different piece, the radiation damage form that TID causes is different, mainly comprise three kinds of forms: 1) TID causes positive charge accumulation in the gate oxide of MOS transistor, cause the threshold value of N channel transistor (NMOS) and p channel transistor (PMOS) that negative sense drift all occurs; 2) TID introduces positive charge in field oxide or shallow trench isolating oxide layer, cause NMOS raceway groove both sides to occur parasitic channel, electric leakage between source region and the drain region of initiation NMOS, this process is called device inside electric leakage (intra device leakage); 3) TID forms parasitic channel below field oxide or shallow trench isolating oxide layer, between two N-type regions that cause isolating mutually, leaks electricity, and this process is called electric leakage (inter device leakage) between device.At present, along with the continuous progress of integrated circuit technology, the continuous attenuate of transistorized gate oxide thickness, the above-mentioned the first radiation damage being caused by TID has no longer become principal element.But electric leakage still exists between device inside electric leakage and device.For leaking electricity between device, main method is to use high concentration P type doped region to isolate at present, uses guard ring structure.For device inside electric leakage, be mainly to adopt sealing gate transistor (Enclosed Gate NMOS, EGNMOS) structure.Using EGNMOS is cut-out parasitic channel to the leak electricity basic ideas of isolating of device inside, and this method has been proved to be the effective ways that TID is reinforced.But EGNMOS structure exists problems, comprise the restriction of minimum breadth length ratio, slower switching speed and larger area etc.

Summary of the invention

For overcoming the deficiencies in the prior art, realize the digit buffer circuit of reinforcing for TID, the technical solution adopted in the utility model is, the digit buffer circuit of reinforcing for integral dose radiation effect, comprise 4 PMOS transistor MP1, MP2, MP3 and MP4, and two nmos pass transistor MN1 and MN2; VIN and NVIN are two complementary input signal ports, accept anti-phase input signal.VOUT and NVOUT are two complementary output signal ports, export two anti-phase signals; Wherein, the output level value of VOUT and NVOUT port respectively with VIN and NVIN homophase; Each transistorized annexation is as follows: source, drain terminal and the grid end of MP1 is connected respectively ground, NVOUT and NVIN; Source, drain terminal and the grid end of MP2 is connected respectively ground, VOUT and VIN; Source, drain terminal and the grid end of MP3 are connected respectively power supply, NVOUT and VOUT; Source, drain terminal and the grid end of MP4 are connected respectively power supply, VOUT and NVOUT; Source, drain terminal and the grid end of MN1 are connected to respectively NVIN, NVOUT and VOUT; Source, drain terminal and the grid end of MN2 are connected to respectively VIN, VOUT and NVOUT.

Technical characterstic of the present utility model and effect:

1, this digit buffer is reinforced for TID effect based on circuit structure, only adopts common nmos pass transistor just can to leak electricity abatement device inside, has simplified design cycle;

2, this digit buffer circuit can provide complementary output.

Brief description of the drawings

Fig. 1 is the digit buffer the utility model proposes.

Embodiment

What the utility model proposes a kind of novelty carries out the thinking of radiation hardening for TID effect, not via cutting off leakage path, but eliminate the leakage current between the leakage of NMOS source by avoiding producing voltage difference between the leakage of nmos pass transistor source, and design a kind of digit buffer circuit of reinforcing for TID based on this design.

The digit buffer circuit of reinforcing for TID effect the utility model proposes as shown in Figure 1.This digit buffer circuit comprises 4 PMOS transistor MP1, MP2, MP3 and MP4, and two nmos pass transistor MN1 and MN2.VIN and NVIN are two complementary input signal ports, accept anti-phase input signal.VOUT and NVOUT are two complementary output signal ports, export two anti-phase signals.Wherein, the output level value of VOUT and NVOUT port respectively with VIN and NVIN homophase.Each transistorized annexation is as follows: source, drain terminal and the grid end of MP1 is connected respectively ground, NVOUT and NVIN; Source, drain terminal and the grid end of MP2 is connected respectively ground, VOUT and VIN; Source, drain terminal and the grid end of MP3 are connected respectively power supply, NVOUT and VOUT; Source, drain terminal and the grid end of MP4 are connected respectively power supply, VOUT and NVOUT; Source, drain terminal and the grid end of MN1 are connected to respectively NVIN, NVOUT and VOUT; Source, drain terminal and the grid end of MN2 are connected to respectively VIN, VOUT and NVOUT.

The course of work of this digit buffer is described with the situation of VIN=0, NVIN=1.Due to VIN=0, VOUT is pulled to low level by MP2 conducting, can produce threshold value loss because PMOS manages drop-down level, and therefore VOUT starts fashion and cannot pulled down to ground.Because VOUT pulled down to low level, therefore MP3 can conducting and NVOUT is carried out on draw.NVIN=1 turn-offs MP1.Therefore, NVOUT by move VDD to, and conducting MN2.After the conducting of MN2 pipe, VOUT is carried out drop-downly further, cause it and be thoroughly pulled down to ground.Now VOUT=0, NVOUT=1, the source-drain voltage of MN1 and MN2 equates, even if therefore its inside exists parasitic leakage raceway groove, also can not produce leakage current.The situation of VIN=1, NVIN=0 and above-mentioned analytic process are similar, repeat no more herein.

In Fig. 1, effectively drop-down for ensureing that MP1 and MP2 pipe can carry out respectively NVOUT and VOUT node, the minimum channel width that MP3 pipe and MP4 pipe channel width employing manufacturing process can provide.In addition, in layout design, between MN1 and MN2, and need to use P type guard ring to isolate between MN1 and MN2 and other circuit parts, with the generation that prevents from leaking electricity between device.

Claims

1. a digit buffer circuit of reinforcing for integral dose radiation effect, is characterized in that, comprises 4 PMOS transistor MP1, MP2, MP3 and MP4, and two nmos pass transistor MN1 and MN2; VIN and NVIN are two complementary input signal ports, accept anti-phase input signal, and VOUT and NVOUT are two complementary output signal ports, export two anti-phase signals; Wherein, the output level value of VOUT and NVOUT port respectively with VIN and NVIN homophase; Each transistorized annexation is as follows: source, drain terminal and the grid end of MP1 is connected respectively ground, NVOUT and NVIN; Source, drain terminal and the grid end of MP2 is connected respectively ground, VOUT and VIN; Source, drain terminal and the grid end of MP3 are connected respectively power supply, NVOUT and VOUT; Source, drain terminal and the grid end of MP4 are connected respectively power supply, VOUT and NVOUT; Source, drain terminal and the grid end of MN1 are connected to respectively NVIN, NVOUT and VOUT; Source, drain terminal and the grid end of MN2 are connected to respectively VIN, VOUT and NVOUT.