CN103985759A - A Depletion-mode PMOS Tube Structure Without Depletion Implantation - Google Patents

Abstract

The invention discloses a depletion-type PMOS transistor structure without depletion implantation, which changes the practice of using N-type impurity heavy doping in the prior art of polysilicon gates in the CMOS process to P-type impurity doping, and The P-type doping concentration is properly adjusted, and the work function difference between the polysilicon gate and silicon is changed to obtain a depletion-type PMOS transistor with a low pinch-off voltage. The invention does not need to add depletion layer photolithography and implantation, but only needs to change the doping type of gate polycrystal, which can reduce production cost and improve product competitiveness.

Description

A Depletion-mode PMOS Tube Structure Without Depletion Implantation

technical field

The invention discloses a depletion-type PMOS tube structure without depletion injection, and relates to the field of semiconductor manufacturing.

Background technique

CMOS (Complementary Metal Oxide Semiconductor), a complementary metal oxide semiconductor, a voltage-controlled amplifier device, is the basic unit of a CMOS digital integrated circuit. At present, in the mainstream mixed-signal CMOS process, depletion-type MOS transistors are widely used as memories and current sources.

PMOS (positive channel Metal Oxide Semiconductor, positive MOS) refers to an n-type substrate, a p-channel, and a MOS tube that transports current by the flow of holes. Metal-oxide-semiconductor field-effect (MOS) transistors can be divided into two categories: N-channel and P-channel. P-channel silicon MOS field-effect transistors have two P+ regions on the N-type silicon substrate, which are called source and P-channel respectively. Drain, there is no conduction between the two poles, and when sufficient positive voltage is applied to the source (the gate is grounded), the N-type silicon surface under the gate presents a P-type inversion layer, which becomes a channel connecting the source and drain . Changing the gate voltage can change the hole density in the channel, thus changing the resistance of the channel. This MOS field effect transistor is called a P-channel enhancement type field effect transistor. If there is no gate voltage on the surface of the N-type silicon substrate, there is a P-type inversion layer channel, and an appropriate bias voltage can increase or decrease the resistance of the channel. Such a MOS field effect transistor is called a P-channel depletion field effect transistor. Collectively referred to as PMOS transistors. A schematic diagram of a typical structure of a conventional depletion-mode PMOS transistor is shown in FIG. 1 . PMOS is on an N-type silicon substrate, through selective doping to form a P-type doped region, as the source and drain regions of the PMOS. The distance between the two doped source and drain regions is called the channel length, and the effective source and drain region dimension perpendicular to the channel length is called the channel width. For this simple structure, the source and drain of the device are completely symmetrical, and the specific source and drain can only be finally confirmed according to the flow direction of the source and drain current in the application. The working principle of PMOS is similar to that of NMOS. Because PMOS is an N-type silicon substrate, the majority carriers in it are electrons, the minority carriers are holes, and the doping type of the source and drain regions is P-type, so the working condition of PMOS is that the gate is relative to the source. Negative voltage is applied to the pole, that is, negatively charged electrons are applied to the gate of the PMOS, while movable positively charged holes and a depletion layer with fixed positive charges are induced on the substrate, regardless of the existence of The amount of positive charges induced in the substrate is equal to the amount of negative charges on the PMOS gate. When the strong inversion is achieved, under the action of the drain-source voltage which is negative relative to the source terminal, the positively charged holes at the source terminal reach the drain terminal through the conduction P-type channel, forming a source-drain current from source to drain. Similarly, the more negative VGS is (the larger the absolute value), the smaller the on-resistance of the channel and the larger the value of the current.

The above is the structure and working principle of the enhanced PMOS transistor. In the prior art, a certain negative voltage must be applied between the gate and the source to make the PMOS transistor conduct and flow current. The depletion-type PMOS tube, even when there is no voltage between the gate and the source, the depletion-type PMOS tube is in the on state, and a certain current flows; when a certain negative voltage is applied between the gate and the source , the on-resistance will decrease and the current will increase. In order to manufacture a depletion-type MOS transistor, it is necessary to add an additional depletion layer photolithography and implantation to form a permanent conductive channel with zero gate voltage, which will increase the production cost.

Contents of the invention

The technical problem to be solved by the present invention is to provide a depletion-type PMOS transistor structure without depletion implantation for the structural defects of the depletion-type PMOS transistor in the prior art, and to change the doping of the gate polysilicon from the current N-type The doping method is changed to P-type doping, and a depletion-type PMOS transistor with a low pinch-off voltage can be manufactured without adding depletion layer photolithography and implantation.

The present invention adopts the following technical solutions for solving the problems of the technologies described above:

A depletion-type PMOS tube structure without depletion implantation. A layer of N well is set on the upper surface of the P substrate. The N well diffuses downward from the surface of the silicon wafer in the PMOS tube area to form the back gate of the PMOS tube. A large active area, a small active area, and a field area are arranged at intervals on the silicon wafer in the tube area, and a gate oxide and a plurality of contact holes are provided on the upper surface of the large and small active area, and the field area The upper surface is provided with a field oxide to form the isolation between the large and small active regions, and the small active region is provided with an N+ implantation diffusion region, and the N+ implantation diffusion region is connected to the contact hole to form the lead-out of the back gate. The two ends of the large active region are respectively provided with P+ implantation diffusion regions, and the two P+ implantation diffusion regions are respectively connected to the contact holes to form the source and drain electrodes of the PMOS transistor. In the two places of the large active region A P-type doped polysilicon gate is arranged between the P+ implantation diffusion regions, and the P-type doped polysilicon gate extends to the field region to form the gate of the PMOS transistor.

As a further preferred solution of the present invention, a work function difference will be generated between the back gate of the PMOS transistor formed by the P-type doped polysilicon gate and the N well, so that a line is formed between the bottom of the gate of the PMOS transistor and the surface of the back gate. P-type conductive channel.

As a further preferred solution of the present invention, the thickness of the P-type doped polysilicon is 2500 Å.

As a further preferred solution of the present invention, the thickness of the field oxide is 3500˜5000 Å.

As a further preferred solution of the present invention, the thickness of the gate oxide is 125 Å.

As a further preferred solution of the present invention, the depth of the N well diffused downward from the surface of the silicon wafer in the PMOS transistor region is 2-4um.

As a further preferred solution of the present invention, an ohmic contact is formed between the N+ implantation diffusion region and the P+ implantation diffusion region and the contact hole through a metal wiring.

Compared with the depletion tube structure used in the prior art, the present invention adopts the above depletion-type PMOS tube structure, and has the following technical effects: in the traditional CMOS process, in order to manufacture the depletion-type MOS tube, the common practice is to add a depletion Depletion lithography and implantation, which increases production costs. In the depletion structure of the present invention, there is no need to add this depletion layer photolithography and implantation, only need to change the doping type of the gate poly, and a depletion PMOS with low pinch-off voltage can be produced Tube. This can reduce production costs and improve product competitiveness.

Description of drawings

FIG. 1 is a schematic diagram of a typical structure of a conventional depletion-mode PMOS transistor;

Fig. 2 is a schematic structural diagram of a depletion-type PMOS tube disclosed by the present invention without depletion injection;

Among them, 1. P substrate sheet, 2. N well, 3. Field oxide, 4. Gate oxide layer, 5. Depletion layer diffusion region is the conductive channel, 6. N-type heavily doped polysilicon gate, 6. -1. P-type doped polysilicon gate, 7. P+ implantation diffusion region, 8. N+ implantation diffusion region, 9. Contact hole.

Detailed ways

Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail:

The innovation of the present invention is to change the gate polysilicon doping from the common N-type heavy doping method to P-type doping, and to adjust the P-type doping concentration appropriately, thereby bringing polysilicon gate and silicon The work function difference between them makes the back gate surface under the polysilicon gate form a P-type conductive channel, thereby manufacturing a depletion-type PMOS transistor with low pinch-off voltage, and this method does not need to increase additional consumption Depletion lithography and implantation.

The schematic diagram of the structure of the depletion-type PMOS tube disclosed by the present invention that does not require depletion layer photolithography implantation is shown in Figure 2. The region of the depletion-type PMOS transistor is an N well, and the N-well diffuses downward from the surface of the silicon wafer to a depth of 2~4um to form the back gate of the depletion-type PMOS transistor. There are two active regions on the silicon surface of the depletion-type PMOS tube area: one small active region has N+ implanted diffusion region-forms ohmic contact through contact holes and metal wiring, and is used as the lead-out end of the back gate; the other large active region The active area is used to form a PMOS tube. Outside the active area is the field area. Above the field area is a 3500~5000? (Eggstrand, length unit, referred to as Angstrom) thick oxide, which is used as the isolation between the active areas; the silicon in the active area The surface is a layer of 125? thick oxide, and there is a 2500? P-type doped polysilicon in the middle local area above the oxide in the large active area and extends to the field area to form the gate of the PMOS transistor. The remaining area of the active area and both sides of the P-type doped polysilicon are P+ implanted diffusion areas, and the P+ diffusion areas form ohmic contacts through contact holes and metal wiring to form the source and drain of the PMOS device.

In the actual manufacturing process, by adjusting the doping concentration of P-type impurities, the pinch-off voltage of the depletion-type PMOS transistor can be fine-tuned. In order to make the change of the work function difference between the P-type impurity-doped polysilicon gate and the silicon not affect the turn-on voltage of the conventional MOS transistor, the present invention is applicable to the CMOS process that already has a high-resistance polysilicon blocking process, and the advantage is that it does not need to increase the cost. For a CMOS process that does not have a high-resistance polysilicon barrier process, the use of the present invention may require an additional high-resistance polysilicon barrier process, which is not conducive to reducing production costs.

The embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments, and can also be made without departing from the gist of the present invention within the scope of knowledge possessed by those of ordinary skill in the art. Variations.

Claims (7)

1. A depletion-type PMOS tube structure without depletion implantation, one layer of N well is set on the upper surface of the P substrate, and the N well diffuses downward from the silicon wafer surface in the PMOS tube area to form the back gate of the PMOS tube, A large active area, a small active area, and a field area are arranged at intervals on the silicon chip in the PMOS tube area, and gate oxide and a plurality of contact holes are provided on the upper surface of the large and small active area, and the field area The upper surface of the region is provided with a field oxide to form the isolation between the large and small active regions, and the small active region is provided with an N+ implantation diffusion region, and the N+ implantation diffusion region is connected to the contact hole to form a back gate The two ends of the large active region are respectively provided with P+ implantation diffusion regions, and the two P+ implantation diffusion regions are respectively connected to the contact holes to form the source and drain electrodes of the PMOS transistor. It is characterized in that: in the large A P-type doped polysilicon gate is arranged between two P+ implantation diffusion regions in the active region, and the P-type doped polysilicon gate extends to the field region to form the gate of the PMOS transistor. 2. A kind of depletion-type PMOS tube structure without depletion implantation as claimed in claim 1, characterized in that: work will be generated between the back gate of the PMOS tube formed by the P-type doped polysilicon gate and the N well. Function difference, thereby forming a P-type conductive channel on the surface of the back gate under the gate of the PMOS transistor. 3. A depletion-type PMOS transistor structure without depletion implantation as claimed in claim 1, wherein the thickness of the P-type doped polysilicon is 2500 Å. 4. A depletion-type PMOS transistor structure without depletion implantation as claimed in claim 1, characterized in that: the thickness of the field oxide is 3500-5000 Å. 5. A depletion-mode PMOS transistor structure without depletion implantation as claimed in claim 1, wherein the gate oxide has a thickness of 125 Å. 6. A depletion-type PMOS transistor structure without depletion implantation as claimed in claim 1, characterized in that: the depth of the N well diffused downward from the silicon wafer surface in the PMOS transistor region is 2-4um. 7. A depletion-type PMOS tube structure without depletion implantation as claimed in claim 1, wherein an ohmic contact is formed between the N+ implantation diffusion region and the P+ implantation diffusion region and the contact hole via a metal wiring .