CN103985759A - Depletion-free injected depletion type PMOS transistor structure - Google Patents
Depletion-free injected depletion type PMOS transistor structure Download PDFInfo
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- CN103985759A CN103985759A CN201410218056.4A CN201410218056A CN103985759A CN 103985759 A CN103985759 A CN 103985759A CN 201410218056 A CN201410218056 A CN 201410218056A CN 103985759 A CN103985759 A CN 103985759A
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- pmos
- injection
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- depletion type
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- 238000002347 injection Methods 0.000 claims abstract description 23
- 239000007924 injection Substances 0.000 claims abstract description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 238000009792 diffusion process Methods 0.000 claims description 23
- 238000010276 construction Methods 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 8
- 238000001259 photo etching Methods 0.000 abstract description 7
- 239000012535 impurity Substances 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 abstract description 3
- 239000004065 semiconductor Substances 0.000 description 10
- 230000005669 field effect Effects 0.000 description 6
- 238000005457 optimization Methods 0.000 description 6
- 230000008859 change Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000032258 transport Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a depletion-free injected depletion type PMOS tube structure. According to the method, N-type impurity heavy doping applied to a polycrystalline silicon grid in a CMOS technology in the prior art is changed to P-type impurity doping, and the P-type doping content is adjusted appropriately, and the work function difference between the polycrystalline silicon grid and silicon is changed to obtain a depletion type PMOS tube of low pinch-off voltage. According to the depletion-free injected depletion type PMOS tube structure, photoetching and injection of a depletion layer are not needed, only the doping types of grid polycrystals need to be changed, thus, production cost can be reduced, and product competitiveness can be improved.
Description
Technical field
The invention discloses the depletion type PMOS tubular construction that a kind of nothing exhausts injection, relate to field of semiconductor manufacture.
Background technology
CMOS(Complementary Metal Oxide Semiconductor), complementary metal oxide semiconductors (CMOS), voltage-controlled a kind of amplifying device, is the elementary cell that forms cmos digital integrated circuit.In the mixed signal CMOS of main flow technique, the metal-oxide-semiconductor that has been widely used depletion type is done memory, current source etc. at present.
PMOS(positive channel Metal Oxide Semiconductor, positive MOS) refer to N-shaped substrate, p raceway groove, by the mobile metal-oxide-semiconductor that transports electric current in hole.Metal oxide semiconductor field-effect (MOS) transistor can be divided into N raceway groove and the large class of P raceway groove two, P channel silicon MOS field-effect transistor is in N-type silicon substrate Shang Youliangge P+ district, be called respectively source electrode and drain electrode, admittance not between the two poles of the earth, while being added with enough positive voltages (grounded-grid) on source electrode, N-type silicon face under grid presents P type inversion layer, becomes the raceway groove that connects source electrode and drain electrode.Change grid voltage and can change the hole density in raceway groove, thereby change the resistance of raceway groove.This MOS field-effect transistor is called P-channel enhancement type field-effect transistor.If N-type surface of silicon does not add grid voltage, just there is not P type inversion-layer channel, add suitable bias voltage, can make the resistance of raceway groove increase or reduce.Such MOS field-effect transistor is called P channel depletion type field-effect transistor.Be referred to as PMOS transistor.Conventional depletion type PMOS pipe typical structure schematic diagram as shown in Figure 1.PMOS is on the substrate of N-type silicon, is adulterated and is formed the doped region of P type, as the source-drain area of PMOS by selection.Distance between leakage doped region, two sources is called channel length, and is called channel width perpendicular to effective source-drain area size of channel length.For this simple structure, it is full symmetric that device source is leaked, and only in application, according to the flow direction of source-drain current, could finally confirm concrete source and leakage.Operation principle and the NMOS of PMOS are similar.Because PMOS is N-type silicon substrate, majority carrier is wherein electronics, minority carrier is hole, the doping type of source-drain area is P type, so, the condition of work of PMOS is with respect to source electrode, to apply negative voltage on grid, that is what on the grid of PMOS, apply is negative electrical charge electronics, and be movable positive charge hole and with the depletion layer of fixed positive charge in substrate induction, do not consider the impact of the electric charge that exists in silicon dioxide, the positive charge quantity of responding in substrate just equals the quantity of the negative electrical charge on PMOS grid.When reaching strong inversion, with respect to source, be under the effect of negative drain-source voltage, the positive charge hole of source arrives drain terminal through the P type raceway groove of conducting, forms from source to the source-drain current leaking.Similarly, VGS more negative (absolute value is larger), the conducting resistance of raceway groove is less, and the numerical value of electric current is larger.
Introducing is above structure and the operation principle of enhancement mode PMOS pipe, must between grid and source electrode, apply certain negative voltage and just can make the conducting of PMOS pipe, current flowing in prior art.And depletion type PMOS pipe, even between grid and source electrode during no-voltage, depletion type PMOS manages also in conducting state, flows through certain electric current; When applying certain negative voltage between grid and source electrode, conducting resistance can reduce, and electric current can increase.In order to manufacture the metal-oxide-semiconductor of depletion type, need extra increase a depletion layer photoetching and injection, to form the permanent conducting channel under zero grid voltage, this can bring the increase of production cost.
Summary of the invention
Technical problem to be solved by this invention is: for the fault of construction of depletion type PMOS pipe in prior art, the depletion type PMOS tubular construction that provides a kind of nothing to exhaust injection, the way that the doping of grid polycrystalline silicon is adulterated by the N-type of passing through changes P type into and adulterates, do not need to increase depletion layer photoetching and injection, just can produce the depletion type PMOS pipe of a low pinch-off voltage.
The present invention is for solving the problems of the technologies described above by the following technical solutions:
A kind of nothing exhausts the depletion type PMOS tubular construction of injection, upper surface at P substrate slice arranges one deck N trap, N trap spreads downwards from the silicon chip surface in territory, pmos area, form the back of the body grid of PMOS pipe, on the silicon chip in territory, pmos area, interval is provided with large active area, little active area and place, described large, the upper surface of little active area is provided with gate oxide and a plurality of contact hole, the upper surface of described place is provided with field oxide and forms large, isolation between little active area, place, described little active area is provided with N+ and injects diffusion region, described N+ injects diffusion region and is connected with contact hole, form the exit of back of the body grid, the two ends of described large active area are respectively arranged with P+ and inject diffusion region, two P+ of place inject diffusion region and are connected with contact hole respectively, form source electrode and the drain electrode of PMOS pipe, two P+ of place in large active area inject between diffusion region and are provided with P type doped polysilicon gate, described P type doped polysilicon gate extends to place, form the grid of PMOS pipe.
As present invention further optimization scheme, between the back of the body grid of the PMOS pipe that described P type doped polysilicon gate and N trap form, will produce work function difference, and then make the grid below of PMOS pipe and carry on the back between grid surface to form a P-type conduction raceway groove.
As present invention further optimization scheme, the thickness of described P type doped polycrystalline silicon is 2500.
As present invention further optimization scheme, the thickness of described field oxide is 3500 ~ 5000.
As present invention further optimization scheme, the thickness of described gate oxide is 125.
As present invention further optimization scheme, described N trap is 2 ~ 4um from the degree of depth of the downward diffusion of silicon chip surface in territory, pmos area.
As present invention further optimization scheme, between described N+ injection diffusion region and P+ injection diffusion region and contact hole are logical, by metal line, form ohmic contact.
The present invention adopts above depletion type PMOS tubular construction to compare with the tubular construction that exhausts using in prior art, there is following technique effect: in traditional CMOS technique, for manufacturing the metal-oxide-semiconductor of depletion type, current way is to increase a depletion layer photoetching and injection, and this can increase production cost.Of the present invention, exhaust in tubular construction, do not need to increase current depletion layer photoetching and injection, only need to change the doping type type of grid polycrystalline, just can produce a kind of depletion type PMOS pipe of low pinch-off voltage.This can reduce production cost, improves product competitiveness.
Accompanying drawing explanation
Fig. 1 is conventional depletion type PMOS pipe typical structure schematic diagram;
Fig. 2 is the depletion type PMOS tubular construction schematic diagram that nothing disclosed by the invention exhausts injection;
Wherein, 1.P substrate slice, 2.N trap, 3. field oxide, 4. gate oxide thing, 5. depletion layer diffusion region is also conducting channel, 6.N type heavily doped polysilicon grid, 6-1.P type doped polysilicon gate, 7.P+ injects diffusion region, and 8. N+ injects diffusion region, 9. contact hole.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail:
Innovative point of the present invention is to be that by the heavily doped way of the N-type of passing through, changing grid polycrystalline silicon doping into P type adulterates, and P type doping content is suitably adjusted, bring thus work function difference between polysilicon gate and silicon just to make the back of the body grid surface below polysilicon gate form a P-type conduction raceway groove, thereby the depletion type PMOS pipe that produces a kind of low pinch-off voltage, such way does not need to increase extra depletion layer photoetching and injection simultaneously.
Disclosed by the inventionly do not need depletion type PMOS tubular construction schematic diagram that depletion layer photoetching injects as shown in Figure 2, the described depletion type PMOS tubular construction that does not exhaust injection is: in the territory, depletion type pmos area of P substrate slice upper surface, be a N trap, diffusion 2 ~ 4um is dark downwards from silicon chip surface for N trap, forms the back of the body grid of depletion type PMOS pipe.Silicon face in territory, depletion type pmos area has two active areas: a little active area has N+ to inject diffusion region---by contact hole and metal line, form ohmic contact, as the exit of back of the body grid; The active area that another is large, is used for forming PMOS pipe.Outside active area, being exactly place, is 3500 ~ 5000 (dust Gus spy is bright, and long measure is called for short dust) thick oxide above place, as the isolation between active area; The silicon face of active area is the oxide that one deck 125 is thick, and on the oxide of large active area, middle regional area has the P type doped polycrystalline silicon of 2500 and extends on place, forms the grid of PMOS pipe.The both sides of the remaining region of this active area, P type doped polycrystalline silicon are that P+ injects diffusion region, and P+ diffusion region forms ohmic contact by contact hole and metal line, forms source, the leakage of PMOS device.
Doing in process of actual system, by adjusting the doping content of p type impurity, can finely tune the pinch-off voltage of depletion type PMOS pipe.In order to make the work function difference between p type impurity doped polycrystalline silicon grid and silicon change the cut-in voltage that does not affect conventional metal-oxide-semiconductor, the present invention is applicable to itself and has the CMOS technique that high resistance polysilicon stops operation, and advantage is without increasing cost.For itself not having high resistance polysilicon to stop the CMOS technique of technique, use the present invention may need additionally to increase high resistance polysilicon and stop operation, unfavorable to reducing production cost.
By reference to the accompanying drawings embodiments of the present invention are explained in detail above, but the present invention is not limited to above-mentioned execution mode, in the ken possessing those of ordinary skills, can also under the prerequisite that does not depart from aim of the present invention, makes a variety of changes.
Claims (7)
1. a nothing exhausts the depletion type PMOS tubular construction of injection, upper surface at P substrate slice arranges one deck N trap, N trap spreads downwards from the silicon chip surface in territory, pmos area, form the back of the body grid of PMOS pipe, on the silicon chip in territory, pmos area, interval is provided with large active area, little active area and place, described large, the upper surface of little active area is provided with gate oxide and a plurality of contact hole, the upper surface of described place is provided with field oxide and forms large, isolation between little active area, place, described little active area is provided with N+ and injects diffusion region, described N+ injects diffusion region and is connected with contact hole, form the exit of back of the body grid, the two ends of described large active area are respectively arranged with P+ and inject diffusion region, two P+ of place inject diffusion region and are connected with contact hole respectively, form source electrode and the drain electrode of PMOS pipe, it is characterized in that: two P+ of place in large active area inject between diffusion region and are provided with P type doped polysilicon gate, described P type doped polysilicon gate extends to place, form the grid of PMOS pipe.
2. a kind of nothing as claimed in claim 1 exhausts the depletion type PMOS tubular construction of injection, it is characterized in that: between the back of the body grid of the PMOS pipe that described P type doped polysilicon gate and N trap form, will produce work function difference, and then make to form a P-type conduction raceway groove on the back of the body grid surface below the grid of PMOS pipe.
3. a kind of nothing as claimed in claim 1 exhausts the depletion type PMOS tubular construction of injection, it is characterized in that: the thickness of described P type doped polycrystalline silicon is 2500.
4. a kind of nothing as claimed in claim 1 exhausts the depletion type PMOS tubular construction of injection, it is characterized in that: the thickness of described field oxide is 3500 ~ 5000.
5. a kind of nothing as claimed in claim 1 exhausts the depletion type PMOS tubular construction of injection, it is characterized in that: the thickness of described gate oxide is 125.
6. a kind of nothing as claimed in claim 1 exhausts the depletion type PMOS tubular construction of injection, it is characterized in that: described N trap is 2 ~ 4um from the degree of depth of the downward diffusion of silicon chip surface in territory, pmos area.
7. a kind of nothing as claimed in claim 1 exhausts the depletion type PMOS tubular construction of injection, it is characterized in that: between described N+ injection diffusion region and P+ injection diffusion region and contact hole are logical, by metal line, form ohmic contact.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410218056.4A CN103985759A (en) | 2014-05-22 | 2014-05-22 | Depletion-free injected depletion type PMOS transistor structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410218056.4A CN103985759A (en) | 2014-05-22 | 2014-05-22 | Depletion-free injected depletion type PMOS transistor structure |
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| CN103985759A true CN103985759A (en) | 2014-08-13 |
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| CN201410218056.4A Pending CN103985759A (en) | 2014-05-22 | 2014-05-22 | Depletion-free injected depletion type PMOS transistor structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108807379A (en) * | 2017-05-05 | 2018-11-13 | 立锜科技股份有限公司 | The vague and general type MOS elements of high pressure with adjustable critical voltage and its manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5648288A (en) * | 1992-03-20 | 1997-07-15 | Siliconix Incorporated | Threshold adjustment in field effect semiconductor devices |
| CN1331495A (en) * | 2000-07-04 | 2002-01-16 | 株式会社东芝 | Horizontal semiconductor device |
| CN102136425A (en) * | 2010-01-22 | 2011-07-27 | 北大方正集团有限公司 | P-channel depletion MOS (metal oxide semiconductor) transistor and preparation method thereof |
-
2014
- 2014-05-22 CN CN201410218056.4A patent/CN103985759A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5648288A (en) * | 1992-03-20 | 1997-07-15 | Siliconix Incorporated | Threshold adjustment in field effect semiconductor devices |
| CN1331495A (en) * | 2000-07-04 | 2002-01-16 | 株式会社东芝 | Horizontal semiconductor device |
| CN102136425A (en) * | 2010-01-22 | 2011-07-27 | 北大方正集团有限公司 | P-channel depletion MOS (metal oxide semiconductor) transistor and preparation method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108807379A (en) * | 2017-05-05 | 2018-11-13 | 立锜科技股份有限公司 | The vague and general type MOS elements of high pressure with adjustable critical voltage and its manufacturing method |
| CN108807379B (en) * | 2017-05-05 | 2021-08-27 | 立锜科技股份有限公司 | High-voltage depletion type MOS (Metal oxide semiconductor) element with adjustable threshold voltage and manufacturing method thereof |
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Application publication date: 20140813 |
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