CN203813866U - High-sensitivity CMOS image sensor shared-type pixel structure - Google Patents
High-sensitivity CMOS image sensor shared-type pixel structure Download PDFInfo
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- CN203813866U CN203813866U CN201420222723.1U CN201420222723U CN203813866U CN 203813866 U CN203813866 U CN 203813866U CN 201420222723 U CN201420222723 U CN 201420222723U CN 203813866 U CN203813866 U CN 203813866U
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Abstract
The utility model discloses a high-sensitivity CMOS image sensor shared-type pixel structure, comprising a plurality of photodiodes and charge transmission transistors in the same number, and a first floating active area. The structure also comprises a reset transistor, a source following transistor, a row selection transistor, and a second floating active area. The first floating active area and the second floating active area are separated by a switch transistor. The source following transistor detects potential signals of the second floating active area. Stray capacitance of the second floating active area does not change with shared pixel quantity, thereby effectively improving photovoltaic conversion gain of the shared-type pixel, and effectively improving luminous sensitivity of a CMOS image sensor using the shared-type pixel structure.
Description
Technical field
The utility model relates to a kind of imageing sensor, relates in particular to the shared dot structure of a kind of high sensitivity cmos image sensor.
Background technology
Imageing sensor has been widely used in digital camera, cell phone, medicine equipment, automobile and other application scenarios.Particularly manufacture the fast development of CMOS (CMOS (Complementary Metal Oxide Semiconductor)) image sensor technologies, make people have higher requirement to the output image quality of imageing sensor.
Cmos image sensor of the prior art, particularly adopts the cmos image sensor of small size pixel cell, generally uses shared dot structure, for example two pixel sharings, four pixel sharings, or more pixel sharing.Adopting the major reason of pixel sharing, is to save transistor, to expand the area of photodiode, and then improves the luminous sensitivity of pixel; But the mode of this raising luminous sensitivity, but sacrificed the opto-electronic conversion gain of floating active area, because the charge pass transistor of the each pixel in shared structure is connected with floating active area, and then increase the parasitic capacitance of floating active area, shared pixel quantity is more, the parasitic capacitance of floating active area is larger, so opto-electronic conversion gain is lower; The opto-electronic conversion gain of pixel is lower, and luminous sensitivity is lower, and the original intention that this method proper and employing expansion photoelectricity secondary area improves luminous sensitivity is disagreed.
Imageing sensor of the prior art, taking cmos image sensor four pixel sharing structures of four transistors (4T4S) as example, as shown in Figure 1,101～104 are respectively the photodiode of four pixels, and 105～108 are respectively the charge pass transistor of corresponding four photodiodes, and 109 is reset transistor, 110 for following transistor in source, 111 is row selecting transistor, and 112 is row bit line, and FD is floating active area; Wherein FD capacitive part, C1 is the grid source overlap capacitance of FD and each charge transfer transistor gate, and C2 is the grid source overlap capacitance of FD and 109, and C3 and C4 are respectively grid leak and the grid source overlap capacitance of FD and 110, Cm4 is FD line metal parasitic capacitance, and 4Caa is FD active area body capacitance.
The total capacitance that as shown in Figure 1, can draw FD is:
CFD4＝4C1+C2+C3+C4+Cm4+4Caa
Coefficient 4 in 4C1 and 4Caa in equation equates with the pixel quantity in shared structure, and Cm4 is proportional to pixel quantity.Therefore the parasitic total capacitance that can calculate N pixel sharing structure Zhong FD district is:
CFDn＝nC1+C2+C3+C4+Cmn+nCaa
N in above-mentioned equation is larger, and the transistor that pixel is on average saved is more, and then the area that the photodiode of pixel expands is more, and pixel sensitivity degree will be higher; But the n in equation is larger, floating active area total capacitance CFDn is higher, thereby has reduced opto-electronic conversion gain, and the luminous sensitivity of pixel is lower, and this disagrees with the original intention that the method that adopts expansion photodiode area improves luminous sensitivity.
Utility model content
The purpose of this utility model is to provide the shared dot structure of a kind of high sensitivity cmos image sensor, by adopting switching transistor to isolate the floating active area method of little parasitic capacitance, makes the opto-electronic conversion gain of pixel not affected by shared pixel quantity.
The purpose of this utility model is achieved through the following technical solutions:
The shared dot structure of high sensitivity cmos image sensor of the present utility model, comprise charge pass transistor and the first floating active area of multiple photodiodes and equal number, also comprise that a reset transistor, source follow transistor, row selecting transistor and the second floating active area, between described the first floating active area and the second floating active area, separate by a switching transistor.
The technical scheme being provided by above-mentioned the utility model can be found out, the shared dot structure of high sensitivity cmos image sensor that the utility model provides, owing to using switching transistor that the first larger parasitic capacitance floating active area and less the second floating active area of parasitic capacitance are separated, the electric potential signal of the second floating active area is followed transistor and is surveyed in source, the parasitic capacitance of the second floating active area does not change with shared pixel quantity, effectively improve the opto-electronic conversion gain of shared pixel, can effectively improve the luminous sensitivity of the cmos image sensor that adopts shared dot structure.
Brief description of the drawings
Fig. 1 is the circuit diagram of four pixel sharing structures of four transistors (4T4S) of the cmos image sensor of prior art.
Fig. 2 is the circuit diagram of four pixel sharing structures of the cmos image sensor in the utility model embodiment.
Fig. 3 is shared pixel in the utility model embodiment potential well schematic diagram one in the time of photoelectricity transfer operation.
Fig. 4 is shared pixel in the utility model embodiment potential well schematic diagram two in the time of photoelectricity transfer operation.
Embodiment
To be described in further detail the utility model embodiment below.
The shared dot structure of high sensitivity cmos image sensor of the present utility model, its preferably embodiment be:
Comprise charge pass transistor and the first floating active area of multiple photodiodes and equal number, also comprise that a reset transistor, source follow transistor, row selecting transistor and the second floating active area, between described the first floating active area and the second floating active area, separate by a switching transistor.
The drain electrode of described switching transistor is connected with described the second floating active area, source electrode is connected with described the first floating active area.
Described source is followed transistorized grid and is connected with described the second floating active area, and described source is followed transistor and changed for the electric potential signal of surveying described the second floating active area.
In the shared dot structure of this high sensitivity cmos image sensor, the pixel quantity that shared pixel packets contains is more than or equal to two.
The variation of the quantity that the parasitic total capacitance of described the second floating active area does not contain with shared pixel packets changes.
In the time carrying out the transfer operation of photoelectricity electric charge, the electromotive force of described the first floating active area exhausts electromotive force 0V～0.3V completely higher than described photodiode.
Described the first floating active area comprises that source transistor leaks the active area of active area or photodiode technique.
Described photodiode comprises Pin type photodiode, part Pin type photodiode or polysilicon gate type photodiode.
The shared dot structure of high sensitivity cmos image sensor of the present utility model, owing to using switching transistor that the first larger parasitic capacitance floating active area and less the second floating active area of parasitic capacitance are separated, the electric potential signal of the second floating active area is followed transistor and is surveyed in source, the parasitic capacitance of the second floating active area does not change with shared pixel quantity, effectively improve the opto-electronic conversion gain of shared pixel, the sensitivity that can effectively improve the cmos image sensor that adopts shared dot structure.
Specific embodiment:
In embodiment of the present utility model, taking cmos image sensor four pixel sharing structures as example, in this dot structure, adopt Pin type N-type photodiode, the transistor in pixel adopts N-type transistor.
As shown in Figure 2, comprise that charge pass transistor 205～208, reset transistor 209, source in photodiode 201～204, four pixels of four pixels in shared structure follow transistor 210, row selecting transistor 211, row bit line 212, switching transistor 213; The gate terminal of charge pass transistor 205～208 is respectively TX1, TX2, TX3 and TX4, and the gate terminal of reset transistor 209 and row selecting transistor 211 is RX and SX, and the gate terminal of switching transistor 213 is TX, and Vdd is supply voltage; FD4 is the first floating active area, and FD is the second floating active area, and C1 is the overlap capacitance of FD and TX, C2 is the overlap capacitance of FD and RX, C3 and C4 are respectively the drain electrode of FD and 210 and the overlap capacitance of source electrode, and Cm1 is FD metal capacitance, and Caa is FD active area body capacitance.
From embodiment accompanying drawing 2, can find that switching transistor 213 separates FD4 and two floating active areas of FD, the potential change of the floating active area FD of transistor 210 direct detection second is followed in source, and the parasitic capacitance of the second floating active area FD is expressed as:
CFD＝Cm1+Caa+C1+C2+C3+C4
Therefore, the CFD expression formula in this implementation column than the CFD4 of traditional 4T4S structure of setting forth in background technology few 3C1+3Caa, and can be lower than the Cm4 in traditional 4T4S structure according to design experiences Cm1; In CFD expression formula from the present embodiment, can draw: the value of FD parasitic capacitance CFD does not change with sharing the variation of pixel quantity, it is constant that CFD can keep not sharing the minimum value of 4T dot structure always.The size of CFD value has determined the opto-electronic conversion gain C.G. of pixel, and expression formula is:
C.G.＝q/CFD
Q in expression formula is an electron charge 6.02E-19 coulomb.The luminous sensitivity of pixel is proportional to opto-electronic conversion gain C.G., therefore the pixel of the utility model pixel sharing structure, in keeping expanding photodiode area advantage, also keeping the opto-electronic conversion of the pixel constant advantage that gains, and opto-electronic conversion yield value is identical with the opto-electronic conversion yield value of unshared structure 4T dot structure.So the method for shared dot structure of the present utility model has solved the shortcoming that traditional shared pixel photoelectricity conversion gain reduces, improve the luminous sensitivity of shared pixel.
The operation principle of specific embodiment is:
The method of work that realizes the utility model pixel has two kinds, potential well schematic diagram when pixel is as shown in Figure 3 and Figure 4 operated in photoelectricity electric charge transfer step.
Shown in Fig. 3,301～304 characterize respectively the potential well of four photodiodes in shared pixel, 305～308 characterize respectively four charge pass transistor in shared pixel, 309 is reset transistor, 313 is switching transistor, 314 characterize the potential well of the first floating active area FD4, and 315 characterize the potential well of the second floating active area FD, and 316 characterize supply voltage potential well; TXn is 305～308 gate terminal, and wherein n is 1,2,3 and 4; TX and RX are respectively 313 and 309 gate terminal; CFD represents the parasitic capacitance of the second floating active area of pixel.Potential well state shown in Fig. 3 is that pixel is operated in the operating process that photoelectricity electric charge shifts, when wherein the dotted line below 305～308 and 313 represents that its gate terminal is GND, i.e. and the potential barrier schematic diagram of transistor in the time of closed condition.
The work potential VFD4 of the first floating active area FD4 shown in Fig. 3 is 0V～0.3V higher than the scope that exhausts electromotive force Vpin completely of photodiode, the process using traditional C IS standard logic process of the first floating active area.
The second realize the utility model dot structure electric charge shift operation potential well schematic diagram as shown in Figure 4,401～404 characterize respectively the potential well of four photodiodes in shared pixel, 405～408 characterize respectively four charge pass transistor in shared pixel, 409 is reset transistor, 413 is switching transistor, 414 characterize the potential well of the first floating active area FD4, and 415 characterize the potential well of the second floating active area FD, and 416 characterize supply voltage potential well; TXn is 405～408 gate terminal, and wherein n is 1,2,3 and 4; TX and RX are respectively 413 and 409 gate terminal; CFD represents the parasitic capacitance of the second floating active area of pixel.Potential well state shown in Fig. 4 is that pixel is operated in the operating process that photoelectricity electric charge shifts, when wherein the dotted line below 405～408 and 413 represents that its gate terminal is GND, i.e. and the potential barrier schematic diagram of transistor in the time of closed condition.
The work potential Vpin4 of the first floating active area FD4 shown in Fig. 4 is 0V～0.3V higher than the scope that exhausts electromotive force Vpin completely of photodiode, wherein, the technology type that FD4 active area adopts is identical with the technology type of photodiode, and when pixel is operated in electric charge transfering state, FD4 is completely depleted, and it exhausts electromotive force is completely Vpin4.
The above; it is only preferably embodiment of the utility model; but protection range of the present utility model is not limited to this; any be familiar with those skilled in the art the utility model disclose technical scope in; the variation that can expect easily or replacement, within all should being encompassed in protection range of the present utility model.Therefore, protection range of the present utility model should be as the criterion with the protection range of claims.
Claims (8)
1. the shared dot structure of high sensitivity cmos image sensor, comprise charge pass transistor and the first floating active area of multiple photodiodes and equal number, also comprise that a reset transistor, source follow transistor, row selecting transistor and the second floating active area, it is characterized in that, between described the first floating active area and the second floating active area, separate by a switching transistor.
2. the shared dot structure of high sensitivity cmos image sensor according to claim 1, is characterized in that, the drain electrode of described switching transistor is connected with described the second floating active area, source electrode is connected with described the first floating active area.
3. the shared dot structure of high sensitivity cmos image sensor according to claim 2, it is characterized in that, described source is followed transistorized grid and is connected with described the second floating active area, and described source is followed transistor and changed for the electric potential signal of surveying described the second floating active area.
4. the shared dot structure of high sensitivity cmos image sensor according to claim 3, is characterized in that, in the shared dot structure of this high sensitivity cmos image sensor, the pixel quantity that shared pixel packets contains is more than or equal to two.
5. the shared dot structure of high sensitivity cmos image sensor according to claim 4, is characterized in that, the variation of the quantity that the parasitic total capacitance of described the second floating active area does not contain with shared pixel packets changes.
6. according to the shared dot structure of high sensitivity cmos image sensor described in claim 1 to 5 any one, it is characterized in that, in the time carrying out the transfer operation of photoelectricity electric charge, the electromotive force of described the first floating active area exhausts electromotive force 0V～0.3V completely higher than described photodiode.
7. the shared dot structure of high sensitivity cmos image sensor according to claim 6, is characterized in that, described the first floating active area comprises that source transistor leaks the active area of active area or photodiode technique.
8. the shared dot structure of high sensitivity cmos image sensor according to claim 6, is characterized in that, described photodiode comprises Pin type photodiode, part Pin type photodiode or polysilicon gate type photodiode.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420222723.1U CN203813866U (en) | 2014-04-30 | 2014-04-30 | High-sensitivity CMOS image sensor shared-type pixel structure |
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| CN201420222723.1U CN203813866U (en) | 2014-04-30 | 2014-04-30 | High-sensitivity CMOS image sensor shared-type pixel structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103929600A (en) * | 2014-04-30 | 2014-07-16 | 北京思比科微电子技术股份有限公司 | Sharing type pixel structure of high-sensitivity CMOS image sensor |
| CN110462831A (en) * | 2017-04-01 | 2019-11-15 | 华为技术有限公司 | Control the cmos image sensor of the address XY exposure |
-
2014
- 2014-04-30 CN CN201420222723.1U patent/CN203813866U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103929600A (en) * | 2014-04-30 | 2014-07-16 | 北京思比科微电子技术股份有限公司 | Sharing type pixel structure of high-sensitivity CMOS image sensor |
| CN103929600B (en) * | 2014-04-30 | 2017-03-15 | 北京思比科微电子技术股份有限公司 | The shared dot structure of high sensitivity cmos image sensor |
| CN110462831A (en) * | 2017-04-01 | 2019-11-15 | 华为技术有限公司 | Control the cmos image sensor of the address XY exposure |
| CN110462831B (en) * | 2017-04-01 | 2021-11-26 | 华为技术有限公司 | CMOS image sensor for controlling XY address exposure |
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Granted publication date: 20140903 Effective date of abandoning: 20171114 |
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| AV01 | Patent right actively abandoned |