CN203788267U - Output stage circuit of level shift circuit - Google Patents
Output stage circuit of level shift circuit Download PDFInfo
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- CN203788267U CN203788267U CN201420124922.9U CN201420124922U CN203788267U CN 203788267 U CN203788267 U CN 203788267U CN 201420124922 U CN201420124922 U CN 201420124922U CN 203788267 U CN203788267 U CN 203788267U
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- circuit
- inverter
- output
- level shift
- multistage
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- 230000000087 stabilizing effect Effects 0.000 claims abstract description 26
- 230000005669 field effect Effects 0.000 claims description 26
- 229910044991 metal oxide Inorganic materials 0.000 claims description 26
- 150000004706 metal oxides Chemical class 0.000 claims description 26
- 238000010586 diagram Methods 0.000 description 6
- 230000010355 oscillation Effects 0.000 description 6
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
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Abstract
The utility model provides an output stage circuit of a level shift circuit. The output stage circuit comprises a stabilizing circuit and a multistage inverter circuit, wherein the stabilizing circuit comprises a control switch and a depletion transistor; the depletion transistor is coupled to the control switch and a first node at the output end of the level shift circuit; the multistage inverter circuit comprises a first inverter and a second inverter; the first inverter and the second inverter are provided with a second node therebetween; and the control switch is coupled to the second node. The output stage circuit provided by the utility model has a current supplying capacity and can stabilize output of the level shift circuit.
Description
Technical field
The utility model relates to a kind of technology of stable output level, and particularly relevant for a kind of output-stage circuit of level shift circuit.
Background technology
Fig. 1 is the existing schematic diagram that is applied to switched power supply.Fig. 2 is the oscillogram of the switched power supply of Fig. 1.Please refer to Fig. 1 and Fig. 2.
Existing switched power supply 100 comprises controller 10, level shift circuit 20 and multistage inverter circuit 30.Switched power supply 100 needs level shift circuit 20 with conversion electric power source, and for promoting upper bridge switch (high side switch).When switched power supply 100 is in time T 0, system enable signal SE is converted to logic low by logic high and is used for powered-down, so level shift circuit 20 produces short time pulse via the output (node UG) of multistage inverter circuit 30, to close, closes bridge switch and lower bridge switch (low side switch).During power-off after time T 0, the voltage on phase node PHASE produces the situation of phase oscillation (phase ringing) in time T 1.Due at time T 1 powered-down, phase oscillation reason may be to make phase oscillation too fast because of inductive current IL, cause the voltage of level shift circuit 20 outputs (node preUG) not catch up with the speed of phase oscillation, thereby cause output (node UG) misoperation of multistage inverter circuit 30 and again open upper bridge switch.Therefore, the time T 1 during power-off, output voltage (not shown) will improve suddenly.Worst case will damage the application circuit of the rear end of multistage inverter circuit 30.
Therefore on the other hand, during the power-off of prior art after time T 0, cannot confirm how long also to have afterwards the situation of phase oscillation, except the other times point of time T 1 or above-mentioned misoperation situation likely occurs.
Utility model content
In view of this, the utility model proposes a kind of output-stage circuit of level shift circuit, use the problem that prior art is addressed that solves.
The utility model provides a kind of output-stage circuit of level shift circuit, and it comprises stabilizing circuit and multistage inverter circuit.Stabilizing circuit comprises control switch and vague and general formula transistor.Vague and general formula transistor couples the first node on the output of control switch and level shift circuit.Multistage inverter circuit comprises the first inverter and the second inverter.Between the first inverter and the second inverter, there is Section Point.Control switch couples Section Point.
In an embodiment of the present utility model, on first node, there is the first control signal, on Section Point, there is one second control signal, the logic level of the logic level of the first control signal and the second control signal is anti-phase.
In an embodiment of the present utility model, on Section Point, there is the second control signal, on the output of the second inverter, there is the 3rd control signal, the logic level of the logic level of the second control signal and the 3rd control signal is anti-phase.
In an embodiment of the present utility model, control switch is N-type metal-oxide half field effect transistor.
In an embodiment of the present utility model, multistage inverter circuit also comprises the 3rd inverter, and the input of the 3rd inverter couples the output of the second inverter, and control switch is P type metal-oxide half field effect transistor.
In an embodiment of the present utility model, every one-level inverter of multistage inverter circuit comprises N-type metal-oxide half field effect transistor and P type metal-oxide half field effect transistor.
The utility model separately provides a kind of output-stage circuit of level shift circuit, and it comprises multistage inverter circuit and stabilizing circuit.Multistage inverter circuit comprises the switch element of a plurality of the first conducting types and the switch element of the second conducting type.Multistage inverter circuit couples outside switch element.Stabilizing circuit couples the output of multistage inverter circuit and level shift circuit.Stabilizing circuit comprises vague and general formula switch element.
In an embodiment of the present utility model, vague and general type switch element is vague and general formula N-type transistor.
In an embodiment of the present utility model, every one-level inverter of multistage inverter circuit comprises N-type metal-oxide half field effect transistor and P type metal-oxide half field effect transistor.
Based on above-mentioned, in the utility model when the circuit system in shutdown is while having applied this output-stage circuit, because output-stage circuit has electric current providing capability, output that can stable level off-centre circuit.On the other hand, compared to prior art, output-stage circuit of the present utility model provides a kind of and has had electric current providing capability and for better simply protecting circuit designed.
For above-mentioned feature and advantage of the present utility model can be become apparent, special embodiment below, and coordinate accompanying drawing to be described in detail below.
Accompanying drawing explanation
Accompanying drawing is below a part for specification of the present utility model, and it shows example embodiment of the present utility model, and accompanying drawing is to be used for illustrating principle of the present utility model together with the description with specification.
Fig. 1 is the existing schematic diagram that is applied to switched power supply;
Fig. 2 is the oscillogram of the switched power supply of Fig. 1;
Fig. 3 is the circuit diagram of the circuit system of the utility model one embodiment;
Fig. 4 is the circuit diagram of the circuit system of another embodiment of the utility model;
Fig. 5 is the oscillogram of the circuit system of the utility model embodiment.
Description of reference numerals:
10: controller;
20: level shift circuit;
30: multistage inverter circuit;
100: switched power supply;
300: circuit system;
310: controller;
320: level shift circuit;
330: stabilizing circuit;
340: multistage inverter circuit;
342: the first inverters;
344: the second inverters;
350: output-stage circuit;
400: circuit system;
410: controller;
420: level shift circuit;
430: stabilizing circuit;
440: multistage inverter circuit;
442: the first inverters;
444: the second inverters;
446: the three inverters;
450: output-stage circuit;
G1, G2: operating voltage;
IL: inductive current;
MN1, MN2, MN3:N type metal-oxide half field effect transistor;
MN4: vague and general formula transistor;
MN5: control switch;
MP1, MP2, MP3:P type metal-oxide half field effect transistor;
MP4: control switch;
PHASE: phase node;
PreUG, preUGB: node;
SE: system enable signal;
T0, T1: time;
UG: node;
VP1, VP2: operating voltage.
Embodiment
Now with detailed reference to embodiment of the present utility model, and the example of the described embodiment of explanation in the accompanying drawings.Element/the member of the identical or like numerals will of using in drawings and the embodiments in addition, is for representing identical or similar portions.
In following all embodiment, when element is regarded as " connection " or " coupling " to another element, it can be direct connection or is coupled to another element, maybe may have intervenient element.Term " circuit " can be expressed as at least one element or a plurality of element, or is coupled on one's own initiative and/or passively element together so that proper function to be provided.Term " signal " can be expressed as at least one electric current, voltage, load, temperature, data or other signals.In addition, should be understood that and run through the signal that this specification and accompanying drawing refer to, its physical characteristic can be voltage or electric current.
Fig. 3 is the circuit diagram of the circuit system of the utility model one embodiment.Refer to Fig. 3.Circuit system 300 comprises controller 310, level shift circuit 320 and output-stage circuit 350.
Output-stage circuit 350 couples the output of level shift circuit 320.Output-stage circuit 350 comprises stabilizing circuit 330 and multistage inverter circuit 340.In this embodiment, multistage inverter circuit 340 has secondary inverter, comprises the first inverter 342 and the second inverter 344.Multistage inverter circuit 340 comprises a plurality of P type metal-oxide half field effect transistor (switch element of the first conducting type) MP1, MP2 and a plurality of N-type metal-oxide half field effect transistor (switch element of the second conducting type) MN1, MN2.Multistage inverter circuit 340 couples the control end (not shown) of switch element of output-stage circuit 350 outsides in node UG.Stabilizing circuit 330 couples the output (node preUG) of multistage inverter circuit 340 and level shift circuit 320.
Stabilizing circuit 330 comprises control switch MN5 and vague and general formula transistor (vague and general formula switch element) MN4.Control switch MN5 can be metal-oxide half field effect transistor.The grid of control switch MN5 couples the output (node preUGB) of the first inverter 342 in multistage inverter circuit 340.Vague and general formula transistor MN4 is connected in serial connection mode with control switch MN5.The grid of vague and general formula transistor MN4 connects its source electrode.
The drain electrode of vague and general formula transistor MN4 couples the output of level shift circuit 320 and the input of the first inverter 342 in node preUG.The source electrode of vague and general formula transistor MN4 couples the drain electrode of control switch MN5.A plurality of N-type metal-oxide half field effect transistor MN1 in multistage inverter circuit 340, each source electrode of MN2 couple the source electrode of control switch MN5.
In one embodiment, controller 310 can be applied in operating voltage VP1 and operating voltage G1, and for example operating voltage VP1, G1 are respectively 5V, 0V.Level shift circuit 320 can be applied in operating voltage VP2 and operating voltage G1, and for example operating voltage VP2, G1 are respectively 12V, 0V.Output-stage circuit 350 can be applied in operating voltage VP2 and operating voltage G2, and for example operating voltage VP2, G2 are respectively 12V, 7V.The numerical value that note that operating voltage of the present utility model is not limited with above-mentioned disclosure.
It is worth mentioning that, control switch MN5 can be N-type metal-oxide half field effect transistor, and vague and general formula transistor MN4 can be vague and general formula N-type metal-oxide half field effect transistor.
Multistage inverter circuit 340 is secondary inverter.When the input of the first inverter 342 receives the logic low (the first control signal on node preUG is logic low) from the output of level shift circuit 320, the first inverter 342 output logic high level (the second control signal on node preUGB is logic high) are to the input of the second inverter 344, and the second inverter 344 output logic low levels (the 3rd control signal on node UG is logic low) are to the control end of node UG(switch element) to close outside switch element.The logic level of the logic level of the first control signal and the second control signal is anti-phase, and the logic level of the logic level of the second control signal and the 3rd control signal is anti-phase.On the other hand, the output of the first inverter 342 is the grid to control switch MN5 by output logic high level, is also that stabilizing circuit 330 is by the serial connection path of conducting control switch MN5 and vague and general formula transistor MN4.Therefore, stabilizing circuit 330 pins the output of level shift circuit 320 at logic low.Therefore, stabilizing circuit 330 has electric current providing capability, and the output of energy stable level off-centre circuit 320.
Fig. 4 is the circuit diagram of the circuit system of another embodiment of the utility model.Refer to Fig. 4.Circuit system 400 comprises controller 410, level shift circuit 420 and output-stage circuit 450.
Output-stage circuit 450 comprises stabilizing circuit 430 and multistage inverter circuit 440.Multistage inverter circuit 440 has three grades of inverters, comprises the first inverter 442, the second inverter 444 and the 3rd inverter 446.Multistage inverter circuit 440 comprises a plurality of P type metal-oxide half field effect transistor MP1, MP2, MP3 and a plurality of N-type metal-oxide half field effect transistor MN1, MN2, MN3.Multistage inverter circuit 440 couples the control end (not shown) of switch element of output-stage circuit 450 outsides in node UG.Stabilizing circuit 430 couples the output (node preUGB) of multistage inverter circuit 440 and level shift circuit 320.
Stabilizing circuit 430 comprises control switch MP4 and vague and general formula transistor MN4.Control switch MP4 can be metal-oxide half field effect transistor.The grid of control switch MP4 couples the output (node preUG) of the first inverter 442 in multistage inverter circuit 440.Vague and general formula transistor MN4 is connected in serial connection mode with control switch MP4.The grid of vague and general formula transistor MN4 connects its source electrode.
The source electrode of vague and general formula transistor MN4 couples the output of level shift circuit 420 and the input of the first inverter 442 in node preUGB.The drain electrode of vague and general formula transistor MN4 couples the drain electrode of control switch MP4.A plurality of P type metal-oxide half field effect transistor MP1 in multistage inverter circuit 440, each source electrode of MP2, MP3 couple the source electrode of control switch MP4.
In one embodiment, controller 410 can be applied in operating voltage VP1 and operating voltage G1, and for example operating voltage VP1, G1 are respectively 5V, 0V.Level shift circuit 420 can be applied in operating voltage VP2 and operating voltage G1, and for example operating voltage VP2, G1 are respectively 12V, 0V.Output-stage circuit 350 can be applied in operating voltage VP2 and operating voltage G2, and for example operating voltage VP2, G2 are respectively 12V, 7V.The numerical value that note that operating voltage of the present utility model is not limited with above-mentioned disclosure.
It is worth mentioning that, control switch MP4 can be P type metal-oxide half field effect transistor, and vague and general formula transistor MN4 can be vague and general formula N-type metal-oxide half field effect transistor.
Multistage inverter circuit 440 is three grades of inverters.When the input of the first inverter 442 receives the logic high from the output of level shift circuit 420, the 3rd inverter 446 output logic low levels are used for coupling the control end of outside switch element to node UG(node UG), to close the switch element (not shown) of output-stage circuit 450 outsides.On the other hand, the grid of the output of the first inverter 442 (node preUG) by output logic low level to control switch MP4, is also that stabilizing circuit 430 is by the serial connection path of conducting control switch MP4 and vague and general formula transistor MN4.Therefore, stabilizing circuit 430 pins the output of level shift circuit 420 (node preUGB) at logic high.Therefore stabilizing circuit 430 has electric current providing capability, and the output of energy stable level off-centre circuit 420.
Fig. 5 is the oscillogram of the circuit system of the utility model embodiment.Refer to Fig. 3 to Fig. 5.
Circuit system 300 or 400 can be power supply unit, but not as limit.In time T 0, system enable signal SE transfers logic low to powered-down by logic high, and level shift circuit 320 is closed bridge switch and lower bridge switch by generation one short time pulse to close via the output (node UG) of multistage inverter circuit 440 via multistage inverter circuit 340 or level shift circuit 420.During power-off after time T 0, if the voltage on operating voltage G2 produces phase oscillation in time T 1, because the output signal of level shift circuit 320 or 420 is pinned by stabilizing circuit 330 or 430, therefore can not affect the magnitude of voltage of node UG.Therefore, the application circuit of multistage inverter circuit 340 or 440 rear end is subject to the protection of output-stage circuit 350 or 450 and can misoperation.
Based on above-mentioned, in the utility model when the circuit system in shutdown is while having applied this output-stage circuit, because stabilizing circuit has electric current providing capability, output that can stable level off-centre circuit.On the other hand, compared to prior art, output-stage circuit of the present utility model provides a kind of and has had electric current providing capability and for better simply protecting circuit designed.
Finally it should be noted that: each embodiment, only in order to the technical solution of the utility model to be described, is not intended to limit above; Although the utility model is had been described in detail with reference to aforementioned each embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or some or all of technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the scope of each embodiment technical scheme of the utility model.
Claims (9)
1. an output-stage circuit for level shift circuit, is characterized in that, comprising:
One stabilizing circuit, comprises a control switch and a vague and general formula transistor, and described vague and general formula transistor couples the first node on the output of described control switch and described level shift circuit; And
One multistage inverter circuit, comprises one first inverter and one second inverter, between described the first inverter and described the second inverter, has a Section Point,
Wherein said control switch couples described Section Point.
2. output-stage circuit according to claim 1, it is characterized in that, on described first node, have one first control signal, have one second control signal on described Section Point, the logic level of the logic level of described the first control signal and described the second control signal is anti-phase.
3. output-stage circuit according to claim 1, it is characterized in that, on described Section Point, there is one second control signal, on the output of described the second inverter, have one the 3rd control signal, the logic level of the logic level of described the second control signal and described the 3rd control signal is anti-phase.
4. output-stage circuit according to claim 1, is characterized in that, described control switch is a N-type metal-oxide half field effect transistor.
5. output-stage circuit according to claim 1, it is characterized in that, described multistage inverter circuit also comprises one the 3rd inverter, and the input of described the 3rd inverter couples the output of described the second inverter, and described control switch is a P type metal-oxide half field effect transistor.
6. output-stage circuit according to claim 1, is characterized in that, every one-level inverter of described multistage inverter circuit comprises a N-type metal-oxide half field effect transistor and a P type metal-oxide half field effect transistor.
7. an output-stage circuit for level shift circuit, is characterized in that, described level shift circuit comprises:
One multistage inverter circuit, comprises the switch element of a plurality of the first conducting types and the switch element of a plurality of the second conducting types, and described multistage inverter circuit couples outside switch element; And
One stabilizing circuit, couples the output of described multistage inverter circuit and described level shift circuit, and described stabilizing circuit comprises a vague and general formula switch element.
8. output-stage circuit according to claim 7, is characterized in that, described vague and general type switch element is vague and general formula N-type transistor.
9. output-stage circuit according to claim 7, is characterized in that, every one-level inverter of described multistage inverter circuit comprises a N-type metal-oxide half field effect transistor and a P type metal-oxide half field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420124922.9U CN203788267U (en) | 2014-03-19 | 2014-03-19 | Output stage circuit of level shift circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420124922.9U CN203788267U (en) | 2014-03-19 | 2014-03-19 | Output stage circuit of level shift circuit |
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| Publication Number | Publication Date |
|---|---|
| CN203788267U true CN203788267U (en) | 2014-08-20 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420124922.9U Expired - Lifetime CN203788267U (en) | 2014-03-19 | 2014-03-19 | Output stage circuit of level shift circuit |
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| Country | Link |
|---|---|
| CN (1) | CN203788267U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110570885A (en) * | 2018-06-06 | 2019-12-13 | 美光科技公司 | Method and apparatus for driving circuit of voltage-less level shifter |
-
2014
- 2014-03-19 CN CN201420124922.9U patent/CN203788267U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110570885A (en) * | 2018-06-06 | 2019-12-13 | 美光科技公司 | Method and apparatus for driving circuit of voltage-less level shifter |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140820 |