CN203775187U - SCA multi-channel high-speed acquisition system - Google Patents
SCA multi-channel high-speed acquisition system Download PDFInfo
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- CN203775187U CN203775187U CN201420028447.5U CN201420028447U CN203775187U CN 203775187 U CN203775187 U CN 203775187U CN 201420028447 U CN201420028447 U CN 201420028447U CN 203775187 U CN203775187 U CN 203775187U
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Abstract
The utility model discloses an SCA multi-channel high-speed acquisition system, which is composed of a waveform acquisition and time measurement module assembly and a comprehensive processor module, wherein a high-speed switch capacitor array in an SCA chip is used for storing an analog signal and reading the analog signal through a slow-speed clock, then the analog signal is subjected to digital quantification through a high-accuracy low-speed AD to be stored into a buffer unit, and online real-time calibration can be achieved while multi-channel waveform acquisition and time measurement are completed. The calibration process when the SCA multi-channel high-speed acquisition system is used for time frequency synchronization calibration is simple, the calibration result is good in adaptability, the system calibration error is small, the measurement accuracy is superior to 80ps, and the SCA multi-channel high-speed acquisition system is particularly suitable for the technical field of whole waveform analysis.
Description
Technical field:
This patent relates to a kind of multi-channel high-speed acquisition system, is specifically related to a kind of SCA(Switch Capacitor Arrays, switched capacitor array) multi-channel high-speed acquisition system.
Background technology:
In Full wave shape analysis technical field, compared with scanning system with single channel in the past, multichannel array active probe system can form highdensity three-dimensional point cloud fast, first its data acquisition efficiency improves greatly, secondly can meet the specific demand of high speed real time imagery, imaging resolution also can correspondingly improve simultaneously.No matter survey and still comprise that in the application of the other field such as medical imaging and high-energy physics detection, this all means the lifting of overall performance and economic benefit for laser active remote sensing.Because though corresponding integrated array detector APD, PMT array etc. have conducted a research for many years abroad but device is still immature so far, and domestic this respect obvious progress not especially.Simultaneously, because integrated array detector is all to survey based on energy integral or based on the flight time, obtain echo information amount limited, can not carry out Full wave shape detection and analysis, so the multi-channel detection mode based on Multielement integration is main development trend.For improving image resolution ratio, data acquisition efficiency, improving the considerations such as system real time, according to different application, it has the demand of the even hundreds of passages of tens of passages to port number, and multichannel Full wave shape collection and analytical system become the decisive factor of its future development.
And in multichannel measuring system, consistency problem is one of difficult problem that must solve.Traditional multichannel calibration is divided into amplitude calibration, time calibration and synchronism calibration, traditional method is that scaling experiment method solves, it is the calibrating signal of each passage input same magnitude, same period and identical time delay relation in multichannel, obtain the calibration value of determining each passage after multi-channel measurement data through statistical analysis, needing high-precision calibration system to coordinate.But also there is following problem:
(1) calibration result is poor for applicability, after completion system is demarcated under certain condition, if signal characteristic changes, temperature change and other conditions of work change, demarcates effect and all can variation even lose efficacy.
(2) calibration process complexity, need to carry out complicated full condition of work (in different temperatures, power supply, signal characteristic situation) and demarcate for addressing the above problem, and finally solves by the software interpolation correction of tabling look-up.All higher from design realization and implementation procedure angle complexity.Measuring instrument could use after need to starting shooting and calibrating, and also needs regular demarcation.
(3) large based on the table look-up system calibrating error of interpolation of software, there is system calibrating error in calibration process first, and secondly software matching and actual operating conditions also exist certain error.
The poor source of multi-channel system is mainly divided into: 1. measuring element difference (amplitude-frequency difference); 2. the difference of different measuring passage (amplitude-frequency difference); 3. multi-clock phase error; 4. PCB routing delay difference.Former three error term is main relevant with device difference with system, can change with condition of work difference, cannot demarcate solution by single, and Section 4 error is basic uncorrelated with condition of work can demarcate elimination by single.
Based on above problem, this patent has proposed a kind of multichannel Time and Frequency Synchronization calibration system based on SCA array, this system only needs single system to demarcate and eliminates Section 4 error, other error terms complete operation conditions change insensitive by online real time calibration, also just mean without other calibration process.Meanwhile, adopt full Synchronization Design, further reduce systematic error.
Summary of the invention:
The object of this patent is to propose a kind of SCA multi-channel high-speed acquisition system, in Solving Multichannel measuring system, and the signal inconsistence problems of each passage input range, cycle and the relation of delay.
The SCA multi-channel high-speed acquisition system structure of this patent as shown in Figure 1, comprising: modular assembly 1 and comprehensive treatment device module 2 when waveform acquisition and survey, wherein:
Described waveform acquisition when surveying modular assembly 1 by the identical waveform acquisition of 4 structures and while surveying module form, be respectively 1～4 passage waveform acquisition and module 1-1,5～8 passage waveform acquisitions and module 1-2,9～12 passage waveform acquisitions and module 1-3 and 13～16 passage waveform acquisitions and module 1-4 while surveying while surveying while surveying while surveying; When described waveform acquisition and survey, module as shown in Figure 2, comprises relay attenuation network 101, high speed amplifier 102, SCA chip 103, AD device 104, gathers chip 106 while controlling FPGA105 and special survey; Wherein:
Described relay attenuation network 101 is by relay and capacitance-resistance attenuator circuit combining structure;
Described high speed amplifier 102 is broadband full differential amplifier and comparator combination structure;
Described SCA chip 103 is SCA chips of 8 passages, figure place 12bit, sample rate 0.5～5Gsps;
Described AD device 104 is analog to digital converters of 8 passages, figure place 14bit, sample rate 50Msps;
Described collection control FPGA105 controls SCA chip 103 mode of operations, and selecting model is XC3S1000;
When described special survey, chip 106 is 8 passages, and Measurement Resolution 81ps, without measuring range restriction, 200MHz peak value, the time measurement chip of 40MHz test constantly frequency;
Described comprehensive treatment device module comprises primary processor fpga chip 201 and DSP202, wherein:
Described primary processor fpga chip 201 is ambipolar conduction, the integrated fpga chip of semiconductor;
Described DSP202 is high-performance, fixed-point dsp, and maximum operating frequency is 1.2GHz;
The operation principle of system is as follows:
When waveform acquisition and survey, the relay attenuation network 101 of module 1 receives the echo-signal of returning from target and realizes automatic switch adjusting, the digital echo signal producing after relatively through the amplifier of high speed amplifier 102 and threshold value is input to SCA chip 103 and carries out waveform acquisition, realize the calibration of multichannel Time and Frequency Synchronization by arranging of SCA chip 103Domino clock and calibration clock signal, the digitlization echo input low speed AD104 having calibrated is carried out to waveform quantization, digitized wave graphic data after quantizing is input in FPGA201, send Wave data to DSP202 by LVDS bus, completing initial sampled point to the calculating of the waveform centroid position time interval and other waveform parameters by this DSP202 extracts.Main ripple is as initial signal, digitlization echo, and, the 8 road signals such as pulse and lock-out pulse are inputted as stop signal when in the school, and the special time measurement chip 106 of module completes the time interval measurement between above-mentioned 8 road signals and main ripple when surveying.Echo-signal and sampling clock synchronizing signal are together input to stretch circuit to be completed echo and crosses the time interval measurement of threshold triggers to the first sampled point of the echo waveform moment.Thereby this multi-channel high-speed acquisition system has realized high-precision waveform acquisition and time measurement.
Realize the concrete steps of Time and Frequency Synchronization calibration steps:
1. with chip different measuring passage, the inner each channel switch capacitor array of SCA chip 103 adopts homology sampling clock, ensures clock synchronous;
2. the Domino clock of different SCA chips 103 adopts homology clock fan-out, and each road clock adopts isometric wiring, ensures that clock phase is consistent.
3. in different SCA chips 103, introduce calibration clock signal, this clock and Domino clock synchronous, adopt the analog input signal of clock fan-out mode as each SCA chip 103 equally, ensures the consistency of each road calibration clock phase and amplitude.Because calibration clock is input to 4 SCA chips simultaneously, can carry out synchronous calibration to the echo data of 16 passages as time synchronized benchmark.
4. start timing taking first pulse signal as mark, in the time that timing is full, send Domino stop signal to all SCA chips 103, the electric charge before sampling in a switching capacity is equivalent in latch mode.Calibration clock after shaping is also latching in SCA sampling unit.
5. during by special survey, chip 106 is measured main ripple and first pulse interval and calibration pulse width and is obtained the first positioning time of calibrating clock edge after first echo impulse, the pulse train of each passage is all located taking time at this time edge as benchmark, thereby realizes the absolute waveform location of each passage echo waveform.
Multichannel Time and Frequency Synchronization calibration steps schematic diagram as shown in Figure 3, demonstration be 4 Channel Synchronous calibrations schematic diagrames.
This patent has following beneficial effect:
By the Time and Frequency Synchronization calibration steps based on SCA multi-channel high-speed acquisition system, overcome in multichannel measuring system, each passage input range, the signal inconsistence problems of cycle and the relation of delay, being better than tradition " first measures, demarcate again " calibration steps, can realize online real time calibration, calibration process is simple, calibration result applicability is good, systematic error is little, time difference method is better than 80ps, be highly suitable for laser active remote sensing, high-energy physics, imaging of medical and general waveform collection and analysis etc. require high-resolution, the field that high speed imaging and multi-dimensional complicated target property are analyzed.
Brief description of the drawings:
Fig. 1 is based on SCA array multi-channel high-speed acquisition system structure chart.
In figure: 1. modular assembly when waveform acquisition is with survey;
Module when 1-1.1～4 passage waveform acquisition and survey;
Module when 1-2.5～8 passage waveform acquisition and survey;
Module when 1-3.9～12 passage waveform acquisition and survey;
Module when 1-4.13～16 passage waveform acquisition and survey;
2. comprehensive treatment device module;
201. primary processor fpga chips; 202.DSP
Modular structure figure when Fig. 2 is 4 passage waveform acquisitions and survey.
In figure:
101. relay attenuation networks; 102. high speed amplifiers; 103.SCA chip;
104.AD device; 105. gather control FPGA;
System when 106. multichannels are surveyed;
Fig. 3 is 4 passage Full wave shape Domain Synchronous calibration steps schematic diagrams.
In figure: T
domino=1000ns, the continuous acquisition scope of windowing;
T
stop=900ns, echo stops the sampling time after triggering;
T
presample=100ns, echo triggers the front pre-sampling time of sampling;
T
r-maintdc, the main ripple of reference clock rising edge position during with respect to school;
T
r-bptdc, reference clock rising edge echo position during with respect to school;
T
r-clkct, taking rising edge as the main ripple echo sounding clock cycle of benchmark;
T
f-maintdc, the main ripple of reference clock trailing edge position during with respect to school;
T
f-bptdc, reference clock rising edge echo position during with respect to school;
T
f-clkct, taking trailing edge as the main ripple echo sounding clock cycle of benchmark.
Embodiment:
Can be used for realizing the multi-channel high-speed acquisition system of Time and Frequency Synchronization calibration steps as shown in Figure 1, for realizing 16 channel wave conformal analysis, in this instance system, adopt 4 SCA chips 103, every SCA chip controls 4 railway digital echoes, realize integrated Integral design by multi-chip, many boards mode.In conjunction with Fig. 1, Fig. 3 further set forth application this patent can realize Time and Frequency Synchronization calibration based on SCA multi-channel high-speed acquisition system execution mode:
1. echo belongs to asynchronous signal with calibration clock, may there is the calibration clock edge situation corresponding with first pulse front edge, for avoiding occurring location fuzzy problem, in this system, adopt calibration pulse bilateral along producing two kinds of calibration pulses, be respectively rising edge calibration pulse and trailing edge calibration pulse, two kinds of pulses measured simultaneously.
2.16 passage echo-signals obtain digital echo signal after being input to relay attenuation network 101, high speed amplifier 102, for the triggering synchronous that ensures that 16 passage Domino gather, the SCA that every 4 tunnels of digital echo signal are one group of input gathers and controls FPGA105, the 4 railway digital echo composite pulse signals that this FPGA105 produces gather and control the 3 railway digital echo composite pulses that FPGA105 exports and be together input to primary processor FPGA201 with other 3, form unified echo composite pulse after 4 SCA chips 103 of FEEDBACK CONTROL work.
3. for the different measuring passage of identical SCA chip, the inner 8 channel switch capacitor arrays of SCA chip 103 adopt homology Domino sampling clock, to ensure clock synchronous.
4. for different measuring SCA chip 103, the Domino clock of different SCA chips adopts 1:4 homology clock fan-out, and 4 road clocks adopt isometric wiring, strict guarantee clock phase consistency.Simultaneously, introduce calibration clock signal, this clock and Domino clock synchronous, the same analog input signal of 1:4 fan-out as 4 SCA chips 103 that adopt, to ensure the 4 tunnel calibration phase place of clock and the consistency of amplitude, thereby different SCA chips 103 can complete the calibration of amplitude and time according to calibration clock waveform data in real time under various conditions of work.
5. the digital echo signal producing after relay attenuation network 101 and high speed amplifier 102 and reference calibrations clock signal are together inputted and in SCA chip 103, are carried out waveform acquisition.Because calibration clock is input to 4 SCA chips simultaneously, can carry out synchronous calibration to the echo data of 16 passages as time synchronized benchmark.If SCA does not receive stop signal just always under continuous acquisition state, the inner every channel switch electric capacity of SCA continuous being recycled just as FIFO refreshed, echo-signal produces digital echo signal through threshold value after relatively, after twice 4:1 pulse is synthetic, form multi-path digital echo impulse composite signal, the precedence relationship of a reaction passage echo-signal.
6. start timing taking first pulse signal as mark, when the full 900ns of timing, send Domino stop signal to all SCA chips 103, the electric charge before sampling in a switching capacity is equivalent in latch mode, whole sampling chain length 1024, be equivalent to reserve the pre-sampling time of 124ns, this is helpful to the Latest Information before and after reservation clawback.Calibration rising edge clock after shaping is greater than 5ns and is also latching in SCA sampling unit.
7. produce calibration pulse by High speed sequencing logic, calibration pulse indicates the relativeness between the first pulse of relativeness and echo and calibration clock between main ripple signal and calibration clock simultaneously, and during by special survey, chip 106 is measured main ripple and first pulse interval and calibration pulse width and just can be known the first positioning time of calibrating clock edge after first echo impulse.In each SCA chip image data, all can in 124～124+Tcal interval, search out this clock edge, and the time of this clock edge has located, so the pulse train of 16 passages can be located as benchmark, realize thus the absolute waveform location of each passage echo waveform.
Claims (1)
1. a SCA multi-channel high-speed acquisition system, modular assembly (1) and comprehensive treatment device module (2) when comprising waveform acquisition and surveying; It is characterized in that:
Described waveform acquisition when surveying modular assembly (1) by the identical waveform acquisition of 4 structures and while surveying module form, be respectively 1～4 passage waveform acquisition and module (1-1), 5～8 passage waveform acquisitions and module (1-2), 9～12 passage waveform acquisitions and module (1-3) and 13～16 passage waveform acquisitions and module (1-4) while surveying while surveying while surveying while surveying; Described waveform acquisition and while surveying module comprise relay attenuation network (101), high speed amplifier (102), SCA chip (103), AD device (104), gather and control FPGA(105) and chip (106) when special survey; Wherein:
Described relay attenuation network (101) is relay and capacitance-resistance attenuator circuit combining structure;
Described high speed amplifier (102) is broadband full differential amplifier and comparator combination structure;
Described SCA chip (103) is the SCA chip of 8 passages, figure place 12bit, sample rate 0.5～5Gsps;
Described AD device (104) is the analog to digital converter of 8 passages, figure place 14bit, sample rate 50Msps;
Described collection control FPGA(105) SCA chip (103) mode of operation is controlled, selecting model is XC3S1000;
When described special survey, chip (106) is 8 passages, and Measurement Resolution 81ps, without measuring range restriction, 200MHz peak value, the time measurement chip of 40MHz test constantly frequency;
Described comprehensive treatment device module comprises primary processor fpga chip (201) and DSP(202); Wherein:
Described primary processor fpga chip (201) is ambipolar conduction, the integrated fpga chip of semiconductor;
Described DSP(202) be high-performance, fixed-point dsp, maximum operating frequency is 1.2GHz;
When system works, when waveform acquisition and survey, the relay attenuation network (101) of module receives the echo-signal of returning from target and realizes automatic switch adjusting, the digital echo signal producing after relatively through the amplifier of high speed amplifier (102) and threshold value is input to SCA chip (103) and carries out waveform acquisition, realize the calibration of multichannel Time and Frequency Synchronization by arranging of SCA chip (103) Domino clock and calibration clock signal, by the digitlization echo input low speed AD(104 having calibrated) carry out waveform quantization, digitized wave graphic data after quantizing is input to FPGA(201) in, send Wave data to DSP(202 by LVDS bus), by this DSP(202) complete initial sampled point to the calculating of the waveform centroid position time interval and the extraction of other waveform parameters, main ripple is as initial signal, digitlization echo, , the 8 road signals such as pulse and lock-out pulse are inputted as stop signal when in the school, during by survey, the special time measurement chip (106) of module completes the time interval measurement between above-mentioned 8 road signals and main ripple, echo-signal and sampling clock synchronizing signal are together input to stretch circuit to be completed echo and crosses the time interval measurement of threshold triggers to the first sampled point of the echo waveform moment, thereby this multi-channel high-speed acquisition system has realized high-precision waveform acquisition and time measurement.
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Cited By (7)
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| CN105403892A (en) * | 2015-12-23 | 2016-03-16 | 中国科学院长春光学精密机械与物理研究所 | Semiconductor laser distance measuring device based on switched capacitor array sampling |
| CN107239305A (en) * | 2017-05-22 | 2017-10-10 | 哈尔滨工程大学 | The system and method loaded for field programmable gate array chip file |
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| CN105403892A (en) * | 2015-12-23 | 2016-03-16 | 中国科学院长春光学精密机械与物理研究所 | Semiconductor laser distance measuring device based on switched capacitor array sampling |
| CN107239305A (en) * | 2017-05-22 | 2017-10-10 | 哈尔滨工程大学 | The system and method loaded for field programmable gate array chip file |
| CN111355484A (en) * | 2018-12-20 | 2020-06-30 | 深圳市中兴微电子技术有限公司 | Device and method for realizing data synchronization |
| US11502814B2 (en) | 2018-12-20 | 2022-11-15 | Zte Corporation | Device and method for realizing data synchronization |
| CN111355484B (en) * | 2018-12-20 | 2023-09-05 | 深圳市中兴微电子技术有限公司 | Device and method for realizing data synchronization |
| CN111694790A (en) * | 2020-06-15 | 2020-09-22 | 浪潮集团有限公司 | Feedback type cascade board card synchronous processing method based on FPGA |
| CN111694790B (en) * | 2020-06-15 | 2023-08-29 | 浪潮集团有限公司 | FPGA-based feedback type cascade board card synchronous processing method |
| CN113917966A (en) * | 2021-08-17 | 2022-01-11 | 中国科学院高能物理研究所 | Switched capacitor array chip direct current bias real-time correction method |
| CN113917966B (en) * | 2021-08-17 | 2022-07-22 | 中国科学院高能物理研究所 | Switched capacitor array chip direct current bias real-time correction method |
| CN114578743A (en) * | 2022-05-06 | 2022-06-03 | 四川赛狄信息技术股份公司 | Ship-borne multi-channel signal acquisition synchronous control system based on FPGA |
| CN114968871A (en) * | 2022-05-06 | 2022-08-30 | 松山湖材料实验室 | Signal synchronous acquisition method and device and electronic equipment |
| CN114968871B (en) * | 2022-05-06 | 2023-03-10 | 松山湖材料实验室 | Signal synchronous acquisition method and device and electronic equipment |
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