CN107942280A - A kind of method and system for being calibrated to the absolute delay time - Google Patents

A kind of method and system for being calibrated to the absolute delay time Download PDF

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Publication number
CN107942280A
CN107942280A CN201810005177.9A CN201810005177A CN107942280A CN 107942280 A CN107942280 A CN 107942280A CN 201810005177 A CN201810005177 A CN 201810005177A CN 107942280 A CN107942280 A CN 107942280A
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China
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sampled value
error
sine wave
msubsup
signal
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CN201810005177.9A
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Inventor
杨春燕
熊前柱
胡浩亮
雷民
周峰
李鹤
李登云
徐子立
聂琪
万鹏
黄俊昌
潘瑞
赵双双
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State Grid Corp of China SGCC
China Electric Power Research Institute Co Ltd CEPRI
Electric Power Research Institute of State Grid Jiangsu Electric Power Co Ltd
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State Grid Corp of China SGCC
China Electric Power Research Institute Co Ltd CEPRI
Electric Power Research Institute of State Grid Jiangsu Electric Power Co Ltd
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Application filed by State Grid Corp of China SGCC, China Electric Power Research Institute Co Ltd CEPRI, Electric Power Research Institute of State Grid Jiangsu Electric Power Co Ltd filed Critical State Grid Corp of China SGCC
Priority to CN201810005177.9A priority Critical patent/CN107942280A/en
Publication of CN107942280A publication Critical patent/CN107942280A/en
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R35/00Testing or calibrating of apparatus covered by the other groups of this subclass
    • G01R35/02Testing or calibrating of apparatus covered by the other groups of this subclass of auxiliary devices, e.g. of instrument transformers according to prescribed transformation ratio, phase angle, or wattage rating

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Unknown Time Intervals (AREA)

Abstract

The invention discloses a kind of method for being calibrated to the absolute delay time, including:Standard sine wave table is produced using data processing platform (DPP);Signal processing module handles the standard sine wave table, obtains normal voltage current signal and sends to Devices to test;When reaching default delay threshold, the standard sine wave table is handled using data processing platform (DPP), obtains sampled value SV messages, and the sampled value SV messages are sent to Devices to test;Devices to test carries out analog acquisition while the sampled value SV messages are received, and obtains the first sampled value of default collection point amount threshold;Fast Fourier transform FFT is carried out to first sampled value and corresponding second sampled value of the sampled value SV messages respectively, obtains the phase time difference of first sampled value and the second sampled value, i.e. absolute delay time;According to the absolute delay time and default delay threshold, the absolute delay time measurement error of the Devices to test is determined.

Description

A kind of method and system for being calibrated to the absolute delay time
Technical field
It is used for the present invention relates to checking electronic type transformers technical field, and more particularly, to one kind to definitely prolonging The method and system that the slow time is calibrated.
Background technology
Intelligent substation is one of product platform that energy conversion and control are realized in intelligent grid construction, is intelligent grid Important component.With the iterative method of China's intelligent grid building-up work, a large amount of New Generation of Intelligent substations or intelligence Change the operation operation of transformation substation.In these intelligent substations, the electronic mutual inductor as " power sensor " obtains Substantial amounts of application.Under current technological conditions, the accuracy detecting system of electronic mutual inductor and combining unit mainly uses Synchronos method, by standard channel and the data comparison of subject passage, obtains the angular difference and ratio of electronic mutual inductor and combining unit Difference, for absolute delay method due to that can not trace to the source, the confidence level of test result is not high.As the pilot of third generation intelligent substation is built If electronic mutual inductor is unworthy of combining unit, direct collector output, no synchronizing signal, communications protocol is also incompatible, causes existing Some detections and calibration method all fail.
The content of the invention
The present invention provides a kind of method and system for being calibrated to the absolute delay time, to solve existing inspection The problem of survey and calibration method are inaccurate.
To solve the above-mentioned problems, according to an aspect of the invention, there is provided it is a kind of be used for the absolute delay time into The method of row calibration, it is characterised in that the described method includes:
Standard sine wave table is produced using data processing platform (DPP), and the standard sine wave table is sent to signal processing mould Block;
Signal processing module handles the standard sine wave table, obtains normal voltage current signal, and by described in Normal voltage current signal is sent to Devices to test;
When reaching default delay threshold, the standard sine wave table is handled using data processing platform (DPP), is obtained Sampled value SV messages, and the sampled value SV messages are sent to Devices to test;
Devices to test carries out analog acquisition while the sampled value SV messages are received, and obtains default collection points Measure the first sampled value of threshold value;
Fast Fourier change is carried out to first sampled value and corresponding second sampled value of the sampled value SV messages respectively FFT is changed, obtains the phase time difference of first sampled value and the second sampled value, i.e. absolute delay time;
According to the absolute delay time and default delay threshold, the absolute delay time measurement of the Devices to test is determined Error.
Preferably, wherein the data processing platform (DPP) is on-site programmable gate array FPGA and digital signal processor DSP Framework.
Preferably, wherein the signal processing module, handles the standard sine wave table, standard electric piezoelectricity is obtained Signal is flowed, including:
Digital-to-analogue conversion is carried out to the standard sine wave signal, obtains standard sine wave analog signal;
Power amplification conversion process is carried out to the standard sine wave analog signal, obtains normal voltage current signal, and The normal voltage current signal is sent to Devices to test.
Preferably, wherein the default collection point amount threshold is 800.
Preferably, wherein the Devices to test is:Electronic transducer calibration instrument or combining unit tester.
Preferably, wherein the method further includes:
The error of absolute delay time is evaluated.
Preferably, wherein the error to the absolute delay time is evaluated, including:
Wherein, u1The standard electric piezoelectricity of synchronization pulse and the signal processing module output sent for data processing platform (DPP) Flow the first time error of signal;u2For message analysis module receive synchronization pulse and sampled value SV messages phase when Between difference and predetermined time delay threshold value the second time error;u3For optical fiber jitter error;u4For clock transfer jitter error; u5For measuring device error.
According to another aspect of the present invention, there is provided a kind of system for being calibrated to the absolute delay time, its It is characterized in that, the system comprises:
Data processing platform (DPP), for producing standard sine wave table, the standard sine wave table is sent to signal processing mould Block;For when reaching default delay threshold, handling the standard sine wave table, sampled value SV messages are obtained, and will The sampled value SV messages are sent to Devices to test;
Signal processing module, for handling the standard sine wave table, obtains normal voltage current signal, and will The normal voltage current signal is sent to Devices to test;
Devices to test, for while the sampled value SV messages are received, carrying out analog acquisition, obtains default collection First sampled value of point amount threshold;For being adopted respectively to first sampled value and the sampled value SV messages corresponding second Sample value carries out fast Fourier transform FFT, obtains the phase time difference of first sampled value and the second sampled value, i.e., definitely prolongs The slow time;
Error calculating module, for according to the absolute delay time and default delay threshold, determining the Devices to test Absolute delay time measurement error.
Preferably, wherein the data processing platform (DPP) is on-site programmable gate array FPGA and digital signal processor DSP Framework.
Preferably, wherein the signal processing module includes:
D/A conversion unit, for carrying out digital-to-analogue conversion to the standard sine wave signal, obtains standard sine wave simulation Signal;
Signal amplification unit, for carrying out power amplification conversion process to the standard sine wave analog signal, obtains mark Quasi- voltage and current signal, and the normal voltage current signal is sent to Devices to test.
Preferably, wherein the default collection point amount threshold is 800.
Preferably, wherein the Devices to test is:Electronic transducer calibration instrument or combining unit tester.
Preferably, wherein the system also includes:
Error evaluation module, for being evaluated to the error of absolute delay time.
Preferably, wherein the error evaluation module, evaluates the error of absolute delay time, including:
Wherein, u1The standard electric piezoelectricity of synchronization pulse and the signal processing module output sent for data processing platform (DPP) Flow the first time error of signal;u2For message analysis module receive synchronization pulse and sampled value SV messages phase when Between difference and predetermined time delay threshold value the second time error;u3For optical fiber jitter error;u4For clock transfer jitter error; u5For measuring device error.
The present invention provides a kind of method and system for being calibrated to the absolute delay time, using field-programmable Gate array FPGA and digital signal processor DSP architecture, it is accurate to produce time delay adjustable analog sine wave signal and numeral Sine wave signal.To electronic mutual inductor, the absolute delay time of combining unit tester is calibrated, and the error of itself is ingenious Calibrated by instruments such as clock standard and oscillographs, indirectly realize the magnitude tracing of absolute delay time, for its conjunction Method is effectively used as the technical basis that electric energy metering device provides.
Brief description of the drawings
By reference to the following drawings, the illustrative embodiments of the present invention can be more fully understood by:
Fig. 1 is for the flow chart for the method 100 calibrated to the absolute delay time according to embodiment of the present invention;
Fig. 2 is the schematic diagram calibrated to the absolute delay time according to embodiment of the present invention;And
Fig. 3 is to be shown according to the structure of the system 300 for being calibrated to the absolute delay time of embodiment of the present invention It is intended to.
Embodiment
The illustrative embodiments of the present invention are introduced referring now to attached drawing, however, the present invention can use many different shapes Formula is implemented, and is not limited to the embodiment described herein, there is provided these embodiments are to disclose at large and fully The present invention, and fully pass on the scope of the present invention to person of ordinary skill in the field.Show for what is be illustrated in the accompanying drawings Term in example property embodiment is not limitation of the invention.In the accompanying drawings, identical cells/elements use identical attached Icon is remembered.
Unless otherwise indicated, term (including scientific and technical terminology) used herein has person of ordinary skill in the field It is common to understand implication.Further it will be understood that the term limited with usually used dictionary, be appreciated that and its The linguistic context of association area has consistent implication, and is not construed as Utopian or overly formal meaning.
Fig. 1 is for the flow chart of the method 100 measured to the absolute delay time according to embodiment of the present invention. The application can be used in the absolute delay time measurement function progress to electronic transducer calibration instrument or combining unit tester Calibration.As shown in Figure 1, the method for being calibrated to the absolute delay time that embodiment of the present invention provides can using scene Program gate array FPGA and digital signal processor DSP architecture, it is accurate produce time delay adjustable analog sine wave signal and Digital sample values SV message signals.To electronic mutual inductor, the absolute delay time of combining unit tester is calibrated, itself Error cleverly calibrated by instruments such as clock standard and oscillographs, indirectly realize that the value of absolute delay time traces back Source, is its legal effective technical basis provided as electric energy metering device.What embodiment of the present invention provided is used for exhausted The method 100 measured to time delay produces standard since step 101 place, in step 101 using data processing platform (DPP) Sine wave table, and the standard sine wave table is sent to signal processing module.Preferably, wherein the data processing platform (DPP) is On-site programmable gate array FPGA and digital signal processor DSP architecture.
Preferably, the standard sine wave table is handled in step 102 signal processing module, obtains standard electric piezoelectricity Signal is flowed, and the normal voltage current signal is sent to Devices to test.
Preferably, wherein the signal processing module, handles the standard sine wave table, standard electric piezoelectricity is obtained Signal is flowed, including:
Digital-to-analogue conversion is carried out to the standard sine wave signal, obtains standard sine wave analog signal;
Power amplification conversion process is carried out to the standard sine wave analog signal, obtains normal voltage current signal, and The normal voltage current signal is sent to Devices to test.
Preferably, in step 103 when reaching default delay threshold, using data processing platform (DPP) to the standard sine wave Table is handled, and obtains sampled value SV messages, and the sampled value SV messages are sent to Devices to test.Preferably, wherein institute Stating Devices to test is:Electronic transducer calibration instrument or combining unit tester.
Preferably, while step 104 Devices to test is receiving the sampled value SV messages, analog acquisition is carried out, Obtain the first sampled value of default collection point amount threshold.
Preferably, wherein the default collection point amount threshold is 800.
Preferably, in step 105 the second sampling corresponding to first sampled value and the sampled value SV messages respectively Value carries out fast Fourier transform FFT, obtains the phase time difference of first sampled value and the second sampled value, i.e. absolute delay Time.
Preferably, the Devices to test is determined according to the absolute delay time and default delay threshold in step 106 Absolute delay time measurement error.
Preferably, wherein the method further includes:The error of absolute delay time is evaluated.
Preferably, wherein the error to the absolute delay time is evaluated, including:
Wherein, u1The standard electric piezoelectricity of synchronization pulse and the signal processing module output sent for data processing platform (DPP) Flow the first time error of signal;u2For message analysis module receive synchronization pulse and sampled value SV messages phase when Between difference and predetermined time delay threshold value the second time error;u3For optical fiber jitter error;u4For clock transfer jitter error; u5For measuring device error.
Fig. 2 is to carry out self-alignment schematic diagram to the absolute delay time according to embodiment of the present invention.As shown in Fig. 2, The frequency that data processing platform (DPP) sends signal can reach 100MHz, and the resolution ratio of clock reaches 10ns.When to absolute delay Between when being calibrated, data processing platform (DPP) 1 produces standard sine wave table to signal processing module 2, wherein in the starting of transmission Carve and start timing, and be simultaneously emitted by lock-out pulse to oscillograph 3.The normal voltage current signal exported through signal processing module 2 Oscillograph 3 is also accessed after conversion, the phase error of lock-out pulse and normal voltage electric current is first time error at this time.It is logical The phase of adjustment lock-out pulse and normal voltage electric current is crossed, ensures the rising of lock-out pulse rising edge and normal voltage current signal Start timing along zero crossing, and in guarantee lock-out pulse rising edge time, data processing platform (DPP) is opened when reaching default delay threshold Originate and send sampled value SV messages, wherein, Adjustment precision can reach nanosecond.
Time between lock-out pulse and sampled value SV messages is controlled by default delay threshold, is reached when the time of timer During default delay threshold, data processing platform (DPP) 1 sends sampled value SV messages to message analysis instrument 4, passes through message analysis instrument 4 The markers of No. 0 message wave head of capture and the markers of synchronizing signal, obtain the time delay between synchronizing signal and message, are pre- If delay threshold.The time delay can be compared with the time of timer, determine the accuracy of measurement, usually can reach Within 30 nanoseconds, synchronous error at this time is denoted as the second time error.
Evaluation to the error of absolute delay time includes:
Due to first time error u1With the second time error u2Uncorrelated, the error of absolute delay time is mainly frequency Caused by shake, therefore measuring system can be obtained to first time error and the squared average of the second time error Worst error.Then optical fiber shake u is considered3, clock transfer shake u4With measuring device error u5, it is overall to its square mean After number, the maximum uncertainty of whole device is obtained.
Fig. 3 is to be shown according to the structure of the system 300 for being calibrated to the absolute delay time of embodiment of the present invention It is intended to.The system of the application can be used in the absolute delay time survey to electronic transducer calibration instrument or combining unit tester Amount function is calibrated.As shown in figure 3, the system for being measured to the absolute delay time that embodiment of the present invention provides 300 include:Data processing platform (DPP) 301, signal processing module 302, Devices to test 303 and error calculating module 304.Preferably, In the data processing platform (DPP) 301, standard sine wave table is produced, the standard sine wave table is sent to signal processing module; For when reaching default delay threshold, handling the standard sine wave table, sampled value SV messages are obtained, and by described in Sampled value SV messages are sent to Devices to test.Preferably, wherein the data processing platform (DPP) is on-site programmable gate array FPGA With digital signal processor DSP architecture.
Preferably, in the signal processing module 302, the standard sine wave table is handled, obtains normal voltage Current signal, and the normal voltage current signal is sent to Devices to test.Preferably, wherein the signal processing module bag Include:
D/A conversion unit, for carrying out digital-to-analogue conversion to the standard sine wave signal, obtains standard sine wave simulation Signal;
Signal amplification unit, for carrying out power amplification conversion process to the standard sine wave analog signal, obtains mark Quasi- voltage and current signal, and the normal voltage current signal is sent to Devices to test.
Preferably, in the Devices to test 303, while the sampled value SV messages are received, analog acquisition is carried out, Obtain the first sampled value of default collection point amount threshold;For respectively to first sampled value and the sampled value SV messages Corresponding second sampled value carries out fast Fourier transform FFT, obtains the phase time of first sampled value and the second sampled value Difference, i.e. absolute delay time.
Preferably, in the error calculating module 304, according to the absolute delay time and default delay threshold, determine The absolute delay time measurement error of the Devices to test.Preferably, wherein the default collection point amount threshold is 800.
Preferably, wherein the Devices to test is:Electronic transducer calibration instrument or combining unit tester.
Preferably, wherein the system also includes:
Error evaluation module, for being evaluated to the error of absolute delay time.
Preferably, wherein the error evaluation module, evaluates the error of absolute delay time, including:
Wherein, u1The standard electric piezoelectricity of synchronization pulse and the signal processing module output sent for data processing platform (DPP) Flow the first time error of signal;u2For message analysis module receive synchronization pulse and sampled value SV messages phase when Between difference and predetermined time delay threshold value the second time error;u3For optical fiber jitter error;u4For clock transfer jitter error; u5For measuring device error.
The embodiment of the present invention for the system 300 calibrated to the absolute delay time and the present invention another Embodiment it is corresponding for the method 100 calibrated to the absolute delay time, details are not described herein.
By reference to a small amount of embodiment, the invention has been described.However, it is known in those skilled in the art, as What subsidiary Patent right requirement was limited, except the present invention other embodiments disclosed above equally fall the present invention's In the range of.
Normally, all terms used in the claims are all solved according to them in the common meaning of technical field Release, unless in addition clearly being defined wherein.All references " one/described/be somebody's turn to do [device, component etc.] " are all opened ground At least one example being construed in described device, component etc., unless otherwise expressly specified.Any method disclosed herein Step need not all be run with disclosed accurately order, unless explicitly stated otherwise.

Claims (14)

  1. A kind of 1. method for being calibrated to the absolute delay time, it is characterised in that the described method includes:
    Standard sine wave table is produced using data processing platform (DPP), and the standard sine wave table is sent to signal processing module;
    Signal processing module handles the standard sine wave table, obtains normal voltage current signal, and by the standard Voltage and current signal is sent to Devices to test;
    When reaching default delay threshold, the standard sine wave table is handled using data processing platform (DPP), obtains sampling Value SV messages, and the sampled value SV messages are sent to Devices to test;
    Devices to test carries out analog acquisition while the sampled value SV messages are received, and obtains default collection point quantity threshold First sampled value of value;
    Fast Fourier transform is carried out to first sampled value and corresponding second sampled value of the sampled value SV messages respectively FFT, obtains the phase time difference of first sampled value and the second sampled value, i.e. absolute delay time;
    According to the absolute delay time and default delay threshold, determine that the absolute delay time measurement of the Devices to test misses Difference.
  2. 2. according to the method described in claim 1, it is characterized in that, the data processing platform (DPP) is field programmable gate array FPGA and digital signal processor DSP architecture.
  3. 3. according to the method described in claim 1, it is characterized in that, the signal processing module, to the standard sine wave table Handled, obtain normal voltage current signal, including:
    Digital-to-analogue conversion is carried out to the standard sine wave signal, obtains standard sine wave analog signal;
    Power amplification conversion process is carried out to the standard sine wave analog signal, obtains normal voltage current signal, and by institute Normal voltage current signal is stated to send to Devices to test.
  4. 4. according to the method described in claim 1, it is characterized in that, the default collection point amount threshold is 800.
  5. 5. according to the method described in claim 1, it is characterized in that, the Devices to test is:Electronic transducer calibration instrument or Combining unit tester.
  6. 6. method according to any one of claim 1 to 5, it is characterised in that the method further includes:
    The error of absolute delay time is evaluated.
  7. 7. according to the method described in claim 6, it is characterized in that, the error to the absolute delay time is evaluated, bag Include:
    <mrow> <mi>U</mi> <mo>=</mo> <mn>2</mn> <mo>*</mo> <msqrt> <mfrac> <mrow> <msubsup> <mi>u</mi> <mn>1</mn> <mn>2</mn> </msubsup> <mo>+</mo> <msubsup> <mi>u</mi> <mn>2</mn> <mn>2</mn> </msubsup> <mo>+</mo> <msubsup> <mi>u</mi> <mn>3</mn> <mn>2</mn> </msubsup> <mo>+</mo> <msubsup> <mi>u</mi> <mn>4</mn> <mn>2</mn> </msubsup> <mo>+</mo> <msubsup> <mi>u</mi> <mn>5</mn> <mn>2</mn> </msubsup> </mrow> <mrow> <mn>5</mn> <mo>&amp;times;</mo> <mrow> <mo>(</mo> <mn>5</mn> <mo>-</mo> <mn>1</mn> <mo>)</mo> </mrow> </mrow> </mfrac> </msqrt> <mo>,</mo> <mi>k</mi> <mo>=</mo> <mn>2</mn> <mo>,</mo> </mrow>
    Wherein, u1The normal voltage electric current letter of synchronization pulse and the signal processing module output sent for data processing platform (DPP) Number first time error;u2The synchronization pulse and the phase time of sampled value SV messages received for message analysis module is poor Second time error of value and predetermined time delay threshold value;u3For optical fiber jitter error;u4For clock transfer jitter error;u5For Measuring device error.
  8. A kind of 8. system for being calibrated to the absolute delay time, it is characterised in that the system comprises:
    Data processing platform (DPP), for producing standard sine wave table, the standard sine wave table is sent to signal processing module;With In when reaching default delay threshold, the standard sine wave table is handled, obtains sampled value SV messages, and adopt described Sample value SV messages are sent to Devices to test;
    Signal processing module, for handling the standard sine wave table, obtains normal voltage current signal, and by described in Normal voltage current signal is sent to Devices to test;
    Devices to test, for while the sampled value SV messages are received, carrying out analog acquisition, obtains default collection points Measure the first sampled value of threshold value;For respectively to first sampled value and corresponding second sampled value of the sampled value SV messages Fast Fourier transform FFT is carried out, when obtaining the phase time difference, i.e. absolute delay of first sampled value and the second sampled value Between;
    Error calculating module, for according to the absolute delay time and default delay threshold, determining the exhausted of the Devices to test To delay time measurement error.
  9. 9. system according to claim 8, it is characterised in that the data processing platform (DPP) is field programmable gate array FPGA and digital signal processor DSP architecture.
  10. 10. system according to claim 8, it is characterised in that the signal processing module includes:
    D/A conversion unit, for carrying out digital-to-analogue conversion to the standard sine wave signal, obtains standard sine wave analog signal;
    Signal amplification unit, for carrying out power amplification conversion process to the standard sine wave analog signal, obtains standard electric Current voltage signal, and the normal voltage current signal is sent to Devices to test.
  11. 11. system according to claim 8, it is characterised in that the default collection point amount threshold is 800.
  12. 12. system according to claim 8, it is characterised in that the Devices to test is:Electronic transducer calibration instrument or Combining unit tester.
  13. 13. the system according to any one of claim 8 to 12, it is characterised in that the system also includes:
    Error evaluation module, for being evaluated to the error of absolute delay time.
  14. 14. system according to claim 13, it is characterised in that the error evaluation module, to the absolute delay time Error is evaluated, including:
    <mrow> <mi>U</mi> <mo>=</mo> <mn>2</mn> <mo>*</mo> <msqrt> <mfrac> <mrow> <msubsup> <mi>u</mi> <mn>1</mn> <mn>2</mn> </msubsup> <mo>+</mo> <msubsup> <mi>u</mi> <mn>2</mn> <mn>2</mn> </msubsup> <mo>+</mo> <msubsup> <mi>u</mi> <mn>3</mn> <mn>2</mn> </msubsup> <mo>+</mo> <msubsup> <mi>u</mi> <mn>4</mn> <mn>2</mn> </msubsup> <mo>+</mo> <msubsup> <mi>u</mi> <mn>5</mn> <mn>2</mn> </msubsup> </mrow> <mrow> <mn>5</mn> <mo>&amp;times;</mo> <mrow> <mo>(</mo> <mn>5</mn> <mo>-</mo> <mn>1</mn> <mo>)</mo> </mrow> </mrow> </mfrac> </msqrt> <mo>,</mo> <mi>k</mi> <mo>=</mo> <mn>2</mn> <mo>,</mo> </mrow>
    Wherein, u1The normal voltage electric current letter of synchronization pulse and the signal processing module output sent for data processing platform (DPP) Number first time error;u2The synchronization pulse and the phase time of sampled value SV messages received for message analysis module is poor Second time error of value and predetermined time delay threshold value;u3For optical fiber jitter error;u4For clock transfer jitter error;u5For Measuring device error.
CN201810005177.9A 2018-01-03 2018-01-03 A kind of method and system for being calibrated to the absolute delay time Pending CN107942280A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109406866A (en) * 2018-11-27 2019-03-01 北京锐创新智科技有限公司 Signal validation apparatus and method
CN111934760A (en) * 2020-08-14 2020-11-13 南方电网科学研究院有限责任公司 Signal processing transmission delay characteristic detection device and method and terminal equipment
CN112834798A (en) * 2020-12-21 2021-05-25 深圳供电局有限公司 Transformation ratio testing method, transformation ratio testing device, testing equipment and storage medium
US11506714B2 (en) 2021-04-12 2022-11-22 Digwise Technology Corporation, Ltd Setup time and hold time detection system and detection method
WO2023040058A1 (en) * 2021-09-17 2023-03-23 普源精电科技股份有限公司 Delay measurement apparatus and measurement method

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101581587A (en) * 2009-06-23 2009-11-18 北京航空航天大学 Method for automatically evaluating uncertainty of measurement of virtual instrument
CN202383278U (en) * 2011-12-07 2012-08-15 重庆市电力公司电力科学研究院 Merging unit sampling value time delay measuring system
CN102901874A (en) * 2012-11-08 2013-01-30 江苏凌创电气自动化股份有限公司 Phase- and time mark measurement-based electronic transformer absolute delay detection method
CN102944861A (en) * 2012-11-06 2013-02-27 中国电力科学研究院 Electronic transformer calibrator calibration device and method based on digital source
CN103293363A (en) * 2013-07-02 2013-09-11 东南大学 Time delay compensation method for mutual inductor sampling value
CN103605069A (en) * 2013-11-12 2014-02-26 北京四方继保自动化股份有限公司 Apparatus and method for realizing partial discharging monitoring of switch based on unconventional mutual inductor
CN103869187A (en) * 2014-03-11 2014-06-18 国家电网公司 Portable tester for time response of merging unit
CN104360298A (en) * 2014-11-12 2015-02-18 国家电网公司 Performance test system and method for merging unit tester
CN104396164A (en) * 2012-06-15 2015-03-04 微芯片技术股份有限公司 Communication system and method for synchronizing a plurality of network nodes after a network lock condition occurs
CN105376119A (en) * 2015-12-18 2016-03-02 国网河南省电力公司电力科学研究院 Intelligent transformer substation system grade time characteristic testing device
CN105652227A (en) * 2014-12-04 2016-06-08 国家电网公司 Method and system for measuring sample value (SV) rated time delay of relay protection tester

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101581587A (en) * 2009-06-23 2009-11-18 北京航空航天大学 Method for automatically evaluating uncertainty of measurement of virtual instrument
CN202383278U (en) * 2011-12-07 2012-08-15 重庆市电力公司电力科学研究院 Merging unit sampling value time delay measuring system
CN104396164A (en) * 2012-06-15 2015-03-04 微芯片技术股份有限公司 Communication system and method for synchronizing a plurality of network nodes after a network lock condition occurs
CN102944861A (en) * 2012-11-06 2013-02-27 中国电力科学研究院 Electronic transformer calibrator calibration device and method based on digital source
WO2014071753A1 (en) * 2012-11-06 2014-05-15 国家电网公司 Electronic transformer calibrator calibration device and method based on digital source
CN102901874A (en) * 2012-11-08 2013-01-30 江苏凌创电气自动化股份有限公司 Phase- and time mark measurement-based electronic transformer absolute delay detection method
CN103293363A (en) * 2013-07-02 2013-09-11 东南大学 Time delay compensation method for mutual inductor sampling value
CN103605069A (en) * 2013-11-12 2014-02-26 北京四方继保自动化股份有限公司 Apparatus and method for realizing partial discharging monitoring of switch based on unconventional mutual inductor
CN103869187A (en) * 2014-03-11 2014-06-18 国家电网公司 Portable tester for time response of merging unit
CN104360298A (en) * 2014-11-12 2015-02-18 国家电网公司 Performance test system and method for merging unit tester
CN105652227A (en) * 2014-12-04 2016-06-08 国家电网公司 Method and system for measuring sample value (SV) rated time delay of relay protection tester
CN105376119A (en) * 2015-12-18 2016-03-02 国网河南省电力公司电力科学研究院 Intelligent transformer substation system grade time characteristic testing device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
欧阳帆 等: "变电站合并单元测试设备校验系统及其实现", 《电力系统自动化》, vol. 41, no. 19, pages 152 - 158 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109406866A (en) * 2018-11-27 2019-03-01 北京锐创新智科技有限公司 Signal validation apparatus and method
CN111934760A (en) * 2020-08-14 2020-11-13 南方电网科学研究院有限责任公司 Signal processing transmission delay characteristic detection device and method and terminal equipment
CN111934760B (en) * 2020-08-14 2021-12-28 南方电网科学研究院有限责任公司 Signal processing transmission delay characteristic detection device and method and terminal equipment
CN112834798A (en) * 2020-12-21 2021-05-25 深圳供电局有限公司 Transformation ratio testing method, transformation ratio testing device, testing equipment and storage medium
US11506714B2 (en) 2021-04-12 2022-11-22 Digwise Technology Corporation, Ltd Setup time and hold time detection system and detection method
WO2023040058A1 (en) * 2021-09-17 2023-03-23 普源精电科技股份有限公司 Delay measurement apparatus and measurement method

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