CN203720587U - Waveform generation device based on DDS technology - Google Patents
Waveform generation device based on DDS technology Download PDFInfo
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- CN203720587U CN203720587U CN201420033930.2U CN201420033930U CN203720587U CN 203720587 U CN203720587 U CN 203720587U CN 201420033930 U CN201420033930 U CN 201420033930U CN 203720587 U CN203720587 U CN 203720587U
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Abstract
The utility model discloses a waveform generation device based on DDS technology. The device comprises a main control module, and an FPGA chip, an amplitude control module, a display module and a matrix keyboard respectively connected with the main control module, and also comprises a digital to analog conversion module and a low pass filter, wherein the FPGA chip is connected with the low pass filter via the digital to analog conversion module; and the amplitude control module is connected with the digital to analog conversion module. According to the waveform generation device based on the DDS technology, problems that stability of generated waveform frequency is not high, accuracy is poor, generation of arbitrary waveforms can not be realized and the like in the prior art can be solved.
Description
Technical field
The utility model relates to a kind of waveshape generating device, particularly a kind of waveshape generating device based on DDS technology.
Background technology
Waveform generator is that a kind of undesired signal is inputted and can produce the electronic installation of various periodic waveforms outputs.Divide according to the waveform producing, have sine-wave generator and non-sinusoidal wave generator two classes.Non-sinusoidal wave generator comprises again square wave, triangular wave, sawtooth wave etc.Traditional waveform generator adopts Analog Electronics Technique more, and the shortcoming such as the circuit that forms of analog device exists that size is large, price, power consumption are large, and will produce complicated signal waveform, and circuit structure is more complicated.After the seventies, the appearance of microprocessor, can utilize single-chip microcomputer to do control center and adopt phase-locking type frequency synthesis scheme.But the waveform frequency degree of stability that this scheme produces is not high, poor accuracy, be difficult to meet the area requirement of frequency change, more cannot realize the generation of random wave.
Utility model content
The problem existing in order to solve above-mentioned background technology, the utility model aims to provide a kind of waveshape generating device based on DDS technology, overcomes that the waveform frequency degree of stability of generation that prior art exists is not high, poor accuracy and can not realize the problem such as generation of random wave.
In order to realize above-mentioned technical purpose, the technical scheme of this utility model is:
A kind of waveshape generating device based on DDS technology, it is characterized in that: comprise main control module and the fpga chip being attached thereto respectively, amplitude control module, display module and matrix keyboard, also comprise D/A converter module and low-pass filter, described fpga chip is by D/A converter module and low-pass filter, and described amplitude control module is connected with D/A converter module.
Wherein, above-mentioned fpga chip comprises phase accumulator and waveform table module, the input end of described phase accumulator is connected with main control module, and the output terminal of phase accumulator is connected with the input end of waveform table module, and the output terminal of waveform table module is connected with D/A converter module.
Wherein, above-mentioned amplitude control module comprises the DAC0832 and the operational amplifier that connect successively.
Wherein, above-mentioned D/A converter module comprises the DAC908 and the voltage amplifier that connect successively.
Wherein, above-mentioned main control module adopts MSP430F149 single-chip microcomputer.
Wherein, above-mentioned fpga chip adopts Cyclone II EP2C8Q208C8.
Wherein, above-mentioned display module adopts LCD12864.
The beneficial effect that adopts technique scheme to bring is:
The utility model utilizes single-chip microcomputer to coordinate some peripheral analog digital devices, realized the signal output of multiple waveforms, and it can reach very high precision in the time of low frequency signal.The utility model has been realized the wave forms generator of a kind of flexible programming, fast response time, this waveform generator can be realized arbitrary signal output, and friendly man-machine interface and multiple waveforms method for customizing is provided, be that a kind of low price, power consumption are little, the signal source device of easy care.
Brief description of the drawings
Fig. 1 is system architecture diagram of the present utility model.
Fig. 2 is the chip pin figure of main control module of the present utility model.
Fig. 3 is the pinouts of fpga chip of the present utility model.
Fig. 4 is the chip pin figure of display module of the present utility model.
Fig. 5 is amplitude control module circuit diagram of the present utility model.
Fig. 6 is D/A converter module circuit diagram of the present utility model.
Fig. 7 is low-pass filter circuit figure of the present utility model.
Embodiment
Below with reference to accompanying drawing, the technical solution of the utility model is elaborated.
System architecture diagram of the present utility model as shown in Figure 1, a kind of waveshape generating device based on DDS technology, it is characterized in that: comprise main control module and the fpga chip being attached thereto respectively, amplitude control module, display module and matrix keyboard, also comprise D/A converter module and low-pass filter, described fpga chip is by D/A converter module and low-pass filter, and described amplitude control module is connected with D/A converter module.Fpga chip comprises phase accumulator and waveform table module, and the input end of described phase accumulator is connected with main control module, and the output terminal of phase accumulator is connected with the input end of waveform table module, and the output terminal of waveform table module is connected with D/A converter module.
In the present embodiment, described main control module adopts MSP430F149 single-chip microcomputer, as shown in Figure 2.Fpga chip adopts Cyclone II EP2C8Q208C8, as shown in Figure 3.The P3[7...0 of single-chip microcomputer MSP430F149] pin is connected with PIN_56, PIN_47, PIN_45, PIN_43, PIN_40, PIN_37, PIN_35, the PIN_31 of FPGA respectively, as the communication bus between these two devices.P4.1, the P4.0 of single-chip microcomputer is connected with PIN_8, the PIN_3 of FPGA, transmits and writes control word WR and address control word ADD to FPGA respectively.P6.1, the P6.0 of single-chip microcomputer is connected with PIN_11, the PIN_13 of FPGA, transmits waveform and selects control word WVD[1...0] to FPGA.Display module adopts LCD12864, as shown in Figure 4, the 8 position datawire D[7..0 of LCD12864] with the P5[7...0 of single-chip microcomputer] be connected, control line RS, RW, EN, RESET are connected with P4.4, P4.5, P4.6, the P4.7 of single-chip microcomputer respectively successively.
In the present embodiment, described amplitude control module comprises the DAC0832 and the operational amplifier that connect successively.Amplitude control module circuit diagram of the present utility model as shown in Figure 5, the D[7...0 of DAC0832] pin respectively with the P2[7..0 of single-chip microcomputer] be connected, and CS, WR1, these 3 direct ground connection of pin of WR2.Two-way output terminal IOUT1 and IOUT2 connect respectively end of oppisite phase and the in-phase end of operational amplifier, output terminal feedback are taken back to RFB pin simultaneously, to realize current conversion as voltage, generate the reference voltage of final amplitude control.
In the present embodiment, described D/A converter module comprises the DAC908 and the voltage amplifier that connect successively.Voltage amplifier adopts OPA690.The circuit diagram of D/A converter module of the present utility model as shown in Figure 6, the eight bit data pin D[7 of DAC908 ... 0] be connected with PIN_147, PIN_145, PIN_143, PIN_141, PIN_138, PIN_135, PIN_133, the PIN_127 of FPGA respectively, clock pins CLK is connected with the PIN_117 pin of FPGA, and REF is as being connected with amplitude control module with reference to voltage input end.The IOUT pin of DAC908 is received the inverting input of OPA690 through the first resistance R 1, the inverting input of OPA690 is received the output terminal of OPA690 through potentiometer Rp1, the IOUB of DAC908 receives the in-phase input end of OPA690 through the second resistance R 2, the in-phase input end of OPA690 is through the 3rd resistance eutral grounding.By regulator potentiometer can Rp1 the amplitude of fine setting output voltage.Wherein R1, R2 resistance are 2k Ω, and R3 resistance is 510 Ω, and potentiometer Rp1 resistance is 1k Ω.
In the present embodiment, low-pass filter adopts classical second order voltage controlled filter (Sallen-Key) connection, as shown in Figure 7.Amplifier is selected OPA690, and the in-phase input end of OPA690 is as the input of second-order filter, and the anti-phase input of OPA690 terminates to output terminal.The in-phase input end of OPA690 connect successively the 5th resistance R 5 and the 4th resistance R 4, common port ground connection after the second capacitor C 2 of the in-phase input end of the 5th resistance R 5 and OPA690, the common port of the 5th resistance R 5 and the 4th resistance R 4 is received the output terminal of OPA690 after the first capacitor C 1.Wherein, R4 resistance is 5.6k Ω, and R5 resistance is 5.6k Ω, and C1 electric capacity is 200pF, and C2 electric capacity is 100pF.
Principle of work of the present utility model is: main control module and FPGA adopt parallel communications, transmit shape information and frequency control word to the phase-accumulated module of FPGA, carry out waveform selection and frequency control by entering FPGA waveform table module after the definite speed of tabling look-up of phase-accumulated module, with continuous wave output 8 digit wave form data; Data are directly delivered to D/A converter module with output respective waveforms; Main control module transmits amplitude information and enters amplitude control module simultaneously, produces the reference voltage of different DC voltage as D/A converter module, to reach amplitude control; The output waveform of D/A converter module is passed through low-pass filter again, and filtering high frequency edge, finally obtains relatively level and smooth waveform.The utility model adopts low-power scm MSP430F149 as master controller, and field programmable gate array (FPGA) chip CycloneII:EP2C8Q208C8 is as waveform memory storage.Wave data converts simulating signal to through digital to analog converter DAC908 from FPGA output.Wherein, the phase place of waveform and frequency parameter send out phase control words by single-chip microcomputer and frequency control word is realized to FPGA, export analog current by Single-chip Controlling analog to digital converter DAC0832, then after current conversion is voltage, realize the amplitude adjusted of waveform through amplifier as the reference voltage of digital to analog converter DAC90.Input with matrix keyboard as man-machine interaction, is used for inputting type of waveform, frequency, phase place and amplitude, and design parameter shows by LCD12864.
Above embodiment is only explanation technological thought of the present utility model; can not limit protection domain of the present utility model with this; every technological thought according to the utility model proposes, any change of doing on technical scheme basis, within all falling into the utility model protection domain.
Claims (7)
1. the waveshape generating device based on DDS technology, it is characterized in that: comprise main control module and the fpga chip being attached thereto respectively, amplitude control module, display module and matrix keyboard, also comprise D/A converter module and low-pass filter, described fpga chip is by D/A converter module and low-pass filter, and described amplitude control module is connected with D/A converter module.
2. a kind of waveshape generating device based on DDS technology according to claim 1, it is characterized in that: described fpga chip comprises phase accumulator and waveform table module, the input end of described phase accumulator is connected with main control module, the output terminal of phase accumulator is connected with the input end of waveform table module, and the output terminal of waveform table module is connected with D/A converter module.
3. a kind of waveshape generating device based on DDS technology according to claim 1, is characterized in that: described amplitude control module comprises the DAC0832 and the operational amplifier that connect successively.
4. a kind of waveshape generating device based on DDS technology according to claim 1, is characterized in that: described D/A converter module comprises the DAC908 and the voltage amplifier that connect successively.
5. a kind of waveshape generating device based on DDS technology according to claim 1, is characterized in that: described main control module adopts MSP430F149 single-chip microcomputer.
6. a kind of waveshape generating device based on DDS technology according to claim 1, is characterized in that: described fpga chip adopts Cyclone II EP2C8Q208C8.
7. a kind of waveshape generating device based on DDS technology according to claim 1, is characterized in that: described display module adopts LCD12864.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201420033930.2U CN203720587U (en) | 2014-01-21 | 2014-01-21 | Waveform generation device based on DDS technology |
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| CN201420033930.2U CN203720587U (en) | 2014-01-21 | 2014-01-21 | Waveform generation device based on DDS technology |
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| CN203720587U true CN203720587U (en) | 2014-07-16 |
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| CN201420033930.2U Expired - Fee Related CN203720587U (en) | 2014-01-21 | 2014-01-21 | Waveform generation device based on DDS technology |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104391142A (en) * | 2014-12-22 | 2015-03-04 | 永新电子常熟有限公司 | Novel convenient signal generator |
| CN104714456A (en) * | 2015-03-19 | 2015-06-17 | 苏州市职业大学 | Method for improving low-frequency signal output amplitude and controlling accuracy |
| CN105842562A (en) * | 2016-03-30 | 2016-08-10 | 东莞市广安电气检测中心有限公司 | Device for testing immunity to common-mode conducted disturbance |
| CN106444962A (en) * | 2016-11-30 | 2017-02-22 | 桂林电子科技大学 | Drawing random waveform signal generator |
| CN106681426A (en) * | 2017-01-03 | 2017-05-17 | 聊城大学 | Simple and economic waveform generator based on DDS technology |
| CN108414790A (en) * | 2018-02-12 | 2018-08-17 | 四川海特亚美航空技术有限公司 | Aero-engine speed probe simulator based on DDS and method |
| CN108445388A (en) * | 2018-02-12 | 2018-08-24 | 四川海特亚美航空技术有限公司 | Threephase alternator simulation device based on DDS and method |
| CN111796620A (en) * | 2020-07-09 | 2020-10-20 | 广州大学 | Waveform generation circuit and method with variable reference voltage |
-
2014
- 2014-01-21 CN CN201420033930.2U patent/CN203720587U/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104391142A (en) * | 2014-12-22 | 2015-03-04 | 永新电子常熟有限公司 | Novel convenient signal generator |
| CN104714456A (en) * | 2015-03-19 | 2015-06-17 | 苏州市职业大学 | Method for improving low-frequency signal output amplitude and controlling accuracy |
| CN104714456B (en) * | 2015-03-19 | 2018-06-01 | 苏州市职业大学 | A kind of method for improving the output of low frequency signal amplitude and controlling its precision |
| CN105842562A (en) * | 2016-03-30 | 2016-08-10 | 东莞市广安电气检测中心有限公司 | Device for testing immunity to common-mode conducted disturbance |
| CN105842562B (en) * | 2016-03-30 | 2018-12-21 | 东莞市广安电气检测中心有限公司 | A kind of device for the test of common mode conduction interference immunity to interference |
| CN106444962A (en) * | 2016-11-30 | 2017-02-22 | 桂林电子科技大学 | Drawing random waveform signal generator |
| CN106681426A (en) * | 2017-01-03 | 2017-05-17 | 聊城大学 | Simple and economic waveform generator based on DDS technology |
| CN108414790A (en) * | 2018-02-12 | 2018-08-17 | 四川海特亚美航空技术有限公司 | Aero-engine speed probe simulator based on DDS and method |
| CN108445388A (en) * | 2018-02-12 | 2018-08-24 | 四川海特亚美航空技术有限公司 | Threephase alternator simulation device based on DDS and method |
| CN111796620A (en) * | 2020-07-09 | 2020-10-20 | 广州大学 | Waveform generation circuit and method with variable reference voltage |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C53 | Correction of patent for invention or patent application | ||
| CB03 | Change of inventor or designer information |
Inventor after: Liu Heng Inventor after: You Tianyu Inventor after: Song An Inventor after: Ding Jun Inventor before: Liu Heng Inventor before: You Tianyu Inventor before: Song An Inventor before: Ding Jun |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140716 Termination date: 20160121 |
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| EXPY | Termination of patent right or utility model |