CN102426472B - Hardware-in-the-loop generator and use method thereof - Google Patents
Hardware-in-the-loop generator and use method thereof Download PDFInfo
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Abstract
The invention discloses a hardware-in-the-loop generator which comprises a physical object part and a non-physical object part, wherein the non-physical object part is an upper computer loaded with waveform design simulation software; the physical object part is a lower computer; the lower computer comprises a D/A (Digital/Analogue) converter circuit, a signal conditioning circuit and an FPGA (Field Programmable Gate Array) chip in which an NiosII soft core processor is embedded; when the hardware-in-the-loop generator is in use, the non-physical object part can be used for calling an automatic mode by manual operation or program to set parameters of simulation waveform; if the displayed simulation waveform meets the requirement, module parameters are generated and transmitted to the lower computer and then are matched with an NiosII soft core processor and dual-port RAM (Random Access Memory) and DDS (Direct Digital Synthesizer) modules to transmit the processed digital signal to the D/A converter circuit; and finally, the processed digital signal is processed by the D/A converter circuit and the signal conditioning circuit to obtain a final signal. With the design, the hardware-in-the-loop generator disclosed by the invention has the advantages of higher precision, stronger intuitiveness, lower production cost, higher automatic degree and wide application range.
Description
Technical field
The present invention relates to a kind of signal generator, relate in particular to a kind of half signal generator in kind and using method thereof, be specifically applicable to Nios II soft-core processor, DDS technology, SOPC technology to combine to produce signal with upper computer software, lower computer hardware.
Background technology
At present, the function signal generator of special use mainly contains analog-and digital-two types on the market.Analog signal generator adopts the conversion of mimic channel settling signal, and precision is low, distortion is large, does not substantially re-use; Digital signal generator adopts DDS technology more, utilizes calculating and the output of the mode settling signal that DSP combines with FPGA, although precision is higher, requires circuit to have stronger arithmetic capability, and cost is higher.
In addition, the mode that existing signal generator adopts panel button to control more arranges parameter and the type of waveform, and not only man-machine interface demonstration is directly perceived not, and equipment volume is large, cost is higher.
China Patent Publication No. is CN101162398A, the patent of invention that open day is on April 16th, 2008 discloses a kind of arbitrarily signal generating device based on FPGA, comprises PC, USB controller, MCU3, MCU interface module, crystal oscillator, EPC2, clock controller, binary channels DA output circuit, frequency controller, register matrix unit, keyboard, keyboard scan module, FLASH, FLASH control module, TFT display, TFT control module, DDS signal generator, waveform synthesis module and other waveform generator; During use, on software control interface, after input spectrum figure and phase spectrum graph parameter, software completes spectrum information identification automatically, obtains the phase and magnitude parameter of frequency; Then will after sampled value quantization encoding, obtain time-domain information table, download in the RAM of DDS generation circuit, performance period or aperiodic time-domain signal reduction output, and the online stepping of wave-shape amplitude is adjustable.Although this invention can be inputted by frequency domain, the mode of time domain output produces required signal, it still has following defect:
First, this invention is to produce required signal by the mode that frequency domain is inputted, time domain is exported, rather than the various parameters of signal waveform are directly set, directly specific aim a little less than, there is distortion to a certain degree, especially between frequency domain input, time domain output, also will could realize through Fourier transform, this has further increased the possibility of distortion, so the degree of accuracy of this invention is poor;
Secondly, this invention is by the software settling signal data of PC and upper loading thereof, by USB interface, be sent to successively MCU again, fpga chip in slave computer is to produce signal, wherein, when signal data produces, can only obtain time-domain information table, and do not have emulation to show for the concrete condition of reality generation signal, intuitive is too poor, once arrange wrong, can only after showing, just can reflect slave computer, then do over again, larger waste manpower and material resources, increased production cost, in addition, this invention does not make full use of the internal resource of fpga chip, but pass through MCU, the combined mode of fpga chip is carried out computing to signal data, thereby settling signal occurs, this has not only increased the volume of equipment, and again increased production cost, therefore this invent not only intuitive a little less than, and production cost is higher,
The 3rd, the operations such as the input of this invention intermediate frequency spectrogram and phase place spectrogram, Fourier transform, periodic sampling, all depend on manual input, and this has increased operation easier, so the automaticity of this invention is lower;
The 4th, host computer in this invention is sent to signal data in MCU, fpga chip successively by USB interface, and not only transmission range is limited, and can only carry out man-to-man transmission, limited greatly the range of application of this device, so the range of application of this invention is narrower.
Summary of the invention
The object of the invention is to overcome the degree of accuracy existing in prior art is poor, intuitive is weak, production cost is higher, automaticity is lower, range of application is narrower defect and problem, half signal generator in kind and the using method thereof that a kind of degree of accuracy is higher, intuitive is strong, production cost is lower, automaticity is higher, range of application is wider is provided.
For realizing above object, technical solution of the present invention is: a kind of half signal generator in kind, comprise interconnective host computer and slave computer, described slave computer comprises fpga chip and DA converter circuit, one end of fpga chip and host computer communication connection, the other end is connected with DA converter circuit, and on fpga chip, be connected with power supply, serial FLASH and clock;
On described host computer, be mounted with Waveform Design simulation software, the quantity of described slave computer is at least one, and slave computer also comprises signal conditioning circuit; On described fpga chip, be also connected with RS232 interface, Ethernet interface and SDRAM storer, and in fpga chip, be provided with Nios II soft-core processor, DDS module, dual port RAM and frequency control word register;
Described Nios II soft-core processor comprises CPU processor, URAT controller, sdram controller, EPCS controller, ethernet controller, a PIO controller and No. two PIO controllers, CPU processor is by URAT controller, sdram controller, EPCS controller, ethernet controller respectively with RS232 interface, SDRAM storer, serial FLASH, Ethernet interface communication connection, RS232 interface, the other end of Ethernet interface all communicates to connect with host computer, CPU processor is connected with dual port RAM by a PIO controller, the other end of dual port RAM respectively with DDS module, DA converter circuit is connected, the other end of DDS module is successively by frequency control word register, No. two PIO controller is connected with CPU processor, the other end of DA converter circuit is connected with signal conditioning circuit.
Described host computer is PC, and described fpga chip adopts Cyclone, Cyclone II or the Cyclone III family chip of altera corp.
Described DA converter circuit comprises a high-speed D/A converters and a low-speed highly precise DA converter, one end of high-speed D/A converters is connected with dual port RAM, the other end is connected with signal conditioning circuit, one end of low-speed highly precise DA converter is connected with dual port RAM, and the other end is as the reference source input of high-speed D/A converters.
Described signal conditioning circuit comprises fixed gain amplifier, LC wave filter and power amplifier, and this fixed gain amplifier is connected with the other end of high-speed D/A converters.
A using method for above-mentioned half signal generator in kind, this using method comprises the following steps successively:
The first step: first the Waveform Design simulation software of upper internal stowage is arranged, its method to set up comprises that interface manually arranges and routine call Lookup protocol, and it arranges content and comprises: communication port, signal type, amplitude, frequency, phase place and low and high level; Described communication port comprises RS232 interface or Ethernet interface, and described signal type comprises sine wave, triangular wave and the square wave in reference waveform;
Second step: above-mentioned setting after end of text, on the screen of host computer, demonstrate simulation waveform again, if the simulation waveform showing meets the requirements, Ze Yougai Waveform Design simulation software generates the required module parameter of DDS module in slave computer, this module parameter comprises waveform ROM table data, phase accumulator initial value and amplitude control signal, then by RS232 interface or Ethernet interface, this module parameter is sent to slave computer;
The 3rd step: first switch on power, by serial FLASH, fpga chip is configured again, and Nios II soft-core processor is carried out to program loading, then by Nios II soft-core processor, by RS232 interface or Ethernet interface, receive the module parameter that host computer sends, and this module parameter is deposited in SDRAM storer, by CPU processor, carry out computing again, then the digital signal of computing gained is deposited in dual port RAM, and coordinate this digital signal is passed to DA converter circuit with DDS module, by DA converter circuit, this digital signal is converted to simulating signal again, then by signal conditioning circuit, processed, now can obtain final signal.
In the described first step computing and the modulation that content also comprises signal be set, its method to set up is: first complete the setting of two groups of signals, then Selecting operation mode, this compute mode comprises and adding, subtracts, multiplication and signal modulation, then determine, can the computing of end signal and the setting of modulation.
In the described first step, when adopting the manual set-up mode in interface, its signal type also comprises random waveform, the set-up mode of this random waveform is: first open waveform drawing panel, again with the mouse waveform that manual drawing is wanted in waveform drawing panel, then clicked, can finish the setting of random waveform.
In the described first step, the maximal value of amplitude is 5V, and frequency is 0.1Hz – 10MHz.
Compared with prior art, beneficial effect of the present invention is:
1, owing in a kind of half signal generator in kind of the present invention and using method Zhong Xian Waveform Design simulation software thereof, communication port, signal type, amplitude, frequency, phase place and low and high level being set, on the screen of host computer, demonstrate simulation waveform again, if the waveform showing meets the requirements, Ze Yougai Waveform Design simulation software generates the module parameter that DDS module needs; First, the direct parameter that the content of setting of the present invention is signal waveform, directly specific aim is stronger, is difficult for distortion, have higher degree of accuracy, and the present invention can also carry out computing and the modulation of signal when arranging, and can further improve degree of accuracy; Secondly, the design first shows simulation waveform, just generation module parameter meets the requirements, not only intuitive is stronger, and is convenient to improve degree of accuracy and avoids doing over again, and has saved production cost, especially when adopting the manual set-up mode in interface, its signal type is random waveform, and the complete armrest of this random waveform is depicted as, and intuitive is extremely strong.Therefore not only degree of accuracy is higher, intuitive is stronger in the present invention, and production cost is lower.
2, owing to being embedded with Nios II soft-core processor at fpga chip in a kind of half signal generator in kind of the present invention and using method thereof, the data that this Nios II soft-core processor can come host computer transmission are stored, computing, and the digital signal of computing gained is deposited in dual port RAM, and coordinate this digital signal is passed to DA converter circuit with DDS module, this kind of Nios II soft-core processor design takes full advantage of the internal resource of fpga chip, combine fpga chip and process the fireballing advantage of digital circuit and Nios II soft-core processor processing controls task and data communication advantage easily, rather than as prior art, pass through MCU, the combined mode of fpga chip is carried out computing to signal data, the design has not only reduced the operand of system, and saved a MCU, integrated keyboard and display screen, simplified hardware configuration, dwindled the volume of equipment, reduced the cost of equipment.Therefore production cost of the present invention is lower.
While 3, communication port, signal type, amplitude, frequency, phase place and low and high level being set in Waveform Design simulation software due to a kind of half signal generator in kind of the present invention and using method thereof, its method to set up comprises that interface manually arranges and routine call Lookup protocol, this routine call Lookup protocol refers to and can complete setting by the mode of coding (Matlab, VC++), greatly alleviated manual fatigue.Therefore automaticity of the present invention is higher.
4, because the host computer in a kind of half signal generator in kind of the present invention and using method thereof can be adopted as common PC, this design not only can effectively utilize PC fast operation, man-machine interface close friend's feature, large to solve slave computer operand, button arranges inconvenient technical barrier, PC has been equipped with but also can be widely used in laboratory etc., the occasion that needs signal source, can be under the condition of lowering apparatus performance not, reduce volume and the cost of signal generator, reach at lower cost, hardware simplicity, smaller size smaller realizes the object of signal simulation and output, and the host computer in the present invention can flow to many slave computers by data by Ethernet interface, not only transmission range is far away, and connection object is one-to-many, has greatly expanded range of application of the present invention, in addition, the present invention not only can be applied to the design of instrument and meter, can also be applied in the circuit that needs arbitrary signal generation, as submodule wherein, independently use, can the data of host computer transmission be saved in serial FLASH by slave computer, then slave computer is departed to host computer and use, no longer need upper computer software to transmit data toward slave computer, during use, only need power on, the data of preserving in serial FLASH will be loaded in SDRAM storer, have expanded the design's range of application.Therefore range of application of the present invention is wider.
5, because the DA converter circuit in a kind of half signal generator in kind of the present invention and using method thereof comprises a high-speed D/A converters and a low-speed highly precise DA converter, the output of low-speed highly precise DA converter is the reference source input of high-speed D/A converters, this design uses the output voltage of the high-precision low speed DA of a slice converter as the reference voltage of high-speed D/A converters, now, when less output voltage, magnitude of voltage corresponding to each resolution is less, be convenient to the amplitude of waveform signal to adjust, greatly improved the precision in system dynamic adjustments amplitude process, reduced noise, reduced error.Therefore degree of accuracy of the present invention is higher.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention.
Fig. 2 is the structural representation of DA converter circuit in Fig. 1.
In figure: host computer 1, slave computer 2, fpga chip 3, serial FLASH 4, RS232 interface 5, SDRAM storer 6, Nios II soft-core processor 7, CPU processor 71, URAT controller 72, sdram controller 73, EPCS controller 74, ethernet controller 75, a PIO controller 76, No. two PIO controllers 77, DDS module 8, DA converter circuit 9, high-speed D/A converters 91, low-speed highly precise DA converter 92, signal conditioning circuit 10, power supply 11, clock 12, Ethernet interface 13, dual port RAM 14, frequency control word register 15.
Embodiment
Below in conjunction with accompanying drawing explanation and embodiment, the present invention is further detailed explanation.
Referring to figure 1 – Fig. 2, a kind of half signal generator in kind, comprise interconnective host computer 1 and slave computer 2, described slave computer 2 comprises fpga chip 3 and DA converter circuit 9, one end of fpga chip 3 and host computer 1 communication connection, the other end is connected with DA converter circuit 9, and on fpga chip 3, be connected with power supply 11, serial FLASH 4 and clock 12;
On described host computer 1, be mounted with Waveform Design simulation software, the quantity of described slave computer 2 is at least one, and slave computer 2 also comprises signal conditioning circuit 10; On described fpga chip 3, be also connected with RS232 interface 5, Ethernet interface 13 and SDRAM storer 6, and in fpga chip 3, be provided with Nios II soft-core processor 7, DDS module 8, dual port RAM 14 and frequency control word register 15;
Described Nios II soft-core processor 7 comprises CPU processor 71, URAT controller 72, sdram controller 73, EPCS controller 74, ethernet controller 75, a PIO controller 76 and No. two PIO controllers 77, CPU processor 71 is by URAT controller 72, sdram controller 73, EPCS controller 74, ethernet controller 75 respectively with RS232 interface 5, SDRAM storer 6, serial FLASH 4, Ethernet interface 13 communication connections, RS232 interface 5, the other end of Ethernet interface 13 all communicates to connect with host computer 1, CPU processor 71 is connected with dual port RAM 14 by a PIO controller 76, the other end of dual port RAM 14 respectively with DDS module 8, DA converter circuit 9 is connected, the other end of DDS module 8 is successively by frequency control word register 15, No. two PIO controller 77 is connected with CPU processor 71, the other end of DA converter circuit 9 is connected with signal conditioning circuit 10.
Described host computer 1 is PC, and described fpga chip 3 adopts Cyclone, Cyclone II or the Cyclone III family chip of altera corp.
Described DA converter circuit 9 comprises a high-speed D/A converters 91 and a low-speed highly precise DA converter 92, one end of high-speed D/A converters 91 is connected with dual port RAM 14, the other end is connected with signal conditioning circuit 10, one end of low-speed highly precise DA converter 92 is connected with dual port RAM 14, and the other end is as the reference source input of high-speed D/A converters 91.
Described signal conditioning circuit 10 comprises fixed gain amplifier, LC wave filter and power amplifier, and this fixed gain amplifier is connected with the other end of high-speed D/A converters 91.
A using method for above-mentioned half signal generator in kind, this using method comprises the following steps successively:
The first step: first the Waveform Design simulation software of host computer 1 interior loading is arranged, its method to set up comprises that interface manually arranges and routine call Lookup protocol, and it arranges content and comprises: communication port, signal type, amplitude, frequency, phase place and low and high level; Described communication port comprises RS232 interface 5 or Ethernet interface 13, and described signal type comprises sine wave, triangular wave and the square wave in reference waveform;
Second step: above-mentioned setting after end of text, on the screen of host computer 1, demonstrate simulation waveform again, if the simulation waveform showing meets the requirements, Ze Yougai Waveform Design simulation software generates the required module parameter of DDS module 8 in slave computer 2, this module parameter comprises waveform ROM table data, phase accumulator initial value and amplitude control signal, then by RS232 interface 5 or Ethernet interface 13, this module parameter is sent to slave computer 2;
The 3rd step: first switch on power 11, by 4 pairs of fpga chips 3 of serial FLASH, be configured again, and Nios II soft-core processor 7 is carried out to program loading, then by Nios II soft-core processor 7, by RS232 interface 5 or Ethernet interface 13, receive the module parameter that host computer 1 sends, and this module parameter is deposited in SDRAM storer 6, by CPU processor 71, carry out computing again, then the digital signal of computing gained is deposited in dual port RAM 14, and coordinate this digital signal is passed to DA converter circuit 9 with DDS module 8, by DA converter circuit 9, this digital signal is converted to simulating signal again, then by signal conditioning circuit 10, processed, now can obtain final signal.
In the described first step computing and the modulation that content also comprises signal be set, its method to set up is: first complete the setting of two groups of signals, then Selecting operation mode, this compute mode comprises and adding, subtracts, multiplication and signal modulation, then determine, can the computing of end signal and the setting of modulation.
In the described first step, when adopting the manual set-up mode in interface, its signal type also comprises random waveform, the set-up mode of this random waveform is: first open waveform drawing panel, again with the mouse waveform that manual drawing is wanted in waveform drawing panel, then clicked, can finish the setting of random waveform.
In the described first step, the maximal value of amplitude is 5V, and frequency is 0.1Hz – 10MHz.
Principle of the present invention is described as follows:
Waveform Design simulation software: this software loading is in host computer, there is dynamic link calling function, and dynamic link calling function can be realized the program setting of signal parameter, in Matlab, VC++ supervisor, can complete setting by coding code, thereby this software could be by the parameter of routine call Lookup protocol simulation waveform.
Power supply: input 220V alternating voltage, output ± 5V, ± 15V or 3.3V DC voltage, for whole system work.
RS232 interface: its corresponding interface circuit is completed by MAX232 chip, can communicate by serial interconnection line and host computer.
Clock: the clock of mainly supplying with fpga chip is used, because the high output signal frequency of system is 10M, according to being Qwest's sampling law, half that the highest output frequency is system clock, adopts 50M crystal oscillator can meet the demands completely herein.
SDRAM storer: carry out high-speed read-write for storing data.
SDRAM circuit on fpga chip is for providing Nios II memory headroom and the storing high-speed data of soft core operation.
EPCS series serial Flash configuring chip: be used for preserving the configuration file of FPGA, guarantee FPGA power on after the loading of program.
EPCS circuit on fpga chip adopts the EPCS16 chip of altera corp, for preserving the configuration file of FPGA, and after reset, automatically program code is copied in SDRAM from EPCS.
The effect of PIO controller is middle controller: because fpga chip is controlled IO mouth unlike common single-chip microcomputer, therefore needing PIO controller to come the function of the common IO mouth on analogy single-chip microcomputer, the setting of No. one, No. two PIO controller is in order to illustrate that Nios II soft-core processor will control the just essential such middle controller of other circuit.
DA converter circuit: referring to Fig. 2, adopt the cooperative structure of two-stage DA chip, utilize a serial high precision DA as the reference source of another one high-speed D/A converters, greatly improved precision in system dynamic adjustments amplitude process, reduced noise, reduced error.Generally speaking, amplitude regulates and can realize by the amplitude size of direct modification waveform ROM table, but this method can only realize the adjusting of amplitude when larger, and amplitude hour, in this way with regard to out of true.For this reason, the present invention adopts the cooperative design of two-stage DA chip in DA converter circuit, this design adopts hardware to realize high-precision amplitude and regulates, reference voltage with the output voltage of the high-precision low speed DA of a slice converter as high-speed D/A converters, when less output voltage, magnitude of voltage corresponding to each resolution is less, be convenient in amplitude hour, amplitude be regulated, thereby improved the precision of system.
Signal conditioning circuit: comprise fixed gain amplifier, LC wave filter, three parts of power amplifier, the signal of exporting due to DA converter circuit is 2Vpp, need to increase fixed gain and be 5 amplifier, it is 20M that LC wave filter arranges cutoff frequency, the high order noise of filtering appts, power amplification circuit increases the fan-out capability of electric current, and guarantees that output signal is not because the variation of load changes.
Ethernet interface: comprise network transformer and ethernet control chip, it can identify each instrument by different ID by this kind of signal generator access to LAN, can accept data by network, realizes network control.
Embodiment 1:
Half signal generator in kind, comprises host computer 1 and at least one slave computer 2, is mounted with Waveform Design simulation software on host computer 1, and slave computer 2 comprises fpga chip 3, DA converter circuit 9 and signal conditioning circuit 10, be connected with serial FLASH 4 on fpga chip 3, RS232 interface 5, power supply 11, SDRAM storer 6, clock 12 and Ethernet interface 13, fpga chip 3 is embedded with Nios II soft-core processor 7, DDS module 8, dual port RAM 14 and frequency control word register 15, Nios II soft-core processor 7 comprises CPU processor 71, URAT controller 72, sdram controller 73, EPCS controller 74, ethernet controller 75, a PIO controller 76 and No. two PIO controllers 77, CPU processor 71 is by URAT controller 72, sdram controller 73, EPCS controller 74, ethernet controller 75 respectively with RS232 interface 5, SDRAM storer 6, serial FLASH 4, Ethernet interface 13 communication connections, RS232 interface 5, the other end of Ethernet interface 13 all with host computer 1 communication connection, CPU processor 71 is connected with dual port RAM 14 by a PIO controller 76, the other end of dual port RAM 14 respectively with DDS module 8, DA converter circuit 9 is connected, and the other end of DDS module 8 is successively by frequency control word register 15, No. two PIO controller 77 is connected with CPU processor 71, and the other end of DA converter circuit 9 is connected with signal conditioning circuit 10.Described DA converter circuit 9 comprises a high-speed D/A converters 91 and a low-speed highly precise DA converter 92, one end of high-speed D/A converters 91 is connected with dual port RAM 14, the other end is connected with signal conditioning circuit 10, one end of low-speed highly precise DA converter 92 is connected with dual port RAM 14, and the other end is as the reference source input of high-speed D/A converters 91.Described signal conditioning circuit 10 comprises fixed gain amplifier, LC wave filter and power amplifier, and this fixed gain amplifier is connected with the other end of high-speed D/A converters 91.
A using method for above-mentioned half signal generator in kind, this using method comprises the following steps successively:
The first step: first the Waveform Design simulation software of host computer 1 interior loading is arranged, its method to set up comprises that interface manually arranges and routine call Lookup protocol, and it arranges content and comprises: communication port, signal type, amplitude, frequency, phase place and low and high level; Described communication port comprises RS232 interface 5 or Ethernet interface 13, and described signal type comprises sine wave, triangular wave and the square wave in reference waveform;
Described computing and the modulation that content also comprises signal be set, its method to set up is: first complete the setting of two groups of signals, then Selecting operation mode, this compute mode comprises and adding, subtracts, multiplication and signal modulation, then determine, get final product the computing of end signal and the setting of modulation;
When adopting the manual set-up mode in interface, its signal type also comprises random waveform, and the set-up mode of this random waveform is: first open waveform drawing panel, then with the mouse waveform that manual drawing is wanted in waveform drawing panel, then clicked, can finish the setting of random waveform;
The maximal value of described amplitude is 5V, and frequency is 0.1Hz – 10MHz;
Second step: above-mentioned setting after end of text, on the screen of host computer 1, demonstrate simulation waveform again, if the simulation waveform showing meets the requirements, Ze Yougai Waveform Design simulation software generates the required module parameter of DDS module 8 in slave computer 2, this module parameter comprises waveform ROM table data, phase accumulator initial value and amplitude control signal, then by RS232 interface 5 or Ethernet interface 13, this module parameter is sent to slave computer 2;
The 3rd step: first switch on power 11, by 4 pairs of fpga chips 3 of serial FLASH, be configured again, and Nios II soft-core processor 7 is carried out to program loading, then by Nios II soft-core processor 7, by RS232 interface 5 or Ethernet interface 13, receive the module parameter that host computer 1 sends, and this module parameter is deposited in SDRAM storer 6, by CPU processor 71, carry out computing again, then the digital signal of computing gained is deposited in dual port RAM 14, and coordinate this digital signal is passed to DA converter circuit 9 with DDS module 8, by DA converter circuit 9, this digital signal is converted to simulating signal again, then by signal conditioning circuit 10, processed, now can obtain final signal.
Therefore not only degree of accuracy is higher in the present invention, intuitive is strong, production cost is lower, and automaticity is higher, range of application is wider.
Claims (7)
1. one and half signal generators in kind, comprise interconnective host computer (1) and slave computer (2), described slave computer (2) comprises fpga chip (3) and DA converter circuit (9), one end of fpga chip (3) and host computer (1) communication connection, the other end is connected with DA converter circuit (9), and on fpga chip (3), be connected with power supply (11), serial FLASH (4) and clock (12), it is characterized in that:
Described host computer is mounted with Waveform Design simulation software on (1), and the quantity of described slave computer (2) is at least one, and slave computer (2) also comprises signal conditioning circuit (10); On described fpga chip (3), be also connected with RS232 interface (5), Ethernet interface (13) and SDRAM storer (6), and in fpga chip (3), be provided with Nios II soft-core processor (7), DDS module (8), dual port RAM (14) and frequency control word register (15);
Described Nios II soft-core processor (7) comprises CPU processor (71), URAT controller (72), sdram controller (73), EPCS controller (74), ethernet controller (75), a PIO controller (76) and No. two PIO controllers (77), CPU processor (71) is by URAT controller (72), sdram controller (73), EPCS controller (74), ethernet controller (75) respectively with RS232 interface (5), SDRAM storer (6), serial FLASH (4), Ethernet interface (13) communication connection, RS232 interface (5), the other end of Ethernet interface (13) all with host computer (1) communication connection, CPU processor (71) is connected with dual port RAM (14) by a PIO controller (76), the other end of dual port RAM (14) respectively with DDS module (8), DA converter circuit (9) is connected, and the other end of DDS module (8) is successively by frequency control word register (15), No. two PIO controllers (77) are connected with CPU processor (71), and the other end of DA converter circuit (9) is connected with signal conditioning circuit (10),
Described DA converter circuit (9) comprises a high-speed D/A converters (91) and a low-speed highly precise DA converter (92), one end of high-speed D/A converters (91) is connected with dual port RAM (14), the other end is connected with signal conditioning circuit (10), one end of low-speed highly precise DA converter (92) is connected with dual port RAM (14), and the other end is as the reference source input of high-speed D/A converters (91).
2. a kind of half signal generator in kind according to claim 1, is characterized in that: described host computer (1) is PC, and described fpga chip (3) adopts Cyclone, Cyclone II or the Cyclone III family chip of altera corp.
3. a kind of half signal generator in kind according to claim 1 and 2, it is characterized in that: described signal conditioning circuit (10) comprises fixed gain amplifier, LC wave filter and power amplifier, this fixed gain amplifier is connected with the other end of high-speed D/A converters (91).
4. a using method for half signal generator in kind claimed in claim 1, is characterized in that this using method comprises the following steps successively:
The first step: first the Waveform Design simulation software loading in host computer (1) is arranged, its method to set up comprises that interface manually arranges and routine call Lookup protocol, and it arranges content and comprises: communication port, signal type, amplitude, frequency, phase place and low and high level; Described communication port comprises RS232 interface (5) or Ethernet interface (13), and described signal type comprises sine wave, triangular wave and the square wave in reference waveform;
Second step: above-mentioned setting after end of text, on the screen of host computer (1), demonstrate simulation waveform again, if the simulation waveform showing meets the requirements, Ze Yougai Waveform Design simulation software generates the required module parameter of DDS module (8) in slave computer (2), this module parameter comprises waveform ROM table data, phase accumulator initial value and amplitude control signal, then by RS232 interface (5) or Ethernet interface (13), this module parameter is sent to slave computer (2);
The 3rd step: (11) first switch on power, by serial FLASH (4), fpga chip (3) is configured again, and Nios II soft-core processor (7) is carried out to program loading, then by Nios II soft-core processor (7), by RS232 interface (5) or Ethernet interface (13), receive the module parameter that host computer (1) sends, and this module parameter is deposited in SDRAM storer (6), by CPU processor (71), carry out computing again, then the digital signal of computing gained is deposited in dual port RAM (14), and coordinate this digital signal is passed to DA converter circuit (9) with DDS module (8), by DA converter circuit (9), this digital signal is converted to simulating signal again, then by signal conditioning circuit (10), processed, now can obtain final signal.
5. the using method of a kind of half signal generator in kind according to claim 4, it is characterized in that: in the described first step computing and the modulation that content also comprises signal be set, its method to set up is: first complete the setting of two groups of signals, Selecting operation mode again, this compute mode comprises and adding, subtracts, the modulation of multiplication and signal, then determine, can the computing of end signal and the setting of modulation.
6. according to the using method of a kind of half signal generator in kind described in claim 4 or 5, it is characterized in that: in the described first step, when adopting the manual set-up mode in interface, its signal type also comprises random waveform, the set-up mode of this random waveform is: first open waveform drawing panel, with the mouse waveform that manual drawing is wanted in waveform drawing panel, then clicked again, can finish the setting of random waveform.
7. according to the using method of a kind of half signal generator in kind described in claim 4 or 5, it is characterized in that: in the described first step, the maximal value of amplitude is 5V, frequency is 0.1Hz – 10MHz.
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