CN203707129U - Base plate configuration structure of diode assemblies - Google Patents
Base plate configuration structure of diode assemblies Download PDFInfo
- Publication number
- CN203707129U CN203707129U CN201320762233.6U CN201320762233U CN203707129U CN 203707129 U CN203707129 U CN 203707129U CN 201320762233 U CN201320762233 U CN 201320762233U CN 203707129 U CN203707129 U CN 203707129U
- Authority
- CN
- China
- Prior art keywords
- base plate
- hole
- copper sheet
- copper
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000000712 assembly Effects 0.000 title abstract description 4
- 238000000429 assembly Methods 0.000 title abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 40
- 229910052802 copper Inorganic materials 0.000 claims abstract description 40
- 239000010949 copper Substances 0.000 claims abstract description 40
- 239000003822 epoxy resin Substances 0.000 claims abstract description 5
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 5
- 239000000084 colloidal system Substances 0.000 claims abstract description 4
- 239000011521 glass Substances 0.000 claims description 11
- 238000005553 drilling Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 4
- 229910000881 Cu alloy Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000011469 building brick Substances 0.000 description 3
- 239000003292 glue Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model discloses a base plate configuration structure of diode assemblies. The base plate configuration structure comprises a base plate; the base plate is provided with a plurality of through holes with equal intervals; the inner wall of each through hole is plated with a copper layer; each through hole is filled with colloid; upper and lower surfaces of the base plate at the position of each through hole are both provided with copper sheets conducted with the copper layer; one end of each upper copper sheet on the upper surface of the base plate is provided with a chip, and the other end of each copper sheet is connected with the chip of the prior upper copper sheet through a bonding wire; and the base plate is also provided with an epoxy resin layer used for wrapping the upper copper sheets, the chips and the bonding wires. By adoption of the base plate configuration structure of the diode assemblies, each through hole is cut up along the longitudinal axis when the base plate is cut, one through hole can be respectively used as terminal electrodes for two independent diodes, the number of drilling is largely reduced, and drilling cost is reduced.
Description
Technical field
The utility model has related to a kind of base plate arrangement of diode assembly, belongs to electronic building brick encapsulation technology field.
Background technology
The electronic building brick base plate that at present industry is used is mainly these two kinds of copper alloy plate and glass mats, the electronic building brick that wherein copper alloy plate is done in technique comparatively complexity and yield lower, technique is comparatively simple and yield is higher to use glass mat, on manufacturing process station copper alloy processing procedure many go to overflow glue and whole pin position, to electroplate processing procedure station, termination electrode Deng San road other.
On same process station, on bonding wire processing procedure, should be noted the problem of copper coin spring and framework deformation, need to stick heat resistant adhesive tape must exempt from the problem of excessive glue at the first day of the lunar month envelope processing procedure station, should be noted that at cutting processing procedure station the rear copper of cutting extends and the problem of distortion.
Therefore main flow is to use glass mat electrogenesis in next life sub-component as main, less because of making technology station at present, in the benefit of production, can provide to some extent, the technique station human cost that also representative is used less reduces, yield can effectively promote.
But the cost of glass mat is expensive many compared with copper coin, wherein FR4 plate maximum cost on making is boring, because of glass mat itself non-conductive, therefore need hole on each termination electrode, the DFN1006 diode of a slice 60mm x 90mm just need to get into 9240 holes, calculate with 0.001 yuan, each hole, its cost is 9.625 yuan, therefore boring accounts for the cost of glass mat maximum.
Yield when grinding evenness after the accuracy of boring and boring involves the production of assembly factory especially, because the termination electrode of DFN1006 is 0.35mm*0.5mm to the maximum, therefore the aperture of boring need be less than 0.15mm and side-play amount up and down need be less than 0.03mm, otherwise can produce holes phenomenon, holes plate is invalid plate in assembly factory.
Grinding evenness after boring can directly be reacted on the yield of the bonding wire station of assembly factory, bonding wire station thus Ming Siyi exactly guide line (gold, silver, copper, aluminium) is agreed with (stickup) on substrate to reach the function of conduction, if problem will produce off-line, line simulator, broken string when substrate surface out-of-flatness in bonding wire process time, causes reduction and the qualitative unsteadiness of production efficiency.
Though therefore at present industry is known technologic advantage while using glass mat to produce, most assembly factories or take copper coin as main, so at present on glass mat this how to found technique be the target that current industry need overcome jointly with improving yield.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of base plate arrangement of diode assembly, can effectively reduce drilling hole amount, reduces production costs, and promotes yield.
In order to solve the problems of the technologies described above, the technical scheme that the utility model adopts is:
A kind of base plate arrangement of diode assembly, comprise base plate, described base plate equal intervals is provided with multiple through holes, the inwall of described through hole is coated with copper layer, in described through hole, plug is filled with colloid, the upper and lower surface of the base plate of described through hole is provided with the copper sheet with the conducting of described copper layer, in every a slice of described plate upper surface, one end of copper sheet is provided with chip, the other end is connected with the chip of previous upper copper sheet by bonding wire, is also provided with the epoxy resin layer for wrapping up described upper copper sheet, chip, bonding wire on described base plate.
The base plate arrangement of aforesaid a kind of diode assembly, is characterized in that: described base plate is glass mat.
The base plate arrangement of aforesaid a kind of diode assembly, is characterized in that: described chip is fixedly connected with described upper copper sheet by conducting resinl.
The base plate arrangement of aforesaid a kind of diode assembly, is characterized in that: the diameter of described through hole is 0.3mm-0.4mm.
The beneficial effects of the utility model are:
1, adopt the base plate of the diode assembly of the present utility model mechanism that arranges, in the time of cutting, cut from through hole longitudinal axis, a through hole is used as termination electrode by two independent diodes respectively, greatly reduced boring number, reduced boring cost;
2, the aperture of through hole increases, and is convenient on hole wall copper facing and in through hole, fills in filler body, easily controls;
3, because through hole is positioned on Cutting Road, therefore without too smooth, because position is for this reason can be removed in assembly factory technique;
4,, because the position of through hole has been moved relatively afterwards, therefore in the time of etch component circuit, can amplify and change circuit, be no longer limited to hole and evenness.
Accompanying drawing explanation
Fig. 1 is the structural representation after the base plate hole clipping, copper facing, plug glue of the base plate arrangement of a kind of diode assembly of the utility model;
Fig. 2 is the structural representation of the base plate arrangement of a kind of diode assembly of the utility model when epoxy resin layer is not set;
Fig. 3 is the perspective view of the single diode package after the base plate arrangement of a kind of diode assembly of the utility model is cut open.
Embodiment
Below in conjunction with Figure of description, the utility model is further described.
As shown in Figure 1-Figure 3, a kind of base plate arrangement of diode assembly, comprise base plate 1, described base plate 1 equal intervals is provided with multiple through holes, the inwall of described through hole is coated with copper layer 2, in described through hole, plug is filled with colloid 3, the upper and lower surface of the base plate 1 of described through hole is provided with the copper sheet with described copper layer 2 conducting, in every a slice of described base plate 1 upper surface, one end of copper sheet 4 is provided with chip 6, the other end is connected with the chip 6 of previous upper copper sheet 4 by bonding wire 7, on described base plate 1, be also provided with for wrapping up described upper copper sheet 4, chip 6, the epoxy resin layer 8 of bonding wire 7, wherein going up copper sheet 4 is conducted with lower copper sheet 5 by the copper layer 2 of through-hole wall.
In when cutting, from cut the through hole of each, just form independent one by one diode assembly, because each through hole is used as termination electrode by two independent diode assemblies respectively, thereby greatly reduce boring number, reduce boring cost.Because through hole is positioned on Cutting Road, therefore without too smooth, because position is for this reason can be removed in assembly factory technique; And because having moved relatively afterwards the position of through hole, therefore in the time of etch component circuit, can amplify and change circuit, be no longer limited to hole and evenness.
Described base plate 1 is glass mat, can effectively reduce manufacturing process, improves productivity effect, has reduced labor cost, and yield also can effectively promote.
Described chip 6 is fixedly connected with described upper copper sheet 4 by conducting resinl, has realized the conducting of chip 6 with upper copper sheet 4.
The diameter of described through hole is 0.3mm-0.4mm, and the through-hole diameter that the utility model adopts is 0.35mm, and with respect to the aperture of existing 0.15mm, the aperture of through hole increases, and is convenient on hole wall copper facing and in through hole, fills in filler body, easily controls.
In sum, the base plate arrangement of a kind of diode assembly that the utility model provides, can effectively reduce drilling hole amount, reduces production costs, and promotes yield.
More than show and described basic principle of the present utility model, principal character and advantage.The technical staff of the industry should understand; the utility model is not restricted to the described embodiments; that in above-described embodiment and specification, describes just illustrates principle of the present utility model; do not departing under the prerequisite of the utility model spirit and scope; the utility model also has various changes and modifications, and these changes and improvements all fall within the scope of claimed the utility model.The claimed scope of the utility model is by appending claims and equivalent circle thereof.
Claims (4)
1. the base plate arrangement of a diode assembly, comprise base plate (1), it is characterized in that: described base plate (1) equal intervals is provided with multiple through holes, the inwall of described through hole is coated with copper layer (2), in described through hole, plug is filled with colloid (3), the upper and lower surface of the base plate (1) of described through hole is provided with the copper sheet with described copper layer (2) conducting, in every a slice of described base plate (1) upper surface, one end of copper sheet (4) is provided with chip (6), the other end is connected with the chip (6) of previous upper copper sheet (4) by bonding wire (7), on described base plate (1), be also provided with for wrapping up described upper copper sheet (4), chip (6), the epoxy resin layer (8) of bonding wire (7).
2. the base plate arrangement of a kind of diode assembly according to claim 1, is characterized in that: described base plate (1) is glass mat.
3. the base plate arrangement of a kind of diode assembly according to claim 1 and 2, is characterized in that: described chip (6) is fixedly connected with described upper copper sheet (4) by conducting resinl.
4. the base plate arrangement of a kind of diode assembly according to claim 3, is characterized in that: the diameter of described through hole is 0.3mm-0.4mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320762233.6U CN203707129U (en) | 2013-11-28 | 2013-11-28 | Base plate configuration structure of diode assemblies |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320762233.6U CN203707129U (en) | 2013-11-28 | 2013-11-28 | Base plate configuration structure of diode assemblies |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203707129U true CN203707129U (en) | 2014-07-09 |
Family
ID=51057528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320762233.6U Expired - Lifetime CN203707129U (en) | 2013-11-28 | 2013-11-28 | Base plate configuration structure of diode assemblies |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203707129U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110970329A (en) * | 2019-11-27 | 2020-04-07 | 丽智电子(昆山)有限公司 | Method for preparing crystal diode based on soluble protective film |
-
2013
- 2013-11-28 CN CN201320762233.6U patent/CN203707129U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110970329A (en) * | 2019-11-27 | 2020-04-07 | 丽智电子(昆山)有限公司 | Method for preparing crystal diode based on soluble protective film |
| CN110970329B (en) * | 2019-11-27 | 2024-03-29 | 丽智电子（南通）有限公司 | Method for preparing transistor diode based on soluble protective film |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140709 |