CN203659843U - Double-tabletop silicon controlled rectifier (SCR) device packaging structure - Google Patents
Double-tabletop silicon controlled rectifier (SCR) device packaging structure Download PDFInfo
- Publication number
- CN203659843U CN203659843U CN201320823589.6U CN201320823589U CN203659843U CN 203659843 U CN203659843 U CN 203659843U CN 201320823589 U CN201320823589 U CN 201320823589U CN 203659843 U CN203659843 U CN 203659843U
- Authority
- CN
- China
- Prior art keywords
- scr
- tabletop
- double
- table top
- wire frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 39
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 28
- 239000010703 silicon Substances 0.000 title claims abstract description 28
- 238000004806 packaging method and process Methods 0.000 title abstract 4
- 229910000679 solder Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 10
- 238000003466 welding Methods 0.000 claims description 5
- 230000000903 blocking effect Effects 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 abstract description 3
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 abstract 4
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 238000005538 encapsulation Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model discloses a double-tabletop silicon controlled rectifier (SCR) device packaging structure. The packaging structure sequentially comprises a double-tabletop SCR chip, a soft solder and a wire frame pedestal. The lower surface of the double-tabletop SCR chip is provided with a weldable metal piece. The soft solder is arranged between the weldable metal piece and the wire frame pedestal on the lower surface of the double-tabletop SCR chip. The upper surface of the wire frame pedestal is provided with a groove structure. The groove structure is used for storing the excess soft solder. According to the technical scheme of the utility model, the upper surface of the wire frame pedestal is provided with the groove structure. The groove is arranged to surround the double-tabletop SCR chip and is used for storing the excess soft solder. In this way, the excess soft solder is prevented from flowing into the tabletops of the SCR to cause the breakdown phenomenon on the surface of the device. Therefore, the degradation of the reverse blocking capability of the double-tabletop SCR device is effectively avoided. Meanwhile, the packaging yield of double-tabletop SCR devices is also improved.
Description
Technical field
The utility model relates to a kind of two table top silicon-controlled device encapsulating structure, belongs to power semiconductor encapsulation technology field.
Background technology
It is low that slicken solder has good wettability and solderability and welding temperature, is therefore widely used in Plastic Package large power semiconductor device process for assembling and welding.But in two table top silicon-controlled device assembling process of employing slicken solder; situation about often occurring is: the good mobility of slicken solder usually can cause too much slicken solder to flow to the table top place of controlled silicon chip; cause silicon-controlled device surface breakdown; the reverse blocking capability of the two table top silicon-controlled devices of infringement; serious two table top silicon-controlled devices that also can cause burn inefficacy, and this becomes a major issue of the two table top silicon-controlled device packaging technology reliabilities of restriction.Therefore, need to provide a kind of new technical scheme to solve the problems referred to above.
Utility model content
For addressing the above problem, the utility model provides a kind of two table top silicon-controlled device encapsulating structure.Can effectively improve two table top silicon-controlled device encapsulation rate of finished productss and reliability.
The technical solution adopted in the utility model is:
A kind of two table top silicon-controlled device encapsulating structure, this encapsulating structure comprises two table top controlled silicon chips, slicken solder and wire frame base from top to bottom successively, described pair of table top controlled silicon chip lower surface is provided with and can supplies the metal of welding, described slicken solder be arranged on two table top controlled silicon chip lower surfaces can weld metal and wire frame base between, the upper surface of described wire frame base is provided with groove structure, and described groove structure is for storing excessive slicken solder.
Described groove structure is the groove around two table top controlled silicon chips.
The beneficial effects of the utility model: the utility model is provided with groove at the upper surface of wire frame base, groove is around two table top controlled silicon chips, groove can be for storing excessive slicken solder, prevent from causing that device surface punctures in excessive slicken solder inflow silicon controlled table top, thereby can effectively avoid two table top silicon-controlled device reverse blocking capabilities to degenerate, improve two table top silicon-controlled device encapsulation rate of finished productss.
Brief description of the drawings
Fig. 1 is structural representation of the present utility model.
Fig. 2 is the utility model groove structure schematic diagram.
Wherein: 1, two table top controlled silicon chips, 2, metal, 3, slicken solder, 4, groove, 5, wire frame base.
Embodiment
In order to deepen understanding of the present utility model, below in conjunction with embodiment and accompanying drawing, the utility model is described in further detail, and this embodiment only, for explaining the utility model, does not form the restriction to protection range of the present utility model.
As illustrated in fig. 1 and 2, the two table top silicon-controlled device encapsulating structures of one of the present utility model, this encapsulating structure comprises two table top controlled silicon chips 1, slicken solder 3 and wire frame base 5 from top to bottom successively, two table top controlled silicon chip 1 lower surfaces are provided with can be for the metal 2 of welding, slicken solder 3 be arranged on two table top controlled silicon chip 1 lower surfaces can weld metal 2 and wire frame base 5 between, the upper surface of wire frame base 5 is provided with groove structure, groove structure is for storing excessive slicken solder 3, and groove structure is the groove 4 around two table top controlled silicon chips 1.
The utility model is made a groove 4 in the time making sealing wire frame on wire frame base, the two table top controlled silicon chips of the interior rectangle Area Ratio of groove 4 can be bigger for weld metal area, groove 4 width and be highly moderately advisable can hold lower excess solder material 3, when assembling, groove 4 is positioned at the wire frame base 5 in outside under two table top controlled silicon chips 1.
The utility model is provided with groove 4 at the upper surface of wire frame base, groove 4 is around two table top controlled silicon chips 1, groove 4 can be for storing excessive slicken solder 3, preventing that excessive slicken solder 3 from flowing in silicon controlled table top causes that device surface punctures, thereby can effectively avoid two table top silicon-controlled device reverse blocking capabilities to degenerate, improve two table top silicon-controlled device encapsulation rate of finished productss.
Claims (2)
1. a two table top silicon-controlled device encapsulating structure, it is characterized in that: this encapsulating structure comprises two table top controlled silicon chips, slicken solder and wire frame base from top to bottom successively, described pair of table top controlled silicon chip lower surface is provided with and can supplies the metal of welding, described slicken solder be arranged on two table top controlled silicon chip lower surfaces can weld metal and wire frame base between, the upper surface of described wire frame base is provided with groove structure, and described groove structure is for storing excessive slicken solder.
2. the two table top silicon-controlled device encapsulating structures of one according to claim 1, is characterized in that: described groove structure is the groove around two table top controlled silicon chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320823589.6U CN203659843U (en) | 2013-12-16 | 2013-12-16 | Double-tabletop silicon controlled rectifier (SCR) device packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320823589.6U CN203659843U (en) | 2013-12-16 | 2013-12-16 | Double-tabletop silicon controlled rectifier (SCR) device packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203659843U true CN203659843U (en) | 2014-06-18 |
Family
ID=50926204
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320823589.6U Expired - Lifetime CN203659843U (en) | 2013-12-16 | 2013-12-16 | Double-tabletop silicon controlled rectifier (SCR) device packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203659843U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104064533A (en) * | 2014-07-03 | 2014-09-24 | 江苏东光微电子股份有限公司 | QFN packaging structure and method for double-face semiconductor device |
-
2013
- 2013-12-16 CN CN201320823589.6U patent/CN203659843U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104064533A (en) * | 2014-07-03 | 2014-09-24 | 江苏东光微电子股份有限公司 | QFN packaging structure and method for double-face semiconductor device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 226200 1800 Mudanjiang West Road, Huilong Town, Qidong City, Nantong City, Jiangsu Province Patentee after: Jiangsu Jilai Microelectronics Co.,Ltd. Address before: 226200 1261 Gongyuan North Road, Huilong Town, Qidong City, Nantong City, Jiangsu Province Patentee before: QIDONG JILAI ELECTRONICS Co.,Ltd. |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140618 |