CN203631560U - Bipolar NPN transistor - Google Patents
Bipolar NPN transistor Download PDFInfo
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- CN203631560U CN203631560U CN201320815662.5U CN201320815662U CN203631560U CN 203631560 U CN203631560 U CN 203631560U CN 201320815662 U CN201320815662 U CN 201320815662U CN 203631560 U CN203631560 U CN 203631560U
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Abstract
The utility model provides a bipolar NPN transistor which comprises a substrate; an epitaxial layer formed on the substrate; adeep phosphorous zone, a base zone, a collecting zone and an emitting zone formed in the epitaxial layer; a first interlayer dielectric layer and a voltage modulation dielectric layer formed on the epitaxial layer; a first interconnection line formed on the first interlayer dielectric layer and the voltage modulation dielectric layer; a second interlayer dielectric layer formed on the first interlayer dielectric layer and the first interconnection line; and a second interconnection line formed on the second interlayer dielectric layer. The voltage modulation dielectric layer covers the base zone and is electrically led out through the first interconnection line. According to the utility model, the voltage modulation dielectric layer is formed above the base zone, and the voltage modulation dielectric layer is led out through the first interconnection line, so that by changing the quantity of induced charges of the voltage modulation dielectric layer, the charge concentration on the surface of the base zone is changed, and the adjustable amplification factor of a low current is realized.
Description
Technical field
The utility model relates to integrated circuit and manufactures field, particularly a kind of bipolar PNP transistor.
Background technology
Photoelectric sensor is a kind of transducer that by light-sensitive device, light signal is converted to the signal of telecommunication.Light-sensitive device generally adopts semiconductor technology manufacture at present, comprises photodiode, phototriode and photo resistance etc.Because the light ratio that light-sensitive device receives is fainter, so the photogenerated current producing is also fainter, conventionally need a pre-amplification circuit to coordinate with amplifying signal with light-sensitive device.Light-sensitive device and pre-amplification circuit are integrated on chip piece, form photoelectric sensor.
Along with the difference of photoelectric sensor application scenario, all kinds of environmental interference are very large on the impact of light-sensitive device, as Switching Power Supply, surround lighting etc.The electric current that environmental interference produces can affect the sensitivity of light-sensitive device.Pre-amplification circuit will be adjusted to suitable amplification coefficient, to weaken the impact of environmental interference on light-sensitive device, thereby makes photoelectric sensor meet application requirements.Pre-amplification circuit is made up of transistor, and transistorized power dissipation characteristics in leakage current region comprises that bipolar NPN transistor and the transistorized power dissipation characteristics in leakage current region of bipolar PNP are all most important for technique adjustment.
Adopt bipolar process to carry out photoelectric sensor chip design and technique manufacture, because the laying out pattern of bipolar process can bring ghost effect, in order to export the photosignal of large as far as possible signal to noise ratio, need in manufacture process, carry out repeatedly laying out pattern adjustment and process debugging, to seek the optimum Match of light-sensitive device and pre-amplification circuit, thereby adapt to the application requirements under varying environment.
Adopt the bipolar PNP transistor of existing bipolar process manufacturing, the little current amplification factor fluctuation ratio of its output is larger, even if through process optimization, little current fluctuation is reduced, but the central value of little current amplification factor is immutable, therefore cannot meet the application requirements under varying environment.The scope of the collector current that wherein, little electric current amplifies is generally at 10nA～100nA.
Based on this, how improving the nonadjustable problem of the transistorized little current amplification factor of bipolar PNP in prior art has become those skilled in the art and has needed badly the technical problem of solution.
Utility model content
The purpose of this utility model is to provide a kind of bipolar PNP transistor, to solve the nonadjustable problem of the transistorized little current amplification factor of existing bipolar PNP.
For solving the problems of the technologies described above, the utility model provides a kind of bipolar PNP transistor, and described bipolar PNP transistor comprises: substrate; Be formed at the epitaxial loayer on described substrate; Be formed at described epitaxial loayer Zhong Shenlin district, base, collector region and emitter region; Be formed at the first interlayer dielectric layer and voltage modulation dielectric layer on described epitaxial loayer; Be formed at the first interconnection line on described the first interlayer dielectric layer and voltage modulation dielectric layer; Be formed at the second interlayer dielectric layer on described the first interlayer dielectric layer and the first interconnection line; Be formed at the second interconnection line on described the second interlayer dielectric layer; Wherein, described voltage modulation dielectric layer is covered on described base, and is realized and electrically being drawn by described the first interconnection line.
Preferably, in described bipolar PNP transistor, described collector region is surrounded on described base, and described base ring is around in described emitter region; Described the first interconnection line is connected with described Shen Lin district, emitter region and collector region, for realizing electrically drawing of described Shen Lin district and collector region; Described the second interconnection line is connected with the first interconnection line above described emitter region, for realizing electrically drawing of described emitter region.
Preferably, in described bipolar PNP transistor, described voltage modulation dielectric layer comprises silicon dioxide layer and silicon nitride layer; Described silicon dioxide layer is positioned at below described silicon nitride layer, described the first interconnection line be covered in described silicon nitride layer above.
Preferably, in described bipolar PNP transistor, the thickness of described silicon dioxide layer is 150～800 dusts, and the thickness of described silicon nitride layer is 300 dust～1800 dusts.
Preferably, in described bipolar PNP transistor, the thickness of described epitaxial loayer is 2.5 μ m～4 μ m, and the resistivity of described epitaxial loayer is 1.0 Ω cm～2.2 Ω cm.
Preferably, in described bipolar PNP transistor, also comprise: be formed at buried regions and lower isolated area between described substrate and epitaxial loayer; Described lower isolated area is around described buried regions, and described Shen Lin district is connected with described buried regions.
Preferably, in described bipolar PNP transistor, also comprise: be formed at the upper isolated area in epitaxial loayer; Described upper isolated area is connected with described lower isolated area.
Preferably, in described bipolar PNP transistor, also comprise: be formed at the lightly-doped layer of described epi-layer surface, the high order of magnitude of concentration of the concentration ratio epitaxial loayer of described lightly-doped layer.
Preferably, in described bipolar PNP transistor, the doping type of described substrate, lower isolated area, upper isolated area, emitter region and collector region is P type, and the doping type of described epitaxial loayer, buried regions, lightly-doped layer, Shen Lin district and base is N-type.
Preferably, in described bipolar PNP transistor, also comprise: be formed at the passivation layer on described the second interlayer dielectric layer and the second interconnection line.
In the bipolar PNP transistor providing at the utility model, above base, form voltage modulation dielectric layer, described voltage modulation dielectric layer is realized and electrically being drawn by the first interconnection line, so, can make the concentration of electric charges of base region surface change by the charge inducing quantity that changes voltage modulation dielectric layer, thereby it is adjustable to realize little current amplification factor.
Brief description of the drawings
Fig. 1 is the schematic flow sheet of the transistorized manufacture method of bipolar PNP of the utility model one embodiment;
Fig. 2 to Figure 13 is the structural representation of the device of the each step of the transistorized manufacture method of bipolar PNP of the utility model one embodiment.
Embodiment
Below in conjunction with the drawings and specific embodiments, the bipolar PNP transistor the utility model proposes is described in further detail.According to the following describes and claims, advantage of the present utility model and feature will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of aid illustration the utility model embodiment lucidly.
Please refer to Figure 13, it is the transistorized structural representation of bipolar PNP of the utility model embodiment.As shown in figure 13, described bipolar PNP transistor 100 comprises: substrate 10; Be formed at the epitaxial loayer 13 on described substrate 10; Be formed at described epitaxial loayer 13 Zhong Shenlin districts 14, base 16, collector region 17 and emitter region 18; Be formed at the first interlayer dielectric layer 19 and voltage modulation dielectric layer 20 on described epitaxial loayer 13; Be formed at the first interconnection line 21 on described the first interlayer dielectric layer 19 and voltage modulation dielectric layer 20; Be formed at the second interlayer dielectric layer 22 on described the first interlayer dielectric layer 19 and the first interconnection line 21; Be formed at the second interconnection line 23 on described the second interlayer dielectric layer 22; Wherein, described voltage modulation dielectric layer 20 is formed on described base 16, and is realized electrically and being drawn by described the first interconnection line 21.
Concrete, please continue to refer to Figure 13, in the present embodiment, it is the silicon substrate that P type and crystal orientation are <111> that described substrate 10 adopts doping type, the scope of its resistivity is 10 Ω cm～20 Ω cm.On described substrate 10, be formed with epitaxial loayer 13, the doping type of described epitaxial loayer 13 is N-type, and the scope of its resistivity is 1.0 Ω cm～2.2 Ω cm.The thickness of described epitaxial loayer 13 preferably at 2.5 μ m between 4 μ m, this thickness range can match with the platform of existing little regular bipolar process.
In described epitaxial loayer 13, be formed with Shen Lin district 14, upper isolated area 15, base 16, collector region 17 and emitter region 18, wherein, the doping type of Shen Lin district 14 and described base 16 is N-type, and the doping type of described collector region 17, emitter region 18 and upper isolated area 15 is P type.Described collector region 17 is surrounded on described base 16, and described base 16 is surrounded on described emitter region 18.
Between described substrate 10 and described epitaxial loayer 13, be formed with buried regions 11 and lower isolated area 12, described lower isolated area 12 is surrounded on described buried regions 11.Wherein, the doping type of described buried regions 11 is N-type, and the doping type of described lower isolated area 12 is P type.Described Shen Lin district 14 is connected with described buried regions 11, and described upper isolated area 15 is connected with described lower isolated area 12.Visible, the isolation structure district that described upper isolated area 15 and described lower isolated area 12 are combined to form is surrounded on described buried regions 11 and buried regions 11 Shen Lin district 14, base 16, collector region 17 and emitter region 18 above.
As shown in figure 13, on described epitaxial loayer 13, be formed with the first interlayer dielectric layer 19 and voltage modulation dielectric layer 20, on described the first interlayer dielectric layer 19 and voltage modulation dielectric layer 20, be formed with the first interconnection line 21.Wherein, voltage modulation dielectric layer 20 is positioned at the upper of described base 16 and covers whole base 16, the region of the corresponding described Shen Lin of described the first interlayer dielectric layer 19 district 14, collector region 17 and emitter region 18 is formed with the first contact hole, the first interconnection line 21 is connected with described Shen Lin district 14, collector region 17 and emitter region 18 by the first contact hole, realizes electrically drawing of described Shen Lin district 14 and collector region 17.16 of bases are electrically connected by epitaxial loayer 13He Shenlin district 14 and then with the first interconnection line 21, thereby realize electrically drawing of described base 16.Simultaneously, the region of described the first corresponding described base 14 of interlayer dielectric layer 19 is formed with voltage modulation dielectric layer window, described voltage modulation dielectric layer 20 is formed in described voltage modulation dielectric layer window, and described the first interconnection line 21 is covered on described voltage modulation dielectric layer 20 and realizes voltage and becomes electrically drawing of dielectric layer 20.In the present embodiment, described voltage modulation dielectric layer 20 comprises silicon dioxide layer and silicon nitride layer, and described silicon nitride layer is covered on described silicon dioxide layer, and described the first interconnection line 21 is covered on described silicon nitride layer.Described silicon dioxide layer thickness is 150 dust～800 dusts, and described silicon nitride layer thickness is 300 dust～1800 dusts.
As shown in figure 13, on described the first interlayer dielectric layer 19 and the first interconnection line 21, be formed with the second interlayer dielectric layer 22.On described the second interlayer dielectric layer 22, be formed with the second interconnection line 23, and, described the second interlayer dielectric layer 22 is formed with the second contact hole corresponding to the region of described emitter region 18, described the second interconnection line 23 is connected with the first interconnection line 21 being positioned on emitter region 18 by the second contact hole, realizes electrically drawing of described emitter region 18.
As shown in figure 13, described bipolar PNP transistor 100 also comprises: be formed at the passivation layer 24 on described the second interlayer dielectric layer and the second interconnection line.Described passivation layer 24 is preferably the composite construction of silicon nitride layer or silicon nitride containing layer, described silicon nitride layer can effectively stop extraneous mobile ion, steam etc. to enter voltage modulation dielectric layer 20, can ensure that voltage modulation dielectric layer 20 is not subject to external influence, realize the long-term preservation of charge inducing quantity.
Described bipolar PNP transistor 100 may further include the lightly-doped layer 25 being formed on described epitaxial loayer 13, and the doping type of described lightly-doped layer 25 is N-type.Described lightly-doped layer 25 is positioned at the surface of described epitaxial loayer 13, and its doping content is generally than the high order of magnitude of the doping content of epitaxial loayer 13.The doping content of described lightly-doped layer 25 is generally 1E16cm
-2～4E16cm
-2, its effect is the horizontal proliferation that suppresses collector region 17, emitter region 18 and upper isolated area 15, increases the coverage between collector region 17, emitter region 18 and upper isolated area 15, realizes the transistorized manufacture of small size.Meanwhile, described lightly-doped layer 25 is conducive to improve the parasitic fields cut-in voltage under the first interconnection line in two-layer wiring, to avoid the transistorized normal work of ghost effect impact.
In the bipolar PNP transistor 100 providing at the utility model embodiment, base 16 above be coated with voltage modulation dielectric layer 20, described voltage modulation dielectric layer 20 is realized electrically and being drawn by the first interconnection line 21.Described voltage modulation dielectric layer 20 comprises silicon dioxide layer and is formed at the silicon nitride layer on described silicon dioxide layer.Wherein, the silicon nitride layer of voltage modulation dielectric layer 20 has charge storage ability, intensified negative pressure can reduce the negative electrical charge ratio of silicon nitride layer, strengthen malleation and can recover again the negative electrical charge ratio of silicon nitride layer, therefore strengthen forward and reverse potential pulse by the first interconnection line 21, can change the charge inducing quantity in voltage modulation dielectric layer 20.Meanwhile, because the normal working voltage of PNP pipe is low more than the positive and negative pulse voltage adding on voltage modulation dielectric layer 20, charge inducing quantity can stable for extended periods of time thus.The concentration of electric charges impact of manufacturing the transistorized little current amplification factor of bipolar PNP and be subject to base region surface due to bipolar process, therefore change charge inducing quantity and can make the concentration of electric charges on 16 surfaces, base change, and then changed the electric leakage raceway groove between the transistorized base 16 of bipolar PNP and collector region 17.Visible, by changing the charge inducing quantity in voltage modulation dielectric layer 20, can control the electric leakage raceway groove between base 16 and the collector region 17 of described bipolar PNP transistor 100, change the multiplication factor of bipolar PNP transistor 100 under little electric current.
Accordingly, the bipolar PNP transistor of the present embodiment can be manufactured by the following method formation.Please refer to Fig. 1, and in conjunction with Fig. 2 to Figure 13, the transistorized manufacture method of described bipolar PNP comprises the following steps:
S10 a: substrate 10 is provided;
S11: form epitaxial loayer 13 on described substrate 10;
S12: form successively Shen Lin district 14, base 16, collector region 17 and emitter region 18 in described epitaxial loayer 13;
S13: form successively the first interlayer dielectric layer 19 and voltage modulation dielectric layer 20 on described epitaxial loayer 13;
S14: form the first interconnection line 21 on described the first interlayer dielectric layer 19 and voltage modulation dielectric layer 20;
S15: form the second interlayer dielectric layer 22 on described the first interlayer dielectric layer 19 and the first interconnection line 21;
S16: form the second interconnection line 23 on described the second interlayer dielectric layer 22;
Wherein, described voltage modulation dielectric layer 20 is covered on described base 16, and is realized electrically and being drawn by described the first interconnection line 21.
Concrete, as shown in Figure 2, first, providing a substrate 10, it is the silicon substrate that P type and crystal orientation are <111> that described substrate 10 adopts doping type, the scope of its resistivity is 10 Ω cm～20 Ω cm.
Then, as shown in Figure 3, in described substrate 10, form buried regions 11 and lower isolated area 12, described lower isolated area 12 around with described buried regions 11.Wherein, the doping type of described buried regions 11 is N-type, and the doping type of described lower isolated area 12 is P type.
Then, as shown in Figure 4, on described substrate 10, form epitaxial loayer 13 by epitaxial growth technology, the doping type of described epitaxial loayer 13 is N-type.For convenience of matching with the platform of existing little regular bipolar process, the thickness of described epitaxial loayer 13 is preferably controlled at 2.5 μ m between 4 μ m, the scope of its resistivity is 1.0 Ω cm～2.2 Ω cm, and buried regions 11 and lower isolated area 12 are between described substrate 10 and epitaxial loayer 13.
Then, as shown in Figure 5, can adopt the low dose of injection technology of high-energy to form lightly-doped layer 25 on described epitaxial loayer 13, the doping type of described lightly-doped layer 25 is N-type.Before the processing step of formation lightly-doped layer 25 can form Shen Lin district 14 after forming epitaxial loayer 13, before can forming emitter region and collector region after isolated area on being formed on, the precedence that changes this technique does not affect structure and the performance of device yet.Described lightly-doped layer 25 is positioned at the surface of described epitaxial loayer 13, and its doping content is generally than the high order of magnitude of the doping content of epitaxial loayer 13.In the present embodiment, the doping content of described lightly-doped layer 25 is 1E16cm
-2～4E16cm
-2.The effect of described lightly-doped layer 25 is the horizontal proliferation that suppress collector region 17, emitter region 18 and upper isolated area 15 in subsequent technique, increases the coverage between collector region 17, emitter region 18 and upper isolated area 15, realizes the transistorized manufacture of small size.Meanwhile, described lightly-doped layer 25 is conducive to improve the parasitic fields cut-in voltage under the first interconnection line in two-layer wiring, to avoid the transistorized normal work of ghost effect impact.
As shown in Figure 6, form after lightly-doped layer 25, in described epitaxial loayer 13, form Shen Lin district 14, on isolated area 15, base 16, collector region 17 and emitter region 18.In the present embodiment, can form successively Shen Lin district 14, upper isolated area 15, base 16, then form collector region 17 and emitter region 18 simultaneously, or require to adjust the formation order of said structure according to concrete technology.Wherein, the doping type of described Shen Lin district 14 and described base 16 is N-type, the doping type of described collector region 17, emitter region 18 and upper isolated area 15 is P type, described collector region 17 is around described base 16, described base 16 is around described emitter region 18, described Shen Lin district 14 is connected with described buried regions 11, and lower isolated area 12 connects described in described upper isolated area 15.Visible, the isolation structure district that described upper isolated area 15 and described lower isolated area 12 are combined to form is surrounded on described buried regions 11 and buried regions 11 Shen Lin district 14, base 16, collector region 17 and emitter region 18 above.
Then, as shown in Figure 7 and Figure 8, on described lightly-doped layer 25, form successively the first interlayer dielectric layer 19 and voltage modulation dielectric layer 20.Described voltage modulation dielectric layer 20 comprises silicon dioxide layer (SiO
2) and be formed at the silicon nitride layer (SiN) on described silicon dioxide layer, described silicon dioxide layer thickness is preferably 150 dust～800 dusts, and described silicon nitride layer thickness is preferably 300 dust～1800 dusts.
As shown in Figure 9, after forming voltage modulation dielectric layer 20, on the first interlayer dielectric layer 19, form multiple the first contact holes.Described multiple the first contact hole lays respectively at described Shen Lin district 14, on collector region 17 and emitter region 18.
As shown in figure 10, after forming the first contact hole, on described the first interlayer dielectric layer 19 and voltage modulation dielectric layer 20, form the first interconnection line 21.Described the first interconnection line 21 is covered on described voltage modulation dielectric layer 20, and be electrically connected by the first contact hole and described Shen Lin district 14, collector region 17 and emitter region 18, realize electrically drawing of described Shen Lin district 14 and collector region 17,16 of bases are electrically connected by epitaxial loayer 13He Shenlin district 14 and then with the first interconnection line 21.Meanwhile, described the first interconnection line 21 is covered on described voltage modulation dielectric layer 20 and realizes voltage and becomes electrically drawing of dielectric layer 20.
In the present embodiment, the silicon dioxide layer in voltage modulation dielectric layer 20 is to be directly covered on described lightly-doped layer 25, and silicon nitride layer is connected and is covered completely by the first interconnection line 21 with described the first interconnection line 21.In other embodiment of the present utility model, also can not form lightly-doped layer 25, form directly in described epitaxial loayer 13, form after epitaxial loayer 13 Shen Lin district 14, on isolated area 15, base 16, collector region 17 and emitter region 18, then on described epitaxial loayer 13, form successively the first interlayer dielectric layer 19 and voltage modulation dielectric layer 20.Wherein, what described voltage modulation dielectric layer 20 was positioned at described base 16 covers whole base 16 above and directly, and the silicon dioxide layer in described voltage modulation dielectric layer 20 is connected with described base 16.
As shown in figure 11, then, on described the first interlayer dielectric layer 19 and the first interconnection line 21, form the second interlayer dielectric layer 22, form the second interlayer dielectric layer 22 and form the second contact hole in the region of the second corresponding emitter region 18 of interlayer dielectric layer 22 afterwards.The second interlayer dielectric layer 22 covers the first interlayer dielectric layer 19 and the first interconnection line 21, described the second contact hole be positioned at described emitter region 18 above.
As shown in figure 12, form the second contact hole and on described the second interlayer dielectric layer 22, form the second interconnection line 23 afterwards.Described the second interconnection line 23 is connected with the first interconnection line 21 on described emitter region 18 by the second contact hole, realizes electrically drawing of described emitter region 18.
As shown in figure 13, last, on described the second interlayer dielectric layer 22 and the second interconnection line 23, form passivation layer 24.Described passivation layer 24 is covered on the second interlayer dielectric layer 22 and the second interconnection line 23, described passivation layer 24 is the composite construction of silicon nitride layer or silicon nitride containing layer, described silicon nitride layer can stop extraneous mobile ion, steam etc. to enter voltage modulation dielectric layer 20 effectively, ensure that voltage modulation dielectric layer 20 is not subject to external influence, realizes the long-term preservation of charge inducing quantity.
The transistorized manufacture method of bipolar PNP providing according to the utility model embodiment, the bipolar PNP transistor 100 of formation is formed with voltage modulation dielectric layer 20 on base 16, and described voltage modulation dielectric layer 20 is drawn by the first interconnection line 21.By base ground connection, draw and strengthen forward and reverse potential pulse at the first interconnection line 21, can change the charge inducing quantity in voltage modulation dielectric layer 20, the change of charge inducing quantity can make the concentration of electric charges on voltage modulation dielectric layer 20 16 surfaces, base below change, and the concentration of electric charges on 16 surfaces, base determines the electric leakage raceway groove between base 16 and collector region 17, therefore, by changing the charge inducing quantity in voltage modulation dielectric layer 20, can control the little current amplification factor of described bipolar PNP transistor 100.In addition, because the normal working voltage of PNP pipe is low more than the positive and negative pulse voltage adding on voltage modulation dielectric layer 20, charge inducing quantity can remain unchanged for a long time, makes the transistorized little current amplification factor fluctuation of described bipolar PNP smaller.
To sum up, in the bipolar PNP transistor providing at the utility model embodiment, on traditional bipolar process basis by form the structure that silicon dioxide layer adds silicon nitride layer on the transistorized base of described bipolar PNP, utilize the charge storage ability of described silicon nitride layer, by changing charge inducing quantity to affect the concentration of electric charges of base region surface, and then it is adjustable to realize little current amplification factor.
Foregoing description is only the description to the utility model preferred embodiment; the not any restriction to the utility model scope; any change, modification that the those of ordinary skill in the utility model field does according to above-mentioned disclosure, all belong to the protection range of claims.
Claims (10)
1. a bipolar PNP transistor, is characterized in that, comprising:
Substrate;
Be formed at the epitaxial loayer on described substrate;
Be formed at described epitaxial loayer Zhong Shenlin district, base, collector region and emitter region;
Be formed at the first interlayer dielectric layer and voltage modulation dielectric layer on described epitaxial loayer;
Be formed at the first interconnection line on described the first interlayer dielectric layer and voltage modulation dielectric layer;
Be formed at the second interlayer dielectric layer on described the first interlayer dielectric layer and the first interconnection line;
Be formed at the second interconnection line on described the second interlayer dielectric layer;
Wherein, described voltage modulation dielectric layer is covered on described base, and is realized and electrically being drawn by described the first interconnection line.
2. bipolar PNP transistor as claimed in claim 1, is characterized in that, described collector region is surrounded on described base, and described base ring is around in described emitter region; Described the first interconnection line is connected with described Shen Lin district, emitter region and collector region, for realizing electrically drawing of described Shen Lin district, collector region and base; Described the second interconnection line is connected with the first interconnection line on described emitter region, for realizing electrically drawing of described emitter region.
3. bipolar PNP transistor as claimed in claim 1, is characterized in that, described voltage modulation dielectric layer comprises silicon dioxide layer and be formed at the silicon nitride layer on described silicon dioxide layer, and described the first interconnection line covers described silicon nitride layer.
4. bipolar PNP transistor as claimed in claim 3, is characterized in that, the thickness of described silicon dioxide layer is 150～800 dusts, and the thickness of described silicon nitride layer is 300 dust～1800 dusts.
5. bipolar PNP transistor as claimed in claim 1, is characterized in that, the thickness of described epitaxial loayer is 2.5 μ m～4 μ m, and the resistivity of described epitaxial loayer is 1.0 Ω cm～2.2 Ω cm.
6. bipolar PNP transistor as claimed in claim 1, is characterized in that, also comprises the buried regions and the lower isolated area that are formed between described substrate and epitaxial loayer, and described lower isolated area is around described buried regions, and described Shen Lin district is connected with described buried regions.
7. bipolar PNP transistor as claimed in claim 6, is characterized in that, also comprises the upper isolated area being formed in epitaxial loayer, and described upper isolated area is connected with described lower isolated area.
8. bipolar PNP transistor as claimed in claim 7, is characterized in that, also comprises the lightly-doped layer that is formed at described epi-layer surface, and the doping content of described lightly-doped layer is than the high order of magnitude of the doping content of epitaxial loayer.
9. bipolar PNP transistor as claimed in claim 8, it is characterized in that, the doping type of described substrate, lower isolated area, upper isolated area, emitter region and collector region is P type, and the doping type of described epitaxial loayer, buried regions, lightly-doped layer, Shen Lin district and base is N-type.
10. bipolar PNP transistor as claimed in claim 1, is characterized in that, also comprises the passivation layer being formed on described the second interlayer dielectric layer and the second interconnection line.
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| CN103646963A (en) * | 2013-12-10 | 2014-03-19 | 杭州士兰集成电路有限公司 | Bipolar PNP transistor and manufacturing method thereof |
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| CN103646963A (en) * | 2013-12-10 | 2014-03-19 | 杭州士兰集成电路有限公司 | Bipolar PNP transistor and manufacturing method thereof |
| CN103646963B (en) * | 2013-12-10 | 2017-02-08 | 杭州士兰集成电路有限公司 | bipolar PNP transistor and manufacturing method thereof |
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