CN103646963B - bipolar PNP transistor and manufacturing method thereof - Google Patents

Abstract

The invention provides a bipolar PNP transistor and a manufacturing method thereof, comprising: a substrate; an epitaxial layer formed on the substrate; a deep phosphorus region, a base region, a collector region and a deep phosphorus region formed in the epitaxial layer Emitting region; the first interlayer dielectric layer and the voltage modulation dielectric layer formed on the epitaxial layer; the first interconnection line formed on the first interlayer dielectric layer and the voltage modulation dielectric layer; formed on The first interlayer dielectric layer and the second interlayer dielectric layer on the first interconnection; the second interconnection formed on the second interlayer dielectric layer; wherein, the voltage modulation dielectric layer covering on the base region, and realizing electrical extraction through the first interconnection line. In the present invention, a voltage-modulating dielectric layer is formed above the base region, and the voltage-modulating dielectric layer is electrically extracted through the first interconnection line. In this way, by changing the amount of induced charges in the voltage-modulating dielectric layer, the surface of the base region can be made The charge concentration changes, so that the small current magnification can be adjusted.

Description

Bipolar PNP transistor and manufacturing method thereof

technical field

The invention relates to the field of integrated circuit manufacturing, in particular to a bipolar PNP transistor and a manufacturing method thereof.

Background technique

A photoelectric sensor is a sensor that converts light signals into electrical signals through photosensitive devices. At present, photosensitive devices are generally manufactured by semiconductor technology, including photodiodes, phototransistors and photoresistors. Since the light received by the photosensitive device is relatively weak, the photogenerated current generated is also relatively weak. Usually, a preamplifier circuit is required to cooperate with the photosensitive device to amplify the signal. The photosensitive device and the preamplifier circuit are integrated on one chip to form a photoelectric sensor.

With the different applications of photoelectric sensors, various environmental disturbances have a great impact on photosensitive devices, such as switching power supply and ambient light. The current generated by environmental disturbance will affect the sensitivity of the photosensitive device. The pre-amplification circuit should be adjusted to an appropriate amplification factor to reduce the influence of environmental interference on the photosensitive device, so that the photoelectric sensor can meet the application requirements. The preamplifier circuit is composed of transistors, and the small current characteristics of transistors, including bipolar NPN transistors and bipolar PNP transistors, are very important for process adjustment.

The bipolar process is used for the design and process manufacturing of the photoelectric sensor chip. Because the layout of the bipolar process will bring parasitic effects, in order to output the photoelectric signal with the largest possible signal-to-noise ratio, it is necessary to perform multiple layout adjustments during the manufacturing process. And process debugging to find the best match between the photosensitive device and the preamplifier circuit, so as to adapt to the application requirements in different environments.

The bipolar PNP transistor manufactured by the existing bipolar process has relatively large fluctuations in the output small current magnification. Even if the small current fluctuation is reduced through process optimization, the central value of the small current magnification is not variable, so It cannot meet the application requirements in different environments. Among them, the range of the collector current amplified by the small current is generally in the range of 10nA to 100nA.

Based on this, how to improve the non-adjustable small current amplification factor of the bipolar PNP transistor in the prior art has become an urgent technical problem to be solved by those skilled in the art.

Contents of the invention

The object of the present invention is to provide a bipolar PNP transistor and a manufacturing method thereof, so as to solve the problem that the small current amplification factor of the existing bipolar PNP transistor cannot be adjusted.

In order to solve the above technical problems, the present invention provides a bipolar PNP transistor, which includes: a substrate; an epitaxial layer formed on the substrate; a deep phosphorus region formed in the epitaxial layer, Base region, collector region and emitter region; the first interlayer dielectric layer and the voltage modulation dielectric layer formed on the epitaxial layer; the first interlayer dielectric layer and the voltage modulation dielectric layer formed on the first interlayer dielectric layer An interconnection line; a second interlayer dielectric layer formed on the first interlayer dielectric layer and the first interconnection line; a second interconnection line formed on the second interlayer dielectric layer; wherein, The voltage-modulating medium layer covers the base region, and is electrically drawn out through the first interconnection line.

Preferably, in the bipolar PNP transistor, the collector region surrounds the base region, and the base region surrounds the emitter region; the first interconnection line and the deep phosphorus region, The emitter region is connected to the collector region for realizing the electrical extraction of the deep phosphorus region and the collector region; the second interconnection is connected to the first interconnection above the emitter region for realizing the The electrical extraction of the emission area.

Preferably, in the bipolar PNP transistor, the voltage modulation medium layer includes a silicon dioxide layer and a silicon nitride layer; the silicon dioxide layer is located below the silicon nitride layer, and the second An interconnection line covers the silicon nitride layer.

Preferably, in the bipolar PNP transistor, the thickness of the silicon dioxide layer is 150-800 angstroms, and the thickness of the silicon nitride layer is 300-1800 angstroms.

Preferably, in the bipolar PNP transistor, the thickness of the epitaxial layer is 2.5 μm˜4 μm, and the resistivity of the epitaxial layer is 1.0Ω·cm˜2.2Ω·cm.

Preferably, in the bipolar PNP transistor, it also includes: a buried layer and a lower isolation region formed between the substrate and the epitaxial layer; the lower isolation region surrounds the buried layer, and the deep phosphorus region is connected to the buried layer.

Preferably, the bipolar PNP transistor further includes: an upper isolation region formed in the epitaxial layer; the upper isolation region is connected to the lower isolation region.

Preferably, the bipolar PNP transistor further includes: a lightly doped layer formed on the surface of the epitaxial layer, the concentration of the lightly doped layer being an order of magnitude higher than that of the epitaxial layer.

Preferably, in the bipolar PNP transistor, the doping types of the substrate, the lower isolation region, the upper isolation region, the emitter region and the collector region are all P-type, and the epitaxial layer, buried layer, light The doping types of the doped layer, the deep phosphorus region and the base region are all N type.

Preferably, the bipolar PNP transistor further includes: a passivation layer formed on the second interlayer dielectric layer and the second interconnection line.

The present invention also provides a method for manufacturing a bipolar PNP transistor, the method for manufacturing a bipolar PNP transistor includes the following steps:

providing a substrate;

forming an epitaxial layer on the substrate;

sequentially forming a deep phosphorus region, a base region, a collector region and an emitter region in the epitaxial layer;

sequentially forming a first interlayer dielectric layer and a voltage modulation dielectric layer on the epitaxial layer;

forming a first interconnect line on the first interlayer dielectric layer and the voltage modulation dielectric layer;

forming a second interlayer dielectric layer on the first interlayer dielectric layer and the first interconnect;

forming a second interconnection line on the second interlayer dielectric layer;

Wherein, the voltage-modulating dielectric layer covers the base region, and is electrically drawn out through the first interconnection line.

Preferably, in the manufacturing method of the bipolar PNP transistor, the collector region surrounds the base region, and the base region surrounds the emitter region; the first interconnection line and the deep The phosphorus region, the emitter region and the collector region are connected to realize the electrical extraction of the deep phosphorus region and the collector region; the second interconnection is connected to the first interconnection above the emitter region for The electrical extraction of the emitting area is realized.

Preferably, in the manufacturing method of the bipolar PNP transistor, the voltage modulation medium layer includes a silicon dioxide layer and a silicon nitride layer; the silicon dioxide layer is located under the silicon nitride layer, The first interconnection covers the silicon nitride layer.

Preferably, in the manufacturing method of the bipolar PNP transistor, the thickness of the silicon dioxide layer is 150-800 angstroms, and the thickness of the silicon nitride layer is 300-1800 angstroms.

Preferably, in the manufacturing method of the bipolar PNP transistor, the thickness of the epitaxial layer is 2.5 μm˜4 μm, and the resistivity of the epitaxial layer is 1.0Ω·cm˜2.2Ω·cm.

Preferably, in the manufacturing method of the bipolar PNP transistor, before forming the epitaxial layer, it also includes: sequentially forming a buried layer and a lower isolation region in the substrate; the lower isolation region surrounds the buried layer , the deep phosphorus region is connected to the buried layer.

Preferably, in the manufacturing method of the bipolar PNP transistor, after forming the epitaxial layer, it also includes: forming a lightly doped layer on the surface of the epitaxial layer, the concentration of the lightly doped layer is higher than that of the epitaxial layer concentration is an order of magnitude higher.

Preferably, in the manufacturing method of the bipolar PNP transistor, before forming the base region and after forming the lightly doped layer, it further includes: forming an upper isolation region in the epitaxial layer; the upper isolation region and The lower isolation zone is connected.

Preferably, in the manufacturing method of the bipolar PNP transistor, the doping types of the substrate, the lower isolation region, the upper isolation region, the emitter region and the collector region are all P-type, and the epitaxial layer, buried The doping types of layer, lightly doped layer, deep phosphorus region and base region are all N type.

Preferably, in the manufacturing method of the bipolar PNP transistor, after forming the second interconnection, it further includes: forming a passivation layer on the second interlayer dielectric layer and the second interconnection.

In the bipolar PNP transistor and its manufacturing method provided by the present invention, a voltage-modulating dielectric layer is formed above the base region, and the voltage-modulating dielectric layer is electrically drawn out through the first interconnection line. In this way, by changing the voltage regulation The amount of induced charges in the variable dielectric layer can change the charge concentration on the surface of the base region, thereby realizing the adjustable magnification of small currents.

Description of drawings

Fig. 1 is the schematic flow sheet of the manufacturing method of the bipolar PNP transistor of an embodiment of the present invention;

2 to 13 are structural schematic diagrams of devices in each step of the manufacturing method of the bipolar PNP transistor according to an embodiment of the present invention.

detailed description

The bipolar PNP transistor and its manufacturing method proposed by the present invention will be further described in detail below with reference to the drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

Please refer to FIG. 13 , which is a schematic structural diagram of a bipolar PNP transistor according to an embodiment of the present invention. As shown in FIG. 13 , the bipolar PNP transistor 100 includes: a substrate 10; an epitaxial layer 13 formed on the substrate 10; a deep phosphorus region 14 formed in the epitaxial layer 13, a base region 16, The collector region 17 and the emitter region 18; the first interlayer dielectric layer 19 and the voltage modulation dielectric layer 20 formed on the epitaxial layer 13; the first interlayer dielectric layer 19 and the voltage modulation dielectric layer formed on the The first interconnection line 21 on the 20; the second interlayer dielectric layer 22 formed on the first interlayer dielectric layer 19 and the first interconnection line 21; the second interlayer dielectric layer 22 formed on the second interlayer dielectric layer 22 The second interconnection line 23; wherein, the voltage modulation medium layer 20 is formed on the base region 16, and is electrically extracted through the first interconnection line 21.

Specifically, please continue to refer to FIG. 13. In this embodiment, the substrate 10 is a silicon substrate whose doping type is P-type and whose crystal orientation is <111>, and its resistivity ranges from 10Ω·cm to 20Ω·cm. cm. An epitaxial layer 13 is formed on the substrate 10 , the doping type of the epitaxial layer 13 is N type, and its resistivity ranges from 1.0Ω·cm to 2.2Ω·cm. The thickness of the epitaxial layer 13 is preferably between 2.5 μm and 4 μm, and this thickness range can match the platform of the existing small regular bipolar process.

A deep phosphorus region 14, an upper isolation region 15, a base region 16, a collector region 17 and an emitter region 18 are formed in the epitaxial layer 13, wherein the doping type of the deep phosphorus region 14 and the base region 16 is N type , the doping type of the collector region 17, the emitter region 18 and the upper isolation region 15 is P type. The collector region 17 surrounds the base region 16 , and the base region 16 surrounds the emitter region 18 .

A buried layer 11 and a lower isolation region 12 are formed between the substrate 10 and the epitaxial layer 13 , and the lower isolation region 12 surrounds the buried layer 11 . Wherein, the doping type of the buried layer 11 is N type, and the doping type of the lower isolation region 12 is P type. The deep phosphorus region 14 is connected to the buried layer 11 , and the upper isolation region 15 is connected to the lower isolation region 12 . It can be seen that the isolation structure region formed by the combination of the upper isolation region 15 and the lower isolation region 12 surrounds the buried layer 11 and the deep phosphorus region 14 above the buried layer 11, the base region 16, the collector region 17 and the emitter region 18.

As shown in FIG. 13, a first interlayer dielectric layer 19 and a voltage modulation dielectric layer 20 are formed on the epitaxial layer 13, and a first interlayer dielectric layer 19 and a voltage modulation dielectric layer 20 are formed on the first interlayer dielectric layer 19. Interconnect 21. Wherein, the voltage modulating dielectric layer 20 is located on the base region 16 and covers the entire base region 16, and the first interlayer dielectric layer 19 corresponds to the regions of the deep phosphorus region 14, the collector region 17 and the emitter region 18 A first contact hole is formed, and the first interconnection line 21 is connected to the deep phosphorus region 14, the collector region 17 and the emitter region 18 through the first contact hole, so as to realize the electrical connection between the deep phosphorus region 14 and the collector region 17. sex elicited. The base region 16 is then electrically connected to the first interconnection line 21 through the epitaxial layer 13 and the deep phosphorus region 14 , so as to realize the electrical extraction of the base region 16 . At the same time, the region of the first interlayer dielectric layer 19 corresponding to the base region 14 is formed with a voltage-modulating dielectric layer window, and the voltage-modulating dielectric layer 20 is formed in the voltage-modulating dielectric layer window. The first interconnection line 21 covers the voltage-modulating medium layer 20 and realizes electrical extraction of the voltage-modulating medium layer 20 . In this embodiment, the voltage modulating medium layer 20 includes a silicon dioxide layer and a silicon nitride layer, the silicon nitride layer covers the silicon dioxide layer, and the first interconnection line 21 covers on the silicon nitride layer. The silicon dioxide layer has a thickness of 150 angstroms to 800 angstroms, and the silicon nitride layer has a thickness of 300 angstroms to 1800 angstroms.

As shown in FIG. 13 , a second interlayer dielectric layer 22 is formed on the first interlayer dielectric layer 19 and the first interconnection lines 21 . A second interconnection line 23 is formed on the second interlayer dielectric layer 22, and a second contact hole is formed in a region of the second interlayer dielectric layer 22 corresponding to the emission region 18, the second The interconnection line 23 is connected to the first interconnection line 21 on the emission area 18 through the second contact hole, so as to realize the electrical extraction of the emission area 18 .

As shown in FIG. 13 , the bipolar PNP transistor 100 further includes: a passivation layer 24 formed on the second interlayer dielectric layer and the second interconnection line. The passivation layer 24 is preferably a silicon nitride layer or a composite structure containing a silicon nitride layer. The silicon nitride layer can effectively prevent external movable ions, water vapor, etc. The variable medium layer 20 is not affected by the outside world, and realizes long-term storage of the induced charge quantity.

The bipolar PNP transistor 100 may further include a lightly doped layer 25 formed on the epitaxial layer 13 , and the doping type of the lightly doped layer 25 is N type. The lightly doped layer 25 is located on the surface of the epitaxial layer 13 , and its doping concentration is generally an order of magnitude higher than that of the epitaxial layer 13 . The doping concentration of the lightly doped layer 25 is generally 1E16cm ^-2 ~ 4E16cm ^-2 , its function is to suppress the lateral diffusion of the collector region 17, the emitter region 18 and the upper isolation region 15, increase the concentration of the collector region 17, the emitter region The effective distance between 18 and the upper isolation region 15 realizes the manufacture of small-area transistors. At the same time, the lightly doped layer 25 is beneficial to increase the turn-on voltage of the parasitic field under the first interconnection line in the double-layer wiring, so as to prevent the parasitic effect from affecting the normal operation of the transistor.

In the bipolar PNP transistor 100 provided by the embodiment of the present invention, the base region 16 is covered with a voltage-modulating dielectric layer 20 , and the voltage-modulating dielectric layer 20 is electrically extracted through the first interconnection line 21 . The voltage modulating medium layer 20 includes a silicon dioxide layer and a silicon nitride layer formed on the silicon dioxide layer. Wherein, the silicon nitride layer of the voltage modulating medium layer 20 has charge storage characteristics, increasing the negative pressure can reduce the negative charge ratio of the silicon nitride layer, and increasing the positive voltage can restore the negative charge ratio of the silicon nitride layer, therefore By increasing the forward and reverse voltage pulses through the first interconnection line 21 , the amount of induced charges in the voltage modulation medium layer 20 can be changed. At the same time, since the normal operating voltage of the PNP transistor is much lower than the forward and reverse pulse voltage applied to the voltage-modulating dielectric layer 20, the amount of induced charges can be kept stable for a long time. Because the small current magnification of the bipolar PNP transistor manufactured by the bipolar process is affected by the charge concentration on the surface of the base region, changing the amount of induced charges can change the charge concentration on the surface of the base region 16, thereby changing the base region of the bipolar PNP transistor. 16 and the leakage channel between the collector region 17. It can be seen that by changing the amount of induced charge in the voltage modulating dielectric layer 20, the leakage channel between the base region 16 and the collector region 17 of the bipolar PNP transistor 100 can be controlled, and the low current flow rate of the bipolar PNP transistor 100 can be changed. The lower magnification.

Correspondingly, this embodiment also provides a method for manufacturing a bipolar PNP transistor. Please refer to Fig. 1, and in conjunction with Fig. 2 to Fig. 13, the manufacturing method of described bipolar PNP transistor comprises the following steps:

S10: providing a substrate 10;

S11: forming an epitaxial layer 13 on the substrate 10;

S12: sequentially forming a deep phosphorus region 14, a base region 16, a collector region 17 and an emitter region 18 in the epitaxial layer 13;

S13: sequentially forming a first interlayer dielectric layer 19 and a voltage modulation dielectric layer 20 on the epitaxial layer 13;

S14: forming a first interconnection line 21 on the first interlayer dielectric layer 19 and the voltage modulation dielectric layer 20;

S15: forming a second interlayer dielectric layer 22 on the first interlayer dielectric layer 19 and the first interconnection line 21;

S16: forming a second interconnection line 23 on the second interlayer dielectric layer 22;

Wherein, the voltage-modulating dielectric layer 20 covers the base region 16 and is electrically extracted through the first interconnection line 21 .

Specifically, as shown in FIG. 2, firstly, a substrate 10 is provided, and the substrate 10 adopts a silicon substrate whose doping type is P-type and whose crystal orientation is <111>, and its resistivity ranges from 10Ω·cm ~20Ω·cm.

Next, as shown in FIG. 3 , a buried layer 11 and a lower isolation region 12 are formed in the substrate 10 , and the lower isolation region 12 surrounds the buried layer 11 . Wherein, the doping type of the buried layer 11 is N type, and the doping type of the lower isolation region 12 is P type.

Then, as shown in FIG. 4 , an epitaxial layer 13 is formed on the substrate 10 through an epitaxial growth process, and the doping type of the epitaxial layer 13 is N type. In order to facilitate matching with the existing small-rule bipolar process platform, the thickness of the epitaxial layer 13 is preferably controlled between 2.5 μm and 4 μm, and its resistivity ranges from 1.0Ω·cm to 2.2Ω·cm. Layer 11 and lower isolation region 12 are located between said substrate 10 and epitaxial layer 13 .

Next, as shown in FIG. 5 , a lightly doped layer 25 may be formed on the epitaxial layer 13 by using a high-energy low-dose field implantation process, and the doping type of the lightly doped layer 25 is N type. The process steps of forming the lightly doped layer 25 can be formed after forming the epitaxial layer 13 before forming the deep phosphorus region 14, and can also be formed after forming the upper isolation region and before forming the emitter region and the collector region. Changing the sequence of the process does not affect Device structure and performance. The lightly doped layer 25 is located on the surface of the epitaxial layer 13 , and its doping concentration is generally an order of magnitude higher than that of the epitaxial layer 13 . In this embodiment, the doping concentration of the lightly doped layer 25 is 1E16cm ⁻² to 4E16cm ⁻² . The function of the lightly doped layer 25 is to suppress the lateral diffusion of the collector region 17, the emitter region 18 and the upper isolation region 15 in the subsequent process, and increase the effective distance between the collector region 17, the emitter region 18 and the upper isolation region 15. The distance enables the fabrication of small-area transistors. At the same time, the lightly doped layer 25 is beneficial to increase the turn-on voltage of the parasitic field under the first interconnection line in the double-layer wiring, so as to prevent the parasitic effect from affecting the normal operation of the transistor.

As shown in FIG. 6 , after the lightly doped layer 25 is formed, a deep phosphorus region 14 , an upper isolation region 15 , a base region 16 , a collector region 17 and an emitter region 18 are formed in the epitaxial layer 13 . In this embodiment, the deep phosphorus region 14, the upper isolation region 15, and the base region 16 can be formed sequentially, and then the collector region 17 and the emitter region 18 can be formed simultaneously, or the formation sequence of the above structures can be adjusted according to specific process requirements. Wherein, the doping type of the deep phosphorus region 14 and the base region 16 is N type, the doping type of the collector region 17, the emitter region 18 and the upper isolation region 15 is P type, and the collector region 17 surrounds the base region 16, the base region 16 surrounds the emitter region 18, the deep phosphorus region 14 is connected to the buried layer 11, and the upper isolation region 15 is connected to the lower isolation region 12. It can be seen that the isolation structure region formed by the combination of the upper isolation region 15 and the lower isolation region 12 surrounds the buried layer 11 and the deep phosphorus region 14 above the buried layer 11, the base region 16, the collector region 17 and the emitter region 18.

Then, as shown in FIG. 7 and FIG. 8 , the first interlayer dielectric layer 19 and the voltage modulation dielectric layer 20 are sequentially formed on the lightly doped layer 25 . The voltage-modulating dielectric layer 20 includes a silicon dioxide layer (SiO ₂ ) and a silicon nitride layer (SiN) formed on the silicon dioxide layer, and the thickness of the silicon dioxide layer is preferably 150 angstroms to 800 angstroms , the thickness of the silicon nitride layer is preferably 300 angstroms to 1800 angstroms.

As shown in FIG. 9 , after forming the voltage modulating dielectric layer 20 , a plurality of first contact holes are formed on the first interlayer dielectric layer 19 . The plurality of first contact holes are respectively located on the deep phosphorus region 14 , the collector region 17 and the emitter region 18 .

As shown in FIG. 10 , after forming the first contact hole, a first interconnection line 21 is formed on the first interlayer dielectric layer 19 and the voltage modulation dielectric layer 20 . The first interconnection 21 covers the voltage modulation dielectric layer 20, and is electrically connected to the deep phosphorus region 14, the collector region 17 and the emitter region 18 through a first contact hole, realizing the deep The phosphorus region 14 and the collector region 17 are electrically drawn out, and the base region 16 is electrically connected to the first interconnection line 21 through the epitaxial layer 13 and the deep phosphorus region 14 . At the same time, the first interconnection line 21 covers the voltage-modulating medium layer 20 and realizes electrical extraction of the voltage-modulating medium layer 20 .

In this embodiment, the silicon dioxide layer in the voltage modulating dielectric layer 20 is directly covered on the lightly doped layer 25, and the silicon nitride layer is connected to the first interconnection line 21 and is connected by the first interconnection line 21. Line 21 is completely covered. In other embodiments of the present invention, the lightly doped layer 25 may not be formed, and the deep phosphorus region 14, the upper isolation region 15, the base region 16, the collector Region 17 and emitter region 18 , and then a first interlayer dielectric layer 19 and a voltage-modulating dielectric layer 20 are sequentially formed on the epitaxial layer 13 . Wherein, the voltage-modulating dielectric layer 20 is located above the base region 16 and directly covers the entire base region 16 , and the silicon dioxide layer in the voltage-modulating dielectric layer 20 is connected to the base region 16 .

As shown in FIG. 11, then, a second interlayer dielectric layer 22 is formed on the first interlayer dielectric layer 19 and the first interconnection 21, and after the second interlayer dielectric layer 22 is formed, the second interlayer dielectric layer 22 is formed. The region of layer 22 corresponding to emitter region 18 forms a second contact hole. The second interlayer dielectric layer 22 covers the first interlayer dielectric layer 19 and the first interconnection line 21 , and the second contact hole is located above the emission region 18 .

As shown in FIG. 12 , after forming the second contact hole, a second interconnection line 23 is formed on the second interlayer dielectric layer 22 . The second interconnection line 23 is connected to the first interconnection line 21 on the emitting region 18 through a second contact hole, so as to realize electrical extraction of the emitting region 18 .

As shown in FIG. 13 , finally, a passivation layer 24 is formed on the second interlayer dielectric layer 22 and the second interconnection line 23 . The passivation layer 24 covers the second interlayer dielectric layer 22 and the second interconnection 23, the passivation layer 24 is a silicon nitride layer or a composite structure containing a silicon nitride layer, and the silicon nitride The layer can effectively prevent external movable ions, water vapor, etc. from entering the voltage modulation medium layer 20, ensure that the voltage modulation medium layer 20 is not affected by the outside world, and realize long-term storage of the induced charge quantity.

According to the manufacturing method of the bipolar PNP transistor provided in the embodiment of the present invention, the formed bipolar PNP transistor 100 has a voltage-modulating dielectric layer 20 formed on the base region 16, and the voltage-modulating dielectric layer 20 passes through the first interconnection line 21 elicited. The base area is grounded, and the forward and reverse voltage pulses are increased on the leads of the first interconnection line 21, which can change the amount of induced charges in the voltage modulation dielectric layer 20, and the change of the amount of induced charges will make the voltage modulation dielectric layer 20 below The charge concentration on the surface of the base region 16 changes, and the charge concentration on the surface of the base region 16 determines the leakage channel between the base region 16 and the collector region 17. Therefore, the amount of induced charges in the dielectric layer 20 can be adjusted by changing the voltage , the small current amplification factor of the bipolar PNP transistor 100 can be controlled. In addition, since the normal operating voltage of the PNP transistor is far lower than the forward and reverse pulse voltage applied on the voltage-modulating dielectric layer 20, the amount of induced charge can remain unchanged for a long time, so that the small current amplification factor of the bipolar PNP transistor fluctuates smaller.

To sum up, in the bipolar PNP transistor and its manufacturing method provided by the embodiment of the present invention, on the basis of the traditional bipolar process, a silicon dioxide layer plus a silicon nitride layer is formed on the base region of the bipolar PNP transistor The structure utilizes the charge storage characteristics of the silicon nitride layer to affect the charge concentration on the surface of the base region by changing the amount of induced charges, thereby realizing adjustable small current magnification.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosures shall fall within the protection scope of the claims.

Claims (18)

1. A bipolar PNP transistor is characterized in that, comprising: Substrate; an epitaxial layer formed on the substrate; a deep phosphorus region, a base region, a collector region and an emitter region formed in the epitaxial layer; a first interlayer dielectric layer and a voltage modulation dielectric layer formed on the epitaxial layer; A first interconnect line formed on the first interlayer dielectric layer and the voltage modulation dielectric layer; a second interlayer dielectric layer formed on the first interlayer dielectric layer and the first interconnect; a second interconnect line formed on the second interlayer dielectric layer; Wherein, the voltage modulation medium layer includes a silicon dioxide layer and a silicon nitride layer formed on the silicon dioxide layer, and the first interconnection line covers the silicon nitride layer; the voltage modulation The dielectric layer covers the base region and realizes electrical extraction through the first interconnection line, and the charge concentration on the surface of the base region can be changed by changing the amount of induced charges in the voltage modulation dielectric layer . 2. The bipolar PNP transistor according to claim 1, wherein the collector region surrounds the base region, and the base region surrounds the emitter region; the first interconnection line and the The deep phosphorus region, the emitter region and the collector region are connected to realize the electrical extraction of the deep phosphorus region, the collector region and the base region; the second interconnection line is connected to the first interconnection on the emitter region The wiring connection is used to realize the electrical extraction of the emitting area. 3. The bipolar PNP transistor according to claim 1, wherein the silicon dioxide layer has a thickness of 150-800 angstroms, and the silicon nitride layer has a thickness of 300-1800 angstroms. 4 . The bipolar PNP transistor according to claim 1 , wherein the thickness of the epitaxial layer is 2.5 μm˜4 μm, and the resistivity of the epitaxial layer is 1.0Ω·cm˜2.2Ω·cm. 5. The bipolar PNP transistor according to claim 1, further comprising a buried layer and a lower isolation region formed between the substrate and the epitaxial layer, the lower isolation region surrounds the buried layer, The deep phosphorus region is connected to the buried layer. 6. The bipolar PNP transistor according to claim 5, further comprising an upper isolation region formed in the epitaxial layer, the upper isolation region being connected to the lower isolation region. 7. The bipolar PNP transistor according to claim 6, further comprising a lightly doped layer formed on the surface of the epitaxial layer, the doping concentration of the lightly doped layer being higher than the doping concentration of the epitaxial layer an order of magnitude higher. 8. The bipolar PNP transistor according to claim 7, wherein the doping type of the substrate, the lower isolation region, the upper isolation region, the emitter region and the collector region is P-type, and the epitaxial layer The doping types of the buried layer, the lightly doped layer, the deep phosphorus region and the base region are all N type. 9. The bipolar PNP transistor according to claim 1, further comprising a passivation layer formed on the second interlayer dielectric layer and the second interconnection line. 10. A method for manufacturing a bipolar PNP transistor, comprising: providing a substrate; forming an epitaxial layer on the substrate; forming a deep phosphorous region, a base region, a collector region and an emitter region in the epitaxial layer; forming a first interlayer dielectric layer and a voltage modulation dielectric layer on the epitaxial layer; forming a first interconnect line on the first interlayer dielectric layer and the voltage modulation dielectric layer; forming a second interlayer dielectric layer on the first interlayer dielectric layer and the first interconnect; forming a second interconnection line on the second interlayer dielectric layer; Wherein, the voltage modulation medium layer includes a silicon dioxide layer and a silicon nitride layer formed on the silicon dioxide layer, and the first interconnection line covers the silicon nitride layer; the voltage modulation The dielectric layer covers the base region and realizes electrical extraction through the first interconnection line, and the charge concentration on the surface of the base region can be changed by changing the amount of induced charges in the voltage modulation dielectric layer . 11. The method for manufacturing a bipolar PNP transistor according to claim 10, wherein the collector region surrounds the base region, and the base region surrounds the emitter region; the first interconnection The line is connected with the deep phosphorus region, the emitter region and the collector region, and is used to realize the electrical extraction of the deep phosphorus region, the collector region and the base region, and the second interconnection line is located on the emitter region. The first interconnection line is used to realize the electrical extraction of the emission area. 12. The method for manufacturing a bipolar PNP transistor according to claim 10, wherein the thickness of the silicon dioxide layer is 150-800 angstroms, and the thickness of the silicon nitride layer is 300-1800 angstroms. 13. The method for manufacturing a bipolar PNP transistor according to claim 10, wherein the thickness of the epitaxial layer is 2.5 μm to 4 μm, and the resistivity of the epitaxial layer is 1.0 Ω·cm to 2.2 Ω·cm . 14. The method for manufacturing a bipolar PNP transistor according to claim 10, further comprising sequentially forming a buried layer and a lower isolation region in the substrate before forming the epitaxial layer, the lower isolation region A region surrounds the buried layer, and the deep phosphorus region is connected to the buried layer. 15. The method for manufacturing a bipolar PNP transistor according to claim 14, further comprising forming a lightly doped layer on the surface of the epitaxial layer after forming the epitaxial layer, the doped layer of the lightly doped layer The dopant concentration is an order of magnitude higher than that of the epitaxial layer. 16. The method for manufacturing a bipolar PNP transistor according to claim 15, further comprising forming an upper isolation region in the epitaxial layer before forming the base region and after forming the lightly doped layer, the The upper isolation region is connected to the lower isolation region. 17. the manufacture method of bipolar PNP transistor as claimed in claim 16 is characterized in that, the doping type of described substrate, lower isolation region, upper isolation region, emitter region and collector region is all P-type, so The doping types of the epitaxial layer, the buried layer, the lightly doped layer, the deep phosphorus region and the base region are all N type. 18. The method for manufacturing a bipolar PNP transistor according to claim 10, further comprising forming a passivation layer on the second interlayer dielectric layer and the second interconnection after forming the second interconnection. layers.