CN103646963B - bipolar PNP transistor and manufacturing method thereof - Google Patents
bipolar PNP transistor and manufacturing method thereof Download PDFInfo
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- CN103646963B CN103646963B CN201310674022.1A CN201310674022A CN103646963B CN 103646963 B CN103646963 B CN 103646963B CN 201310674022 A CN201310674022 A CN 201310674022A CN 103646963 B CN103646963 B CN 103646963B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 40
- 239000010410 layer Substances 0.000 claims abstract description 300
- 239000011229 interlayer Substances 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 32
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 3
- 239000011574 phosphorus Substances 0.000 claims abstract description 3
- 238000002955 isolation Methods 0.000 claims description 55
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 44
- 238000000034 method Methods 0.000 claims description 44
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 28
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 28
- 239000000377 silicon dioxide Substances 0.000 claims description 22
- 235000012239 silicon dioxide Nutrition 0.000 claims description 21
- 238000000605 extraction Methods 0.000 claims description 14
- 230000001939 inductive effect Effects 0.000 claims description 14
- 238000002161 passivation Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 230000006698 induction Effects 0.000 abstract 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 14
- 230000003321 amplification Effects 0.000 description 13
- 230000000694 effects Effects 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910003978 SiClx Inorganic materials 0.000 description 3
- 230000007613 environmental effect Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000004321 preservation Methods 0.000 description 2
- 230000035755 proliferation Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 241000790917 Dioxys <bee> Species 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- VDGJOQCBCPGFFD-UHFFFAOYSA-N oxygen(2-) silicon(4+) titanium(4+) Chemical compound [Si+4].[O-2].[O-2].[Ti+4] VDGJOQCBCPGFFD-UHFFFAOYSA-N 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
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- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention provides a bipolar PNP transistor and a manufacturing method thereof. The bipolar PNP transistor comprises a substrate, an epitaxial layer formed on the substrate, a deep phosphorus zone, a base zone, a collection zone and an emission zone which are formed in the epitaxial layer, a first interlayer dielectric layer and a voltage modulation dielectric layer which are formed on the epitaxial layer, a first interconnection line formed on the first interlayer dielectric layer and the voltage modulation dielectric layer, a second interlayer dielectric layer formed on the first interlayer dielectric layer and the first interconnection line, and a second interconnection line formed on the second interlayer dielectric layer, wherein the base zone is covered by the voltage modulation dielectric layer, and electric leading out is realized through the first interconnection line. According to the bipolar PNP transistor and the manufacturing method, through forming the voltage modulation dielectric layer on the base zone, the electric leading out of the voltage modulation dielectric layer is realized through the first interconnection line, so the charge concentration of a base zone surface is changed through changing the induction charge number of the voltage modulation dielectric layer, and thus the magnification times of small current is adjustable.
Description
Technical field
The present invention relates to IC manufacturing field, particularly to a kind of bipolar PNP transistor and its manufacture method.
Background technology
Photoelectric sensor is a kind of sensor converting optical signals into the signal of telecommunication by light-sensitive device.Light-sensitive device at present
Typically adopt semiconductor technology manufacture, including light sensitive diode, phototriode and photoconductive resistance etc..Because light-sensitive device is connect
The light received is fainter, so the photogenerated current producing is also fainter, it usually needs a pre-amplification circuit and light-sensitive device
Cooperation is to amplify signal.Light-sensitive device and pre-amplification circuit are integrated on one chip, form photoelectric sensor.
With the difference of photoelectric sensor application scenario, the impact to light-sensitive device for all kinds of environmental disturbances is very big, such as switchs
Power supply, ambient light etc..The electric current that environmental disturbances produce can affect the sensitivity of light-sensitive device.Pre-amplification circuit will be adjusted to close
Suitable amplification coefficient, to weaken the impact to light-sensitive device for the environmental disturbances, so that photoelectric sensor meets application requirement.Preposition
Amplifying circuit is made up of transistor, the power dissipation characteristics in leakage current region of transistor, little including bipolar NPN transistor and bipolar PNP transistor
Current characteristics is all most important for technique adjustment.
Photoelectric sensor chip design and technique manufacture are carried out using bipolar process, due to the laying out pattern meeting of bipolar process
Bring ghost effect, in order to export the photosignal of signal to noise ratio as big as possible, need to carry out in the fabrication process multiple domain
Distributing adjustment and process debugging, to seek the best match of light-sensitive device and pre-amplification circuit, thus adapt under varying environment
Application requirement.
Using the bipolar PNP transistor manufactured by existing bipolar process, the small current amplification fluctuation ratio of its output
Larger, even across process optimization, small current fluctuation is reduced, but the central value of small current amplification is immutable,
The application requirement under varying environment therefore cannot be met.Wherein, the scope of the collector current that small current amplifies is typically in 10nA
～100nA.
Based on this, how to improve the nonadjustable problem of small current amplification of bipolar PNP transistor in prior art
Through becoming the technical problem of those skilled in the art's urgent need to resolve.
Content of the invention
It is an object of the invention to provide a kind of bipolar PNP transistor and its manufacture method, to solve existing bipolar PNP
The nonadjustable problem of small current amplification of transistor.
For solving above-mentioned technical problem, the present invention provides a kind of bipolar PNP transistor, and described bipolar PNP transistor includes：
Substrate；It is formed at the epitaxial layer on described substrate；It is formed at described epitaxial layer Zhong Shenlin area, base, collecting zone and launch site；
It is formed at the first interlayer dielectric layer on described epitaxial layer and voltage modulation dielectric layer；Be formed at described first interlayer dielectric layer and
The first interconnection line on voltage modulation dielectric layer；It is formed at the second interlayer on described first interlayer dielectric layer and the first interconnection line
Dielectric layer；It is formed at the second interconnection line on described second interlayer dielectric layer；Wherein, described voltage modulation dielectric layer is covered in institute
State on base, and realize electrically drawing by described first interconnection line.
Preferably, in described bipolar PNP transistor, described collecting zone is surrounded on described base, described base ring around
In described launch site；Described first interconnection line is connected with described Shen Lin area, launch site and collecting zone, is used for realizing described Shen Lin area
Electrical extraction with collecting zone；Described second interconnection line is connected with the first interconnection line above described launch site, is used for realizing institute
State the electrical extraction of launch site.
Preferably, in described bipolar PNP transistor, described voltage modulation dielectric layer includes silicon dioxide layer and nitridation
Silicon layer；Described silicon dioxide layer is located at below described silicon nitride layer, and described first interconnection line is covered in described silicon nitride layer
Above.
Preferably, in described bipolar PNP transistor, the thickness of described silicon dioxide layer is 150～800 angstroms, described
The thickness of silicon nitride layer is 300 angstroms～1800 angstroms.
Preferably, in described bipolar PNP transistor, the thickness of described epitaxial layer is 2.5 μm～4 μm, described extension
The resistivity of layer is 1.0 Ω cm～2.2 Ω cm.
Preferably, in described bipolar PNP transistor, also include：It is formed at burying between described substrate and epitaxial layer
Layer and lower isolation area；Described lower isolation area is connected with described buried regions around described buried regions, described Shen Lin area.
Preferably, in described bipolar PNP transistor, also include：It is formed at the upper isolation area in epitaxial layer；On described
Isolation area is connected with described lower isolation area.
Preferably, in described bipolar PNP transistor, also include：It is formed at the lightly-doped layer of described epi-layer surface,
High an order of magnitude of concentration of the concentration ratio epitaxial layer of described lightly-doped layer.
Preferably, in described bipolar PNP transistor, described substrate, lower isolation area, upper isolation area, launch site and collection
The doping type in electric area is p-type, and described epitaxial layer, buried regions, the doping type of lightly-doped layer, Shen Lin area and base are N-type.
Preferably, in described bipolar PNP transistor, also include：It is formed at described second interlayer dielectric layer and second
Passivation layer on interconnection line.
Present invention also offers a kind of manufacture method of bipolar PNP transistor, the manufacture method of described bipolar PNP transistor
Comprise the following steps：
One substrate is provided；
Form epitaxial layer over the substrate；
Shen Lin area, base, collecting zone and launch site is sequentially formed in described epitaxial layer；
Sequentially form the first interlayer dielectric layer and voltage modulation dielectric layer on said epitaxial layer there；
Described first interlayer dielectric layer and voltage modulation dielectric layer form the first interconnection line；
Described first interlayer dielectric layer and the first interconnection line form the second interlayer dielectric layer；
Described second interlayer dielectric layer forms the second interconnection line；
Wherein, described voltage modulation dielectric layer is covered on described base, and is realized electrically by described first interconnection line
Draw.
Preferably, in the manufacture method of described bipolar PNP transistor, described collecting zone is surrounded on described base, institute
State base and be surrounded on described launch site；Described first interconnection line is connected with described Shen Lin area, launch site and collecting zone, for realizing
Described Shen Lin area and the electrical extraction of collecting zone；Described second interconnection line is connected with the first interconnection line above launch site,
For realizing the electrical extraction of described launch site.
Preferably, in the manufacture method of described bipolar PNP transistor, described voltage modulation dielectric layer includes titanium dioxide
Silicon layer and silicon nitride layer；Described silicon dioxide layer is located at below described silicon nitride layer, and described first interconnection line is covered in described
Above silicon nitride layer.
Preferably, in the manufacture method of described bipolar PNP transistor, described silicon dioxide layer thickness is 150～800
Angstrom, described silicon nitride layer thickness is 300～1800 angstroms.
Preferably, in the manufacture method of described bipolar PNP transistor, the thickness of described epitaxial layer is 2.5 μm～4 μ
M, the resistivity of described epitaxial layer is 1.0 Ω cm～2.2 Ω cm.
Preferably, in the manufacture method of described bipolar PNP transistor, before forming epitaxial layer, also include：Institute
State and in substrate, sequentially form buried regions and lower isolation area；Described lower isolation area is around described buried regions, described Shen Lin area and described buried regions
Connect.
Preferably, in the manufacture method of described bipolar PNP transistor, after forming epitaxial layer, also include：Institute
The surface stating epitaxial layer forms lightly-doped layer, high an order of magnitude of concentration of the concentration ratio epitaxial layer of described lightly-doped layer.
Preferably, in the manufacture method of described bipolar PNP transistor, before forming base, it is lightly doped in formation
After layer, also include：Isolation area on being formed in described epitaxial layer；Described upper isolation area is connected with described lower isolation area.
Preferably, in the manufacture method of described bipolar PNP transistor, described substrate, lower isolation area, upper isolation area,
The doping type of launch site and collecting zone is p-type, described epitaxial layer, buried regions, the doping class of lightly-doped layer, Shen Lin area and base
Type is N-type.
Preferably, in the manufacture method of described bipolar PNP transistor, after forming the second interconnection line, also include：
Passivation layer is formed on described second interlayer dielectric layer and the second interconnection line.
In the bipolar PNP transistor that the present invention provides and its manufacture method, form voltage modulation medium above base
Layer, described voltage modulation dielectric layer passes through the first interconnection line and realizes electrically drawing, so, by changing voltage modulation dielectric layer
Charge inducing quantity can make the concentration of electric charges of base region surface change, thus it is adjustable to realize small current amplification.
Brief description
Fig. 1 is the schematic flow sheet of the manufacture method of the bipolar PNP transistor of one embodiment of the invention；
Fig. 2 to Figure 13 is the structure of the device of each step of manufacture method of the bipolar PNP transistor of one embodiment of the invention
Schematic diagram.
Specific embodiment
Below in conjunction with the drawings and specific embodiments, bipolar PNP transistor proposed by the present invention and its manufacture method are made into one
Step describes in detail.According to following explanation and claims, advantages and features of the invention will become apparent from.It should be noted that, attached
Figure is all in the form of very simplification and all using non-accurately ratio, only real in order to conveniently, lucidly to aid in illustrating the present invention
Apply the purpose of example.
Refer to Figure 13, it is the structural representation of the bipolar PNP transistor of the embodiment of the present invention.As shown in figure 13, institute
State bipolar PNP transistor 100 to include：Substrate 10；It is formed at the epitaxial layer 13 on described substrate 10；It is formed at described epitaxial layer 13
Zhong Shenlin area 14, base 16, collecting zone 17 and launch site 18；It is formed at the first interlayer dielectric layer 19 on described epitaxial layer 13
With voltage modulation dielectric layer 20；It is formed at the first interconnection line on described first interlayer dielectric layer 19 and voltage modulation dielectric layer 20
21；It is formed at the second interlayer dielectric layer 22 on described first interlayer dielectric layer 19 and the first interconnection line 21；It is formed at described
The second interconnection line 23 on two interlayer dielectric layers 22；Wherein, described voltage modulation dielectric layer 20 is formed on described base 16, and
Realize electrically drawing by described first interconnection line 21.
Specifically, please continue to refer to Figure 13, in the present embodiment, described substrate 10 is p-type using doping type and crystal orientation is<
111>Silicon substrate, the scope of its resistivity is 10 Ω cm～20 Ω cm.Epitaxial layer 13, institute are formed with described substrate 10
The doping type stating epitaxial layer 13 is N-type, and the scope of its resistivity is 1.0 Ω cm～2.2 Ω cm.Described epitaxial layer 13
Preferably between 2.5 μm to 4 μm, this thickness range can be matched thickness with the platform of existing little regular dipole technique.
It is formed with Shen Lin area 14, upper isolation area 15, base 16, collecting zone 17 and launch site 18 in described epitaxial layer 13, its
In, the doping type of Shen Lin area 14 and described base 16 is N-type, the mixing of described collecting zone 17, launch site 18 and upper isolation area 15
Miscellany type is p-type.Described collecting zone 17 is surrounded on described base 16, and described base 16 is surrounded on described launch site 18.
It is formed with buried regions 11 and lower isolation area 12, described lower isolation area 12 ring between described substrate 10 and described epitaxial layer 13
It is around in described buried regions 11.Wherein, the doping type of described buried regions 11 is N-type, and the doping type of described lower isolation area 12 is p-type.
Described Shen Lin area 14 is connected with described buried regions 11, and described upper isolation area 15 is connected with described lower isolation area 12.It can be seen that, described on every
The isolation structure area being formed from area 15 and the combination of described lower isolation area 12 is surrounded on the deep phosphorus above described buried regions 11 and buried regions 11
Area 14, base 16, collecting zone 17 and launch site 18.
As shown in figure 13, described epitaxial layer 13 is formed with the first interlayer dielectric layer 19 and voltage modulation dielectric layer 20, institute
State and the first interconnection line 21 is formed with the first interlayer dielectric layer 19 and voltage modulation dielectric layer 20.Wherein, voltage modulation dielectric layer
20 are located at the upper of described base 16 and cover whole base 16, and described first interlayer dielectric layer 19 corresponds to described Shen Lin area 14, collection
The region of electric area 17 and launch site 18 is formed with the first contact hole, and the first interconnection line 21 passes through the first contact hole and described Shen Lin area
14th, collecting zone 17 and launch site 18 connect, and realize the electrical extraction of described Shen Lin area 14 and collecting zone 17.Base 16 then passes through outer
Prolong floor 13 and Shen Lin area 14 and then be electrically connected with the first interconnection line 21, thus realizing the electrical extraction of described base 16.Meanwhile,
The region of the corresponding described base 14 of described first interlayer dielectric layer 19 is formed with voltage modulation dielectric layer window, described voltage modulation
Dielectric layer 20 is formed in described voltage modulation dielectric layer window, and described first interconnection line 21 is covered in described voltage modulation medium
Layer 20 on and realize voltage become dielectric layer 20 electrical extraction.In the present embodiment, described voltage modulation dielectric layer 20 includes dioxy
SiClx layer and silicon nitride layer, described silicon nitride layer is covered in described silicon dioxide layer, and described first interconnection line 21 is covered in institute
State on silicon nitride layer.Described silicon dioxide layer thickness is 150 angstroms～800 angstroms, and described silicon nitride layer thickness is 300 angstroms～1800
Angstrom.
As shown in figure 13, described first interlayer dielectric layer 19 and the first interconnection line 21 are formed with the second interlayer dielectric layer
22.It is formed with the second interconnection line 23 on described second interlayer dielectric layer 22, and, described second interlayer dielectric layer 22 corresponds to institute
The region stating launch site 18 is formed with the second contact hole, and described second interconnection line 23 passes through the second contact hole and positioned at launch site 18
On the first interconnection line 21 connect, realize the electrical extraction of described launch site 18.
As shown in figure 13, described bipolar PNP transistor 100 also includes：It is formed at described second interlayer dielectric layer and second
Passivation layer 24 on interconnection line.Described passivation layer 24 is preferably the composite construction of silicon nitride layer or silicon nitride containing layer, described nitridation
Silicon layer can effectively stop extraneous mobile ion, steam etc. from entering voltage modulation dielectric layer 20 it is ensured that voltage modulation dielectric layer
20 are not subject to external influence, realize the long-term preservation of charge inducing quantity.
Described bipolar PNP transistor 100 may further include the lightly-doped layer 25 being formed on described epitaxial layer 13, institute
The doping type stating lightly-doped layer 25 is N-type.Described lightly-doped layer 25 is located at the surface of described epitaxial layer 13, its doping content one
As than the doping content of epitaxial layer 13 high an order of magnitude.The doping content of described lightly-doped layer 25 is generally 1E16cm-2~
4E16cm-2, its effect is the horizontal proliferation of suppression collecting zone 17, launch site 18 and upper isolation area 15, increases collecting zone 17, transmitting
Coverage between area 18 and upper isolation area 15, realizes the manufacture of small area transistor.Meanwhile, described lightly-doped layer 25 is favourable
In improving the parasitic fields cut-in voltage under the first interconnection line in two-layer wiring, to avoid ghost effect to affect the normal work of transistor
Make.
In bipolar PNP transistor 100 provided in an embodiment of the present invention, above base 16, it is coated with voltage modulation medium
Layer 20, described voltage modulation dielectric layer 20 is realized electrically drawing by the first interconnection line 21.Described voltage modulation dielectric layer 20 wraps
Include silicon dioxide layer and be formed at the silicon nitride layer in described silicon dioxide layer.Wherein, the nitridation of voltage modulation dielectric layer 20
Silicon layer has charge storage ability, and intensified negative pressure can reduce the negative charge ratio of silicon nitride layer, increases malleation and can recover nitrogen again
The negative charge ratio of SiClx layer, therefore increases forward and reverse potential pulse by the first interconnection line 21, thus it is possible to vary voltage modulation is situated between
Charge inducing quantity in matter layer 20.Simultaneously as the normal working voltage of PNP pipe more than on voltage modulation dielectric layer 20 plus
Positive and negative pulse voltage is low, can stable for extended periods of time by this charge inducing quantity.Because bipolar process manufactures bipolar PNP transistor
Small current amplification affected by the concentration of electric charges of base region surface, therefore change charge inducing quantity enable to base 16
The concentration of electric charges on surface changes, and then changes the electric leakage ditch between the base 16 of bipolar PNP transistor and collecting zone 17
Road.It can be seen that, by changing the charge inducing quantity in voltage modulation dielectric layer 20, described bipolar PNP transistor 100 can be controlled
Base 16 and collecting zone 17 between electric leakage raceway groove, change amplification under small current for the bipolar PNP transistor 100.
Accordingly, the present embodiment additionally provides a kind of manufacture method of bipolar PNP transistor.Refer to Fig. 1, and combine figure
2 to Figure 13, the manufacture method of described bipolar PNP transistor comprises the following steps：
S10：One substrate 10 is provided；
S11：Epitaxial layer 13 is formed on described substrate 10；
S12：Shen Lin area 14, base 16, collecting zone 17 and launch site 18 is sequentially formed in described epitaxial layer 13；
S13：First interlayer dielectric layer 19 and voltage modulation dielectric layer 20 are sequentially formed on described epitaxial layer 13；
S14：Described first interlayer dielectric layer 19 and voltage modulation dielectric layer 20 form the first interconnection line 21；
S15：Described first interlayer dielectric layer 19 and the first interconnection line 21 form the second interlayer dielectric layer 22；
S16：Described second interlayer dielectric layer 22 forms the second interconnection line 23；
Wherein, described voltage modulation dielectric layer 20 is covered on described base 16, and real by described first interconnection line 21
Now electrically draw.
Specifically, as shown in Fig. 2 first, provide a substrate 10, it is p-type and crystal orientation that described substrate 10 adopts doping type
For<111>Silicon substrate, the scope of its resistivity is 10 Ω cm～20 Ω cm.
Then, as shown in figure 3, forming buried regions 11 and lower isolation area 12, described lower isolation area 12 ring in described substrate 10
Around with described buried regions 11.Wherein, the doping type of described buried regions 11 is N-type, and the doping type of described lower isolation area 12 is p-type.
Then, as shown in figure 4, epitaxial layer 13, described epitaxial layer are formed by epitaxial growth technology on described substrate 10
13 doping type is N-type.Match for convenience of the platform with existing little regular dipole technique, the thickness of described epitaxial layer 13
It is preferably controlled between 2.5 μm to 4 μm, the scope of its resistivity is 1.0 Ω cm～2.2 Ω cm, buried regions 11 and lower isolation
Area 12 is located between described substrate 10 and epitaxial layer 13.
Then, gently mix as shown in figure 5, can be formed on described epitaxial layer 13 using high-energy low dose field injection technology
Diamicton 25, the doping type of described lightly-doped layer 25 is N-type.The processing step forming lightly-doped layer 25 can form epitaxial layer
It is also possible to before forming launch site and collecting zone after isolation area on being formed at, change before forming Shen Lin area 14 after 13
The precedence of this technique has no effect on structure and the performance of device.Described lightly-doped layer 25 is located at the table of described epitaxial layer 13
Face, its doping content high an order of magnitude typically than the doping content of epitaxial layer 13.In the present embodiment, described lightly-doped layer 25
Doping content is 1E16cm-2～4E16cm-2.The effect of described lightly-doped layer 25 be suppression subsequent technique in collecting zone 17, send out
Penetrate area 18 and the horizontal proliferation of upper isolation area 15, increase the coverage between collecting zone 17, launch site 18 and upper isolation area 15,
Realize the manufacture of small area transistor.Meanwhile, described lightly-doped layer 25 is conducive to improving under the first interconnection line in two-layer wiring
Parasitic fields cut-in voltage, to avoid ghost effect to affect the normal work of transistor.
As shown in fig. 6, formed lightly-doped layer 25 after, in described epitaxial layer 13 formed Shen Lin area 14, on isolation area 15,
Base 16, collecting zone 17 and launch site 18.In the present embodiment, Shen Lin area 14, upper isolation area 15, base 16 can be sequentially formed, so
Form collecting zone 17 and launch site 18, or the formation order requiring adjustment said structure according to concrete technology afterwards simultaneously.Wherein,
The doping type of described Shen Lin area 14 and described base 16 is N-type, the mixing of described collecting zone 17, launch site 18 and upper isolation area 15
Miscellany type is p-type, and, around described base 16, described base 16 is around described launch site 18, described Shen Lin area for described collecting zone 17
14 are connected with described buried regions 11, and described in described upper isolation area 15, lower isolation area 12 connects.It can be seen that, described upper isolation area 15 and described
The isolation structure area that the combination of lower isolation area 12 is formed be surrounded on Shen Lin area 14 above described buried regions 11 and buried regions 11, base 16,
Collecting zone 17 and launch site 18.
Then, as shown in Figure 7 and Figure 8, the first interlayer dielectric layer 19 and voltage are sequentially formed on described lightly-doped layer 25
Modulation dielectric layer 20.Described voltage modulation dielectric layer 20 includes silicon dioxide layer（SiO2）Be formed in described silicon dioxide layer
Silicon nitride layer（SiN）, preferably 150 angstroms～800 angstroms of described silicon dioxide layer thickness, described silicon nitride layer thickness is preferably
300 angstroms～1800 angstroms.
As shown in figure 9, after forming voltage modulation dielectric layer 20, the first interlayer dielectric layer 19 forming multiple first and connects
Contact hole.The plurality of first contact hole is located at described Shen Lin area 14 respectively, on collecting zone 17 and launch site 18.
As shown in Figure 10, after forming the first contact hole, in described first interlayer dielectric layer 19 and voltage modulation dielectric layer
Form the first interconnection line 21 on 20.Described first interconnection line 21 is covered on described voltage modulation dielectric layer 20, and passes through first
Contact hole is electrically connected with described Shen Lin area 14, collecting zone 17 and launch site 18, realizes described Shen Lin area 14 and collecting zone 17
Electrically draw, base 16 is then passed through epitaxial layer 13 and Shen Lin area 14 and then is electrically connected with the first interconnection line 21.Meanwhile, described
One interconnection line 21 is covered on described voltage modulation dielectric layer 20 and realizes the electrical extraction that voltage becomes dielectric layer 20.
In the present embodiment, the silicon dioxide layer in voltage modulation dielectric layer 20 is directly to be covered in described lightly-doped layer 25
On, silicon nitride layer is connected with described first interconnection line 21 and is completely covered by the first interconnection line 21.Other enforcements in the present invention
It is also possible to not form lightly-doped layer 25 in example, in described epitaxial layer 13, directly form Shen Lin area after forming epitaxial layer 13
14th, upper isolation area 15, base 16, collecting zone 17 and launch site 18, then sequentially forms the first interlayer on described epitaxial layer 13
Dielectric layer 19 and voltage modulation dielectric layer 20.Wherein, described voltage modulation dielectric layer 20 is located above described base 16 simultaneously directly
Connect the whole base 16 of covering, the silicon dioxide layer in described voltage modulation dielectric layer 20 is connected with described base 16.
As shown in figure 11, then, the second interlayer is formed on described first interlayer dielectric layer 19 and the first interconnection line 21 be situated between
Matter layer 22, after forming the second interlayer dielectric layer 22, the region in the corresponding launch site 18 of the second interlayer dielectric layer 22 forms second and connects
Contact hole.Second interlayer dielectric layer 22 covers the first interlayer dielectric layer 19 and the first interconnection line 21, and described second contact hole is located at institute
State above launch site 18.
As shown in figure 12, form the second interconnection line on described second interlayer dielectric layer 22 after forming the second contact hole
23.Described second interconnection line 23 is connected with the first interconnection line 21 on described launch site 18 by the second contact hole, realizes described
The electrical extraction of launch site 18.
As shown in figure 13, finally, passivation layer 24 is formed on described second interlayer dielectric layer 22 and the second interconnection line 23.Institute
State passivation layer 24 to be covered on the second interlayer dielectric layer 22 and the second interconnection line 23, described passivation layer 24 is silicon nitride layer or nitrogenous
The composite construction of SiClx layer, described silicon nitride layer can effectively stop extraneous mobile ion, steam etc. from entering voltage modulation and be situated between
Matter layer 20, it is ensured that voltage modulation dielectric layer 20 is not subject to external influence, realizes the long-term preservation of charge inducing quantity.
According to the manufacture method of bipolar PNP transistor provided in an embodiment of the present invention, the bipolar PNP transistor 100 of formation
Voltage modulation dielectric layer 20 is formed with base 16, described voltage modulation dielectric layer 20 is drawn by the first interconnection line 21.Will
Base is grounded, and increases forward and reverse potential pulse, thus it is possible to vary in voltage modulation dielectric layer 20 on the first interconnection line 21 is drawn
Charge inducing quantity, the change of charge inducing quantity can make the electric charge on base 16 surface below voltage modulation dielectric layer 20 dense
Degree changes, and the concentration of electric charges on base 16 surface determines the electric leakage raceway groove between base 16 and collecting zone 17, therefore, passes through
Change the charge inducing quantity in voltage modulation dielectric layer 20, the small current of described bipolar PNP transistor 100 can be controlled to amplify
Multiple.Further, since the normal working voltage of PNP pipe is low more than the positive and negative pulse voltage adding on voltage modulation dielectric layer 20,
Charge inducing quantity can keep constant for a long time so that the small current amplification fluctuation of described bipolar PNP transistor is smaller.
To sum up, in bipolar PNP transistor provided in an embodiment of the present invention and its manufacture method, in traditional bipolar process
On the basis of add the structure of silicon nitride layer by silicon dioxide layer is formed on the base of described bipolar PNP transistor, using described
The charge storage ability of silicon nitride layer, affects the concentration of electric charges of base region surface by changing charge inducing quantity, and then realizes
Small current amplification is adjustable.
Foregoing description is only the description to present pre-ferred embodiments, not any restriction to the scope of the invention, this
Any change that the those of ordinary skill in bright field does according to the disclosure above content, modification, belong to the protection of claims
Scope.
Claims (18)
1. a kind of bipolar PNP transistor is it is characterised in that include：
Substrate；
It is formed at the epitaxial layer on described substrate；
It is formed at described epitaxial layer Zhong Shenlin area, base, collecting zone and launch site；
It is formed at the first interlayer dielectric layer on described epitaxial layer and voltage modulation dielectric layer；
It is formed at the first interconnection line on described first interlayer dielectric layer and voltage modulation dielectric layer；
It is formed at the second interlayer dielectric layer on described first interlayer dielectric layer and the first interconnection line；
It is formed at the second interconnection line on described second interlayer dielectric layer；
Wherein, the silicon nitride layer that described voltage modulation dielectric layer includes silicon dioxide layer and is formed in described silicon dioxide layer,
Described first interconnection line covers described silicon nitride layer；Described voltage modulation dielectric layer is covered on described base, and by described
First interconnection line is realized electrically drawing, and can make described base by changing the charge inducing quantity in described voltage modulation dielectric layer
The concentration of electric charges on area surface changes.
2. bipolar PNP transistor as claimed in claim 1 is it is characterised in that described collecting zone is surrounded on described base, described
Base is surrounded on described launch site；Described first interconnection line is connected with described Shen Lin area, launch site and collecting zone, is used for realizing institute
The electrical extraction of Shu Shenlin area, collecting zone and base；Described second interconnection line is connected with the first interconnection line on described launch site,
For realizing the electrical extraction of described launch site.
3. bipolar PNP transistor as claimed in claim 1 it is characterised in that described silicon dioxide layer thickness be 150～
800 angstroms, the thickness of described silicon nitride layer is 300 angstroms～1800 angstroms.
4. bipolar PNP transistor as claimed in claim 1 it is characterised in that described epitaxial layer thickness be 2.5 μm～4 μm,
The resistivity of described epitaxial layer is 1.0 Ω cm～2.2 Ω cm.
5. bipolar PNP transistor as claimed in claim 1 is it is characterised in that also include being formed at described substrate and epitaxial layer
Between buried regions and lower isolation area, described lower isolation area is connected with described buried regions around described buried regions, described Shen Lin area.
6. bipolar PNP transistor as claimed in claim 5 is it is characterised in that also include the upper isolation being formed in epitaxial layer
Area, described upper isolation area is connected with described lower isolation area.
7. bipolar PNP transistor as claimed in claim 6 is it is characterised in that also include being formed at described epi-layer surface
Lightly-doped layer, the doping content of described lightly-doped layer high an order of magnitude than the doping content of epitaxial layer.
8. bipolar PNP transistor as claimed in claim 7 it is characterised in that described substrate, lower isolation area, upper isolation area, send out
Penetrate area and the doping type of collecting zone is p-type, described epitaxial layer, buried regions, the doping type of lightly-doped layer, Shen Lin area and base
It is N-type.
9. bipolar PNP transistor as claimed in claim 1 is it is characterised in that also include being formed at described second inter-level dielectric
Passivation layer on layer and the second interconnection line.
10. a kind of manufacture method of bipolar PNP transistor is it is characterised in that include：
One substrate is provided；
Form epitaxial layer over the substrate；
Form Shen Lin area, base, collecting zone and launch site in described epitaxial layer；
Form the first interlayer dielectric layer and voltage modulation dielectric layer on said epitaxial layer there；
Described first interlayer dielectric layer and voltage modulation dielectric layer form the first interconnection line；
Described first interlayer dielectric layer and the first interconnection line form the second interlayer dielectric layer；
Described second interlayer dielectric layer forms the second interconnection line；
Wherein, the silicon nitride layer that described voltage modulation dielectric layer includes silicon dioxide layer and is formed in described silicon dioxide layer,
Described first interconnection line covers described silicon nitride layer；Described voltage modulation dielectric layer is covered on described base, and by described
First interconnection line is realized electrically drawing, and can make described base by changing the charge inducing quantity in described voltage modulation dielectric layer
The concentration of electric charges on area surface changes.
The manufacture method of 11. bipolar PNP transistor as claimed in claim 10 is it is characterised in that described collecting zone is surrounded on
Described base, described base is surrounded on described launch site；Described first interconnection line is with described Shen Lin area, launch site and collecting zone even
Connect, for realizing the electrical extraction of described Shen Lin area, collecting zone and base, described second interconnection line with described launch site
First interconnection line connect, for realizing the electrical extraction of described launch site.
The manufacture method of 12. bipolar PNP transistor as claimed in claim 10 is it is characterised in that described silicon dioxide thickness
Spend for 150～800 angstroms, described silicon nitride layer thickness is 300～1800 angstroms.
The manufacture method of 13. bipolar PNP transistor as claimed in claim 10 is it is characterised in that the thickness of described epitaxial layer
For 2.5 μm～4 μm, the resistivity of described epitaxial layer is 1.0 Ω cm～2.2 Ω cm.
The manufacture method of 14. bipolar PNP transistor as claimed in claim 10 is it is characterised in that forming described epitaxial layer
Before, it is additionally included in described substrate and sequentially forms buried regions and lower isolation area, described lower isolation area is around described buried regions, described depth
Phosphorus area is connected with described buried regions.
The manufacture method of 15. bipolar PNP transistor as claimed in claim 14 it is characterised in that after forming epitaxial layer,
The surface being additionally included in described epitaxial layer forms lightly-doped layer, and the doping content of described lightly-doped layer is than the doping content of epitaxial layer
High an order of magnitude.
The manufacture method of 16. bipolar PNP transistor as claimed in claim 15 it is characterised in that before forming base,
After forming lightly-doped layer, it is additionally included in described epitaxial layer and forms upper isolation area, described upper isolation area and described lower isolation area
Connect.
The manufacture method of 17. bipolar PNP transistor as claimed in claim 16 is it is characterised in that described substrate, lower isolation
Area, the doping type of upper isolation area, launch site and collecting zone are p-type, described epitaxial layer, buried regions, lightly-doped layer, Shen Lin area and
The doping type of base is N-type.
The manufacture method of 18. bipolar PNP transistor as claimed in claim 10 is it is characterised in that forming the second interconnection line
Afterwards, it is additionally included in formation passivation layer on described second interlayer dielectric layer and the second interconnection line.
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| CN87102851A (en) * | 1987-04-17 | 1988-05-25 | 无锡微电子联合公司 | Gate-controlled semiconductor tetrode |
| CN1838413A (en) * | 2005-03-25 | 2006-09-27 | 冲电气工业株式会社 | Semiconductor integrated circuit |
| CN1996571A (en) * | 2006-12-04 | 2007-07-11 | 中国电子科技集团公司第二十四研究所 | A making method for the integration circuit of the CMOS low-voltage difference adjustor |
| CN102637725A (en) * | 2012-04-26 | 2012-08-15 | 杭州士兰集成电路有限公司 | Device accomplished by adopting Bipolar low-pressure process and manufacturing method thereof |
| CN203631560U (en) * | 2013-12-10 | 2014-06-04 | 杭州士兰集成电路有限公司 | Bipolar NPN transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN87102851A (en) * | 1987-04-17 | 1988-05-25 | 无锡微电子联合公司 | Gate-controlled semiconductor tetrode |
| CN1838413A (en) * | 2005-03-25 | 2006-09-27 | 冲电气工业株式会社 | Semiconductor integrated circuit |
| CN1996571A (en) * | 2006-12-04 | 2007-07-11 | 中国电子科技集团公司第二十四研究所 | A making method for the integration circuit of the CMOS low-voltage difference adjustor |
| CN102637725A (en) * | 2012-04-26 | 2012-08-15 | 杭州士兰集成电路有限公司 | Device accomplished by adopting Bipolar low-pressure process and manufacturing method thereof |
| CN203631560U (en) * | 2013-12-10 | 2014-06-04 | 杭州士兰集成电路有限公司 | Bipolar NPN transistor |
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Effective date of registration: 20180312 Address after: 610404 in the Central Development Zone of ABA industry in Chengdu, Sichuan Patentee after: Chengdu Silan Semiconductor Manufacturing Co., Ltd. Address before: Hangzhou City, Zhejiang province 310018 (Hangzhou Xiasha) No. 10 East Road, economic and Technological Development Zone No. 308 Patentee before: Hangzhou Silan Integrated Circuit Co., Ltd. |