CN203574687U - PowerPC signal data switching board - Google Patents
PowerPC signal data switching board Download PDFInfo
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- CN203574687U CN203574687U CN201320767512.1U CN201320767512U CN203574687U CN 203574687 U CN203574687 U CN 203574687U CN 201320767512 U CN201320767512 U CN 201320767512U CN 203574687 U CN203574687 U CN 203574687U
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- srio switch
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- 230000005540 biological transmission Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 239000004606 Fillers/Extenders Substances 0.000 description 1
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- 238000001914 filtration Methods 0.000 description 1
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Abstract
The utility model discloses a PowerPC signal data switching board which comprises a back board bus. The back board bus is connected with an FPGA, a first SRIOSWITCH and a second SRIOSWITCH. The first SRIOSWITCH and the second SRIOSWITCH are connected in series. The FPGA and the first SRIOSWITCH are connected with a PPC. The PPC is connected with a PHY chip, a Uart, a DDR2SARAM and a NORFLASH memory. The PowerPC signal data switching board provided by the utility model has the advantages of fast data switching speed, low power consumption and high stability and reliability.
Description
Technical field
The utility model relates to a kind of signal data power board, relates in particular a kind of PowerPC signal data power board.
Background technology
Handshaking technology is increasingly mature now, has occurred various signal exchange devices, and the common router in life is exactly a kind of data switching exchane; At some special dimensions, need to meet very high exchange velocity and signal precision as radar communication, navigation and aerospace switch, and because equipment is more, also need a plurality of different ports to carry out exchanges data, this just needs switching equipment to have the support of very high exchanges data speed, stability and multiport, for this reason, we have designed a kind of high speed and stable signal data exchange mainboard.
Utility model content
The utility model provides a kind of PowerPC signal data power board, has solved in the past that signal data exchange velocity is slow, stability and poor reliability problem.
For solving above-mentioned technical problem, the utility model is by the following technical solutions: a kind of PowerPC signal data power board, comprise core bus, core bus is connected with FPGA, a SRIO SWITCH and the 2nd SRIO SWITCH, a described SRIO SWITCH and the 2nd SRIO SWITCH are connected in series mutually, described FPGA and a SRIO SWITCH are also connected with PPC, are connected with PHY chip, Uart, DDR2 SARAM and NOR FLASH memory on PPC.
Described FPGA is connected with DDR2 SARAM and GPIO.
Described FPGA model is XC6SLX100.
Described PPC model is MPC8548E.
A described SRIO SWITCH and the 2nd SRIO SWITCH all adopt TSI578 type SRIO SWITCH.
A described SRIO SWITCH adopts SRIO interface to be connected with the 2nd SRIO SWITCH, and described PPC is all connected by SRIO interface with backboard with the 2nd SRIO SWITCH with a SRIO SWITCH, a SRIO SWITCH.
Compared with prior art, the beneficial effects of the utility model are: this PowerPC signal data power board of the utility model design, not only have advantages of that exchanges data speed is fast, low in energy consumption, and stability and reliability high.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.
Fig. 1 is structural representation of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, the utility model is further described.
Embodiment 1
A kind of PowerPC signal data power board as shown in Figure 1, comprise core bus, core bus is connected with FPGA, a SRIO SWITCH and the 2nd SRIO SWITCH, a described SRIO SWITCH and the 2nd SRIO SWITCH are connected in series mutually, described FPGA and a SRIO SWITCH are also connected with PPC, are connected with PHY chip, Uart, DDR2 SARAM and NOR FLASH memory on PPC.
In the present embodiment, FPGA is field programmable gate array; SRIO SWITCH is SRIO SWITCH ZD power board; PPC is PowerPC, is a kind of CPU of RISC framework; PHY chip is ethernet PHY chip; Uart is universal asynchronous receiving-transmitting transmitter; DDR2 SDRAM is random access memory.
The present embodiment signal enters PPC by Uart and PHY chip, by PPC, carry out signal processing, and carry out exchanges data by two SRIO SWITCH that are mutually connected in series, can realize two SRIO SWITCH and carry out swap data respectively, simultaneously, and two SRIO SWITCH can exchange data jointly, improve exchange velocity and accuracy, and swap data is selected through FPGA and is carried out filtering processing, make signal more stable and accurate, realized the high speed of data and precisely exchange, practicality greatly improves.
Embodiment 2
The present embodiment has increased following structure on the basis of embodiment 1: described FPGA is connected with DDR2 SARAM and GPIO.
In the present embodiment, the DDR2 SARAM of FPGA can realize data storages or redundancy backup, and a plurality of DDR2 SARAM can be set, and GPIO(is bus extender) can realize the multithreading output of data, the data of being convenient to a plurality of equipment are used.
Embodiment 3
The present embodiment has been optimized FPGA on the basis of embodiment 1 or embodiment 2, is specially: described FPGA model is XC6SLX100.
XC6SLX100 superior performance in the present embodiment, cost and low in energy consumption, processing speed is fast, can well realize signal and process, and reduces energy consumption simultaneously.
Embodiment 4
The present embodiment is further optimized on the basis of embodiment 3, is specially: described PPC model is MPC8548E.
In the present embodiment, MPC8548E is with two pci controllers, and MPC8548E cost performance is high, and temperature range of operation is large, compatible good, reliable and stable, and processing speed piece is low in energy consumption, can improve stability and the reliability of handshaking.
Embodiment 5
The present embodiment has been done following optimization on the basis of above-mentioned arbitrary embodiment: a described SRIO SWITCH and the 2nd SRIO SWITCH all adopt TSI578 type SRIO SWITCH.
The TSI578 type SRIO SWITCH of the present embodiment has the advantages that speed is fast, energy consumption is low, and energy flexible configuration various port, meets multiport needs, and exchanges data is accurate.
Embodiment 6
Embodiment 6 is optimum embodiment of the present utility model
The present embodiment has been done following optimization on the basis of above-mentioned arbitrary embodiment, be specially: a described SRIO SWITCH adopts SRIO interface to be connected with the 2nd SRIO SWITCH, and described PPC is all connected by SRIO interface with backboard with the 2nd SRIO SWITCH with a SRIO SWITCH, a SRIO SWITCH.
In the present embodiment, SRIO is writing a Chinese character in simplified form of Serial Rapid I/O, be towards serial backplane, DSP and relevant serial data plane, to be connected the serial RapidIO interface of application, there is reliable high-performance advantage, can realize multicast communication, transmission speed piece, can improve whole data transmission rate.
Be as mentioned above embodiment of the present utility model.The utility model is not limited to above-mentioned execution mode, and anyone should learn the structural change of making under enlightenment of the present utility model, every with the utlity model has identical or close technical scheme, within all falling into protection range of the present utility model.
Claims (6)
1. a PowerPC signal data power board, comprise core bus, it is characterized in that: core bus is connected with FPGA, a SRIO SWITCH and the 2nd SRIO SWITCH, a described SRIO SWITCH and the 2nd SRIO SWITCH are connected in series mutually, described FPGA and a SRIO SWITCH are also connected with PPC, are connected with PHY chip, Uart, DDR2 SARAM and NOR FLASH memory on PPC.
2. a kind of PowerPC signal data power board according to claim 1, is characterized in that: described FPGA is connected with DDR2 SARAM and GPIO.
3. a kind of PowerPC signal data power board according to claim 1, is characterized in that: described FPGA model is XC6SLX100.
4. a kind of PowerPC signal data power board according to claim 1, is characterized in that: described PPC model is MPC8548E.
5. a kind of PowerPC signal data power board according to claim 1, is characterized in that: a described SRIO SWITCH and the 2nd SRIO SWITCH all adopt TSI578 type SRIO SWITCH.
6. a kind of PowerPC signal data power board according to claim 1, it is characterized in that: a described SRIO SWITCH adopts SRIO interface to be connected with the 2nd SRIO SWITCH, and described PPC is all connected by SRIO interface with backboard with the 2nd SRIO SWITCH with a SRIO SWITCH, a SRIO SWITCH.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320767512.1U CN203574687U (en) | 2013-11-29 | 2013-11-29 | PowerPC signal data switching board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320767512.1U CN203574687U (en) | 2013-11-29 | 2013-11-29 | PowerPC signal data switching board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203574687U true CN203574687U (en) | 2014-04-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201320767512.1U Expired - Lifetime CN203574687U (en) | 2013-11-29 | 2013-11-29 | PowerPC signal data switching board |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103685076A (en) * | 2013-11-29 | 2014-03-26 | 成都国蓉科技有限公司 | Signal data exchange board |
-
2013
- 2013-11-29 CN CN201320767512.1U patent/CN203574687U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103685076A (en) * | 2013-11-29 | 2014-03-26 | 成都国蓉科技有限公司 | Signal data exchange board |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 610000 No. 2 Tianyu Road, hi tech Zone, Sichuan, Chengdu Patentee after: GUORONG TECHNOLOGY CO.,LTD. Address before: 610000 No. 2 Tianyu Road, hi tech Zone, Sichuan, Chengdu Patentee before: CHENGDU GUORONG TECHNOLOGY Co.,Ltd. |
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| CP01 | Change in the name or title of a patent holder | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140430 |
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| CX01 | Expiry of patent term |