CN202870817U

CN202870817U - Embedded system based on two digital signal processors (DSPs) and 1553B bus interface

Info

Publication number: CN202870817U
Application number: CN201220596295XU
Authority: CN
Inventors: 何志宏; 王群
Original assignee: Hunan Aerospace Institute of Mechanical and Electrical Equipment and Special Materials
Current assignee: Hunan Aerospace Institute of Mechanical and Electrical Equipment and Special Materials
Priority date: 2012-11-13
Filing date: 2012-11-13
Publication date: 2013-04-10
Anticipated expiration: 2022-11-13

Abstract

The utility model discloses an embedded system based on two digital signal processors (DSPs) and a 1553B bus interface. The embedded system based on the two DSPs and the 1553B bus interface comprises a plurality of synchronous dynamic random access memories (SDRAMs), a plurality of flash memories, a field programmable gate array (FPGA) chip, a 1553B bus controller and the two DSPs. The two DSPs, the SDRAMs and the flash memories are all connected with the FPGA chip through DSP buses. The FPGA chip is in bidirectional connection with the 1553B bus controller. The embedded system based on the two DSPs and the 1553B bus interface combines strong data handling capacity of the DSPs, flexibility of an FPGA, and distributed processing, centralized control and real-time response characteristics of a 1553B bus, and therefore the embedded system is high in integration level and processing speed and strong in universality and expandability.

Description

A kind of embedded system based on two DSP and 1553B bus interface

Technical field

The utility model relates to a kind of embedded system, particularly a kind of embedded system based on two DSP and 1553B bus interface.

Background technology

Modern aerospace system inner electronic equipment gets more and more, becomes increasingly complex, the digitizing of armament systems, the level of informatization are also in rapid improve, be starved of between the various device in the system and obtain to have high transfer rate, the data interconnection mode of the high efficiency of management and high reliability.The MIL-STD-1553B bus has higher data transmission performance and the efficiency of management, a reliable data bus of transmission as a kind of, developed into unitized data transmission technology very ripe and that be widely used, widespread use in the systems such as Aero-Space, weaponry.The effect of 1553B bus interface adapter is to build a bridge block between 1553B bus and existing other bussing techniques so that the information flow of different systems can be in real time, change mutually exactly.In the development of 1553B bus interface adapter, complicated and harsh environment has proposed very high requirement to real-time and the reliability of central processing unit.Existing single DSP embedded system reliability is not high, and power consumption is large, and Universal and scalability is not strong.

Summary of the invention

Technical problem to be solved in the utility model is for the prior art deficiency, to provide a kind of embedded system based on two DSP and 1553B bus interface, raising level of integrated system, processing speed, Universal and scalability.

For solving the problems of the technologies described above, the technical scheme that the utility model adopts is: a kind of embedded system based on two DSP and 1553B bus interface, comprise several SDRAM storeies, several FLASH storeies, also comprise fpga chip, 1553B bus controller and two dsp processors, described two dsp controllers, SDRAM storer, FLASH storer all are connected with described fpga chip by dsp bus, described fpga chip and described two-way connection of 1553B bus controller.

Compared with prior art, the beneficial effect that the utility model has is: the characteristics of the dirigibility of the utility model data-handling capacity that DSP is powerful, FPGA and distribution process, centralized control and the real-time response of 1553B bus combine, the utility model level of integrated system is high, processing speed is fast, and Universal and scalability is stronger.

Description of drawings

Fig. 1 is the utility model one example structure block diagram.

Embodiment

As shown in Figure 1, the utility model one embodiment comprises two SDRAM storeies, two FLASH storeies, also comprise fpga chip, 1553B bus controller and two dsp processors, described two dsp controllers, two SDRAM storeies, two FLASH storeies all are connected with described fpga chip by dsp bus, described fpga chip and described two-way connection of 1553B bus controller; Described 1553B bus controller is by two isolating transformer access missile-borne computers.

During practical application, this embedded system timing output system synchronization clock signal cooperates with flight control computer (machine on the bullet), the control of completion system synchronous acquisition.Fpga chip is by isolating chip, the two-way difference controller access inner and outer ring circuit for controlling motor of RS485 and temperature control circuit; Fpga chip is by the first level transferring chip, the first optocoupler receiving chip, the first difference buffer circuit access ground observing and controlling system; FPGA also is connected to high-capacity FLASH and UART protocol chip; The fpga chip input end is connected with signal acquisition circuit by second electrical level conversion chip, the second optocoupler receiving chip and the difference buffer circuit of being connected; Fpga chip is by the 3rd level transferring chip, the 3rd difference buffer circuit access missile-borne computer.

Embedded system of the present utility model and flight control computer 1553B bus communication; Pass through the RS422 serial bus communication with signal acquisition circuit; Carry out the RS485 serial bus communication with temperature control circuit; By RS485 serial bus control inner and outer ring motor.

Claims

1. embedded system based on two DSP and 1553B bus interface, comprise several SDRAM storeies, several FLASH storeies, it is characterized in that, also comprise fpga chip, 1553B bus controller and two dsp processors, described two dsp controllers, SDRAM storer, FLASH storer all are connected with described fpga chip by dsp bus, described fpga chip and described two-way connection of 1553B bus controller.

2. the embedded system based on two DSP and 1553B bus interface according to claim 1 is characterized in that, described fpga chip is connected to isolating chip, level transferring chip, high-capacity FLASH storer, UART protocol chip.