CN203573315U - Two-channel VPX parallel signal processing module - Google Patents
Two-channel VPX parallel signal processing module Download PDFInfo
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- CN203573315U CN203573315U CN201320767502.8U CN201320767502U CN203573315U CN 203573315 U CN203573315 U CN 203573315U CN 201320767502 U CN201320767502 U CN 201320767502U CN 203573315 U CN203573315 U CN 203573315U
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- 238000005457 optimization Methods 0.000 description 2
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Abstract
The utility model discloses a two-channel VPX parallel signal processing module. The two-channel VPX parallel signal processing module comprises a VPX backplane connector, and a first FPGA (field programmable gate array) and two DSPs (data signal processors) which are connected with the VPX backplane connector, wherein the first FPGA is connected with a second FPGA and a third FPGA; the two DSPs are respectively connected with a DDR2SDRAM (double data rate 2 synchronous dynamic random access memory) and a NORFLASH memory. The two-channel VPX parallel signal processing module disclosed by the utility model is simple in structure, high in signal processing speed and high in stability.
Description
Technical field
The utility model relates to a kind of signal processing module, relates in particular a kind of two passage VPX Parallel Signal Processing Modules.
Background technology
VPX is a kind of new bussing technique, and VPX bus is that VITA (VME International Trade Association, VME international trade association) is organized in the high-speed serial bus standard of new generation proposing on its VME bus basis for 2007.VPX bussing technique is now also gradually for signal process field.
Utility model content
The utility model provides a kind of two passage VPX Parallel Signal Processing Modules, adopts VPX bus to connect various electrical parts, has solved the slow problem of signal processing module processing speed in the past.
For solving above-mentioned technical matters, the utility model is by the following technical solutions: a kind of two passage VPX Parallel Signal Processing Modules, comprise VPX back panel connector and a FPGA who is connected with VPX back panel connector and two DSP, a described FPGA is connected with the 2nd FPGA and the 3rd FPGA, and described two DSP are connected with DDR2 SDRAM and NOR FLASH storer respectively.
Described two DSP are all connected with VPX back panel connector by ethernet PHY chip.
A described FPGA is connected with VPX back panel connector with RS644 interface by serial deserializer respectively.
A described FPGA model is Spartan-6 XC6SLX100, and described the 2nd FPGA and the 3rd FPGA model are XC5VLX50T.
Described two DSP models are TMS320C6455, and described two DSP are all connected with a FPGA by EMIF.
Described the 2nd FPGA is all connected with a FPGA by GPIO with the 3rd FPGA.
Compared with prior art, the beneficial effects of the utility model are: this two passage VPX Parallel Signal Processing Modules of the utility model design, simple in structure, conversion speed is fast.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.
Fig. 1 is structural representation of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, the utility model is further described.
Embodiment 1
A kind of two passage VPX Parallel Signal Processing Modules as shown in Figure 1, comprise VPX back panel connector and a FPGA who is connected with VPX back panel connector and two DSP, a described FPGA is connected with the 2nd FPGA and the 3rd FPGA, and described two DSP are connected with DDR2 SDRAM and NOR FLASH storer respectively.
The present embodiment peripheral Parallel Simulation signal converts digital signal to by two DSP respectively by VPX back panel connector, and modify and strengthen, by DSP, process and be input to a FPGA again, two parallel signals are transported to respectively to the 2nd FPGA to the one FPGA and the 3rd FPGA divides out processing, when guaranteeing treatment capacity, also can avoid data to make mistakes, again the signal after processing is returned in corresponding DSP, and carry out data storage and redundancy backup by DDR2 SDRAM and NOR FLASH storer, storage post-processed signal realizes signal by the output of VPX back panel connector again and processes.DDR2 SDRAM and NOR FLASH storer all can arrange and be used for increasing memory space.
The present embodiment is by adopting VPX bus mode, by VPX back panel connector, realized the connection of each FPGA and DSP and DDR2 SDRAM and NOR FLASH storer, the communication mode of employing VPX bus not only takes full advantage of the performance of FPGA and DSP, and communications is stable, data-handling capacity and travelling speed all increase, and have improved the reliability and stability that signal is processed.
FPGA is field programmable gate array; DSP is microprocessor; DDR2 SDRAM is random access memory.
Embodiment 2
The present embodiment has increased following structure on the basis of embodiment 1: described two DSP are all connected with VPX back panel connector by ethernet PHY chip.
In the present embodiment, for realizing communication, between DSP and VPX back panel connector, connect ethernet PHY chip and be used for realizing network interface communication.
Embodiment 3
The present embodiment has added serial deserializer on the basis of embodiment 1 or embodiment 2, and its concrete structure is: a described FPGA is connected with VPX back panel connector with RS644 interface by serial deserializer respectively.
Serial deserializer in the present embodiment (being SERDES, serializer/de-serializers) is mainly used in supporting the data-signal transmission of long distance, improves stable signal transmission.
Embodiment 4
The present embodiment is further optimized on the basis of embodiment 3, is specially: a described FPGA model is Spartan-6 XC6SLX100, and described the 2nd FPGA and the 3rd FPGA model are XC5VLX50T.
Spartan-6 XC6SLX100 and XC5VLX50T superior performance in the present embodiment, cost and low in energy consumption, processing speed is fast, can well realize signal and process, and reduces energy consumption simultaneously.
Embodiment 5
The present embodiment has been done following optimization on the basis of above-mentioned arbitrary embodiment: described two DSP models are TMS320C6455, and described two DSP are all connected with a FPGA by EMIF.
The TMS320C6455 type DSP of the present embodiment has the advantages that speed is fast, energy consumption is low, have EMIF(is external memory interface simultaneously, External Memory Interface, it is a kind of interface on TMS DSP device,), two DSP are all connected with a FPGA by EMIF, realize the high-speed transfer of signal data.
Embodiment 6
Embodiment 6 is optimum embodiment of the present utility model
The present embodiment has been done following optimization on the basis of above-mentioned arbitrary embodiment, is specially: described the 2nd FPGA is all connected with a FPGA by GPIO with the 3rd FPGA.
The present embodiment is General Purpose Input Output by GPIO(, universal input/output, and referred to as GPIO, or bus extender) realize the connection between FPGA, for simplifying interface.
Be as mentioned above embodiment of the present utility model.The utility model is not limited to above-mentioned embodiment, and anyone should learn the structural change of making under enlightenment of the present utility model, every with the utlity model has identical or close technical scheme, within all falling into protection domain of the present utility model.
Claims (7)
1. a passage VPX Parallel Signal Processing Module, it is characterized in that: comprise VPX back panel connector and a FPGA who is connected with VPX back panel connector and two DSP, a described FPGA is connected with the 2nd FPGA and the 3rd FPGA, and described two DSP are connected with DDR2 SDRAM and NOR FLASH storer respectively.
2. a kind of two passage VPX Parallel Signal Processing Modules according to claim 1, is characterized in that: described two DSP are all connected with VPX back panel connector by ethernet PHY chip.
3. a kind of two passage VPX Parallel Signal Processing Modules according to claim 1, is characterized in that: a described FPGA is connected with VPX back panel connector with RS644 interface by serial deserializer respectively.
4. a kind of two passage VPX Parallel Signal Processing Modules according to claim 1, is characterized in that: a described FPGA model is Spartan-6 XC6SLX100, and described the 2nd FPGA and the 3rd FPGA model are XC5VLX50T.
5. a kind of two passage VPX Parallel Signal Processing Modules according to claim 1, is characterized in that: described two DSP models are TMS320C6455.
6. a kind of two passage VPX Parallel Signal Processing Modules according to claim 1, is characterized in that: described two DSP are all connected with a FPGA by EMIF.
7. a kind of two passage VPX Parallel Signal Processing Modules according to claim 1, is characterized in that: described the 2nd FPGA is all connected with a FPGA by GPIO with the 3rd FPGA.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320767502.8U CN203573315U (en) | 2013-11-29 | 2013-11-29 | Two-channel VPX parallel signal processing module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320767502.8U CN203573315U (en) | 2013-11-29 | 2013-11-29 | Two-channel VPX parallel signal processing module |
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| CN203573315U true CN203573315U (en) | 2014-04-30 |
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| CN201320767502.8U Expired - Lifetime CN203573315U (en) | 2013-11-29 | 2013-11-29 | Two-channel VPX parallel signal processing module |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108881385A (en) * | 2018-05-09 | 2018-11-23 | 南京思达捷信息科技有限公司 | Detection device and its method under a kind of big data |
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2013
- 2013-11-29 CN CN201320767502.8U patent/CN203573315U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108881385A (en) * | 2018-05-09 | 2018-11-23 | 南京思达捷信息科技有限公司 | Detection device and its method under a kind of big data |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 610000 No. 2 Tianyu Road, hi tech Zone, Sichuan, Chengdu Patentee after: GUORONG TECHNOLOGY CO.,LTD. Address before: 610000 No. 2 Tianyu Road, hi tech Zone, Sichuan, Chengdu Patentee before: CHENGDU GUORONG TECHNOLOGY Co.,Ltd. |
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| CP01 | Change in the name or title of a patent holder | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140430 |
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| CX01 | Expiry of patent term |