CN203260575U - Bidirectional symmetrical overvoltage protection device - Google Patents
Bidirectional symmetrical overvoltage protection device Download PDFInfo
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- CN203260575U CN203260575U CN 201320203878 CN201320203878U CN203260575U CN 203260575 U CN203260575 U CN 203260575U CN 201320203878 CN201320203878 CN 201320203878 CN 201320203878 U CN201320203878 U CN 201320203878U CN 203260575 U CN203260575 U CN 203260575U
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Abstract
The utility model provides a bidirectional symmetrical overvoltage protection device. The device comprises a first protection unit, a second protection unit, a lead frame and a packaging shell. Each protection unit comprises an NPN transistor, an NPNP thyristor controlled by the NPN transistor, a PNP transistor and a PNPN thyristor controlled by the PNP transistor; the cathode of the NPNP thyristor and the anode of the PNPN thyristor in the first protection unit are connected to be used as a first access port of the device; the cathode of the NPNP thyristor and the anode of the PNPN thyristor in the second protection unit are connected to be used as a second access port of the device; the bases of the NPN transistors of the first protection unit and the second protection unit are electrically connected to be used as a negative overvoltage reference potential port of the device; and the bases of the PNP transistors of the first protection unit and the second protection unit are electrically connected to be used as a positive overvoltage reference potential port of the device. The device is a semiconductor overvoltage protection device having the advantages of balanced positive and negative overvoltage protection capacities, high flow discharge speed and bidirectional symmetry.
Description
Technical field
The utility model relates to a kind of semiconductor overvoltage protective device, and this device is mainly used to the pronounciation processing chip of stored-program control exchange is implemented effectively protection when impacted by the overvoltages such as thunderbolt, voltage fluctuation.
Background technology
Along with telephone communication network bulky complex day by day, effectively prevent from being struck by lightning, mains fluctuations and electromagnetic induction and destruction that the surge voltage that causes causes communication apparatus is the major issue that these those skilled in the art need to solve always.China has promulgated the anti-lightning strike specification requirement of communications industry telecommunication terminal equipment in 1998, and anti-surge protective device has experienced the spanning development from gas discharge tube to semiconductor overvoltage protective device.
Semiconductor overvoltage protective device speed is fast, good reproducibility, and protection effect is good, be used widely in the last few years, and kind is on the increase, and function is more and more perfect.The main flow overvoltage protective device that is used at present stored-program control exchange is formed be used to the thyristor that negative sense overvoltage protection is provided with for the diode that forward overvoltage protection is provided at same chip usually, this device has structure and the simple advantage of manufacture craft, as shown in Figure 1.But, because the earial drainage speed of diode and discharge capacity not as good as thyristor, cause positive and negative protective capacities and protection speed and the protection effect to overvoltage of whole semiconductor overvoltage protective device asymmetric, unbalanced, as shown in Figure 2.This has restricted the raising of semiconductor overvoltage protective device overall performance and protection effect.The at present semiconductor overvoltage protective device of main flow, such as the available model in market is the overvoltage protective device of TisP61089B, and its protection voltage generally is 2000V.
Therefore, how to overcome in the semiconductor overvoltage protective device of prior art positive and negative unbalancedly to overvoltage protective capability, and the protective capacities and the protection speed that improve on the whole the overvoltage protective device are the technical problems to be solved in the utility model.
The utility model content
The utility model aim to provide a kind of positive and negative balanced to overvoltage protective capability, earial drainage speed fast, the semiconductor overvoltage protective device of bi-directional symmetrical.
For realizing this goal, the technical scheme that the utility model is taked is: in view of present main flow semiconductor overvoltage protective device for example the available model in market be the structural defect that the overvoltage protective device of TisP61089B exists, replace the diode of undertaking forward overvoltage protection with thyristor, thereby form one and undertake negative sense overvoltage protection by NPN transistor and by the combination of the NPNP thyristor of its control, undertake forward overvoltage protection by a PNP transistor and by the PNPN thyristor combination of its control in addition, the two combination, just form one, the protective unit that negative sense overvoltage protection cooperates thyristor to realize by transistor, the discharge capacity of diode and the defective that earial drainage speed is weaker than thyristor have so just effectively been overcome, just realize the overvoltage protective device, the negative sense overvoltage protective capability is symmetrical, balanced target, effectively improve whole discharge capacity and the earial drainage speed of device, so that resist wear voltage for example its anti-lightning voltage capability can reach 4500V, earial drainage speed can adapt to the quick waveform that rising edge/trailing edge is 8/20 microsecond.
By each element electrical parameter of reasonable disposition NPN/NPNP combination and PNP/PNPN combination, can be so that the protective capacities bi-directional symmetrical of device.Compare with known semiconductor overvoltage protective device, according to overvoltage protective device of the present utility model by all adopting in the overvoltage protection circuit transistor and thyristor combination to consist of the overvoltage protective unit positive and negative, at aspects such as device architecture, operation principle, device performance and overvoltage protective capabilities, can realize comprising the bi-directional symmetrical of forward and negative sense, and the integral protection ability of device and protection speed are significantly improved.
Preferably, the utility model protective device comprises two identical protective units, and each protective unit is made of a NPN transistor/NPNP thyristor combination and a PNP transistor/PNPN thyristor combination, forms thus two-path bidirectional overvoltage protective device.
According to the utility model, a kind of overvoltage protector of semiconductor spare is provided, this device comprises,
NPN transistor reaches the NPNP thyristor by its control, and
The PNP transistor reaches the PNPN thyristor by its control,
Wherein,
The base stage of this NPN transistor is as the negative sense overvoltage reference potential port of this device,
The transistorized base stage of this PNP is as the forward overvoltage reference potential port of this device,
The negative electrode of the anode of this NPNP thyristor and PNPN thyristor links to each other as the grounding ports of device, and the anode of the negative electrode of this NPNP thyristor and this PNPN thyristor links to each other as the access interface of device.
Preferably, the emitter and collector of described NPN transistor respectively with the control utmost point and the anodic bonding of described NPNP thyristor, the transistorized emitter and collector of described PNP is connected with negative electrode with the control utmost point of described PNPN thyristor respectively.
According on the other hand of the present utility model, a kind of overvoltage protector of semiconductor spare is provided, this device comprises the first protected location and the second protected location, each protected location comprises:
NPN transistor reaches the NPNP thyristor by its control, and
The PNP transistor reaches the PNPN thyristor by its control,
The negative electrode of the NPNP thyristor in described the first protected location links to each other as the first access interface of device with the anode of PNPN thyristor,
The negative electrode of the NPNP thyristor in described the second protected location links to each other as the second access interface of device with the anode of PNPN thyristor,
The base stage of the NPN transistor of described the first protected location and the second protected location is electrically connected the negative sense overvoltage reference potential port as this device,
The transistorized base stage of the PNP of described the first protected location and the second protected location is electrically connected the forward overvoltage reference potential port as this device,
The anode of the NPNP thyristor of the anode of the NPNP thyristor of described the first protected location and the negative electrode of PNPN thyristor and described the second protected location and the negative electrode of PNPN thyristor are electrically connected the grounding ports as device mutually.
Preferably, in each of described the first protected location and the second protected location,
The emitter and collector of described NPN transistor respectively with the control utmost point and the anodic bonding of described NPNP thyristor, the transistorized emitter and collector of described PNP is connected with negative electrode with the control utmost point of described PNPN thyristor respectively.
Preferably, the NPNP thyristor that described NPN transistor reaches by its control is formed by the NPN transistor district that makes at the N type semiconductor substrate and NPNP thyristor district, and the PNPN thyristor that described PNP transistor reaches by its control is formed by the PNP transistor area of making at the P type semiconductor substrate and PNPN thyristor district.
Preferably, in the transistor area of described N-type chip, be provided with successively from the top down n type diffused layer and p type diffused layer, be provided with from bottom to top N
+Diffusion layer, p type diffused layer and N
+The N-type doped layer of the N type semiconductor substrate between the type diffusion layer self consists of NPN transistor with this from top to bottom in N-type chip transistor area; In the described P cake core transistor area, be provided with successively from the top down p type diffused layer and n type diffused layer, be provided with from bottom to top P
+Diffusion layer, n type diffused layer and P
+The P type doped layer of the P type semiconductor substrate between the diffusion layer self consists of the PNP transistor with this from top to bottom in P cake core transistor area.
Preferably, in the thyristor district of described N-type chip, be provided with successively from the top down N
+Type diffusion layer and p type diffused layer are provided with P from bottom to top
+The type diffusion layer, p type diffused layer and P
+The N-type doped layer of the N type semiconductor substrate between the type diffusion layer self consists of NPNP type thyristor with this from top to bottom in N-type chip thyristor district; In the thyristor district of described P cake core, be provided with successively from the top down P
+Type diffusion layer and n type diffused layer are provided with N from bottom to top
+The type diffusion layer, n type diffused layer and N
+The P type doped layer of the P type semiconductor substrate between the type diffusion layer self consists of PNPN type thyristor with this from top to bottom in P cake core thyristor district.
Preferably, the N in described thyristor district
+Have a plurality of short-channels in the type diffusion layer, the equal and N in the top of each short-channel
+The metal level of type diffusion layer top electrically contacts N
+The p type diffused layer of type diffusion layer below is connected to N by described short-channel
+The metal level of type diffusion layer top; The P in described thyristor district
+Be provided with a plurality of short-channels in the type diffusion layer, the equal and P in the top of each short-channel
+The metal level of type diffusion layer top electrically contacts P
+The n type diffused layer of type diffusion layer below is connected to P by described short-channel
+The metal level of type diffusion layer top.
Preferably; two NPN transistor and is formed by the NPN transistor district that makes at the N type semiconductor substrate and two NPNP thyristor districts laying respectively at both sides, NPN transistor district by two NPNP thyristors of its control in the first and second protected locations, two PNP transistor and formed with two PNPN thyristor districts that lay respectively at PNP transistor area both sides by the PNP transistor area of making at the P type semiconductor substrate by two PNPN thyristors of its control in the first and second protected locations.
Preferably, in described NPN transistor district, be provided with successively from the top down two parallel n type diffused layers and p type diffused layer, be provided with from bottom to top N
+Diffusion layer, p type diffused layer and N
+The N-type doped layer of the N type semiconductor substrate between the type diffusion layer self consists of NPN transistor with this from top to bottom in N type semiconductor substrate transistor district; In the described P type semiconductor substrate transistor district, be provided with successively from the top down two parallel p type diffused layers and n type diffused layer, be provided with from bottom to top P
+Diffusion layer, n type diffused layer and P
+The P type doped layer of the P type semiconductor substrate between the diffusion layer self consists of the PNP transistor with this from top to bottom in P type semiconductor substrate transistor district.
Preferably, the metal level that the metal level of N type semiconductor substrate below is connected with the P type semiconductor substrate connects and forms the grounding ports of this device, the N of N type semiconductor substrate
+Metal level on the type diffusion layer respectively with the corresponding P of P type semiconductor substrate
+Metal level on the type diffusion layer is connected to form access interface.
Preferably, the metal level that the metal level of N type semiconductor substrate below be connected with the P type semiconductor substrate by lead frame the Ji Dao connection and draw grounding ports as this device, the N of N type semiconductor substrate
+Metal level on the type diffusion layer respectively with the corresponding P of P type semiconductor substrate
+Metal level on the type diffusion layer is connected to form the first and second access interface of this device by welding wire.
Principle of the present utility model and effect: when the negative sense overvoltage occurs, bear the earial drainage task by NPN transistor/NPNP thyristor combination; When the forward overvoltage occurs, bear the earial drainage task by PNP transistor/PNPN thyristor combination.Like this, namely realize the positive and negative equilibrium to discharge capacity of device, realized again the symmetry of two-way overvoltage protective capability.Simultaneously, because discharge capacity and the speed of thyristor significantly is better than diode, and then makes the integral protection ability of device not be subjected to the diode restriction and be significantly improved.This is just so that the protection method of bi-directional symmetrical overvoltage protective device of the present utility model and protective capacities than present mainstream applications, adopt diode, negative sense overvoltage to adopt protection method and the protective capacities thereof of thyristor that obvious superiority and capability improving are arranged such as the forward overvoltage take TisP61089B as representative.
The utility model is improved for the protective capacities that makes semiconductor overvoltage protective device, realizes bi-directional symmetrical, has taked following measures:
(1) obtains the N-type chip by making NPN transistor/NPNP thyristor combination at the N-type substrate respectively, make PNP transistor/PNPN thyristor combination at P type substrate and obtain the P cake core, and according to the functional requirement of device, between N-type chip and P cake core, implement required electrical connection, so that the diode that replaces prior art with the NPNP thyristor of NPN transistor control realizes that forward overvoltage protection becomes possibility, form thus and positive and negatively bear by thyristor to earial drainage, the semiconductor overvoltage protective unit of quick, forward and reverse equilibrium.
(2) adopt according to chip structure of the present utility model, by NPN transistor and NPNP thyristor are produced on the N-type substrate base, PNP transistor and PNPN thyristor are produced on the P type substrate base symmetry and the harmony of easily Design and implementation overvoltage protective device overvoltage protection effect.
(3) adopt according to chip structure of the present utility model, by the negative electrode of the PNPN thyristor on the anode of the NPNP thyristor on the N-type chip and the P cake core Ji Dao by the plastic packaging lead frame directly being linked to each other and drawing as earth terminal, the anode of the negative electrode of NPNP thyristor and PNPN thyristor is linked to each other by welding wire and draw as incoming end, realized the electrical connection that protective device is required, and so that the miniaturization of device becomes possibility convenient and simplely.
The utility model device is through the thunderbolt performance test, and protection voltage can reach 4500V, and can satisfy the rate request that rising edge/trailing edge is 8/20 microsecond waveform.
Description of drawings
Fig. 1 illustrates the schematic diagram of existing overvoltage protection circuit;
Fig. 2 illustrates existing overvoltage protective device forward and negative sense overvoltage earial drainage V-I curve;
Fig. 3 illustrates the schematic diagram according to the overvoltage protection circuit of the utility model embodiment 1;
Fig. 4 illustrates the schematic diagram according to the overvoltage protection circuit of the utility model embodiment 2;
Fig. 5 illustrates the connection structural map of the overvoltage protective device with overvoltage protection circuit shown in Figure 4;
Fig. 6 A illustrates the vertical view according to the N-type chip of the utility model embodiment 3;
Fig. 6 B illustrates the vertical view according to the P cake core of the utility model embodiment 3;
Fig. 7 A illustrates chip shown in Fig. 6 A along B
1-B
1The longitudinal sectional drawing of line;
Fig. 7 B illustrates chip shown in Fig. 6 B along B
2-B
2The longitudinal sectional drawing of line;
Fig. 8 is the earial drainage V-I curve according to the utility model overvoltage protection circuit;
Fig. 9 is the application circuit figure of overvoltage protection circuit shown in Figure 4;
Figure 10 is the connection structural map of the overvoltage protective device of the utility model embodiment 5.
Various description of symbols are as follows in the above accompanying drawing:
1/8: device pin; 9
N: the N substrate; 9
P: the P substrate; 10
N: the NPN transistor district;
10
P: the PNP transistor area; 11
N: NPNP thyristor district; 11
P: PNPN thyristor district;
12
N: the N diffusion layer; 12
P: the P diffusion layer; 13
N: (NPN transistor district) N diffusion layer;
13
P: (PNP transistor area) P diffusion layer; 14
N: N
+Lower diffusion layer;
14
P: P
+Lower diffusion layer; 15
N: N substrate doped layer; 15
P: P substrate doped layer;
16
N: (NPNP thyristor district) N
+Diffusion layer; 16
P: (PNPN thyristor district) P
+Diffusion layer;
17
N: NPNP thyristor district P diffusion layer; 17
P: PNPN thyristor district N diffusion layer;
18
N: NPNP thyristor district P
+Lower diffusion layer; 18
P: PNPN thyristor district N
+Lower diffusion layer;
19
N: N-type backing material NPNP thyristor district N doped layer; 19
P: P type backing material PNPN thyristor district P doped layer;
20
N: NPNP thyristor district short-channel; 20
P: PNPN thyristor district short-channel;
21
N: metal level in the NPNP thyristor district; 21
P: metal level in the PNPN thyristor district;
22
N: NPN transistor G
–Metal level; 22
P: PNP transistor G
+Metal level;
23
N: NPN transistor and NPNP thyristor connection metal; 23
P: PNP transistor and PNPN thyristor connection metal;
24
N: N-type backing material top oxide layer; 24
P: P type backing material top oxide layer;
25
N: N-type backing material metal layer on back; 25
P: P type backing material metal layer on back.
26
N: the N in N-type backing material front
+The type frame; 26
P: the P in P type backing material front
+The type frame.
Embodiment
The utility model will be further described below with reference to accompanying drawings and in conjunction with the preferred embodiments.
Fig. 3 illustrates the schematic diagram according to the overvoltage protection circuit 300 of the utility model embodiment 1.Overvoltage protection circuit 300 includes NPN transistor 311 and NPNP thyristor 312 and PNP transistor 321 and PNPN thyristor 322.The emitter and collector of NPN transistor 311 respectively with the control utmost point and the anodic bonding of NPNP transistor 312, the emitter and collector of PNP transistor 321 is connected with negative electrode with the control utmost point of PNPN transistor 322 respectively.The base stage of NPN transistor 311 is as the negative sense overvoltage reference potential port G of protection circuit
–, the base stage of PNP transistor 321 is as the forward overvoltage reference potential port G of protection circuit
+The negative electrode that the anode of NPNP thyristor 312 is connected with the PNPN thyristor connects the grounding ports A(Ground as protection circuit); The anodic bonding of the negative electrode of NPNP thyristor 312 and PNPN thyristor 322 is as the access interface K of protection circuit.
When environment generation negative sense overvoltage that this overvoltage protection circuit 300 accesses, realize earial drainage by NPN transistor/NPNP thyristor combination; When the forward overvoltage occurs, realize earial drainage by PNP transistor/PNPN thyristor combination.Overvoltage protection circuit according to this embodiment had both had the positive and negative to discharge capacity of equilibrium, had again symmetrical two-way overvoltage protective capability.Simultaneously, because discharge capacity and the speed of thyristor significantly are better than diode, the integral protection ability of this protection circuit is significantly improved because of the restriction that is not subjected to diode behavior.
Fig. 4 illustrates the schematic diagram according to the overvoltage protection circuit 400 of the utility model embodiment 2.Overvoltage protection circuit 400 comprises the first protective unit and the second protective unit, and each protective unit has structure as shown in Figure 3.The first protective unit comprises NPN transistor 411 and NPNP thyristor 412 and PNP transistor 421 and PNPN thyristor 422.The emitter and collector of NPN transistor 411 respectively with the control utmost point and the anodic bonding of NPNP transistor 412, the emitter and collector of PNP transistor 421 is connected with negative electrode with the control utmost point of PNPN transistor 422 respectively.The second protective unit comprises NPN transistor 431 and NPNP thyristor 432 and PNP transistor 441 and PNPN thyristor 442.The emitter and collector of NPN transistor 431 respectively with the control utmost point and the anodic bonding of NPNP transistor 432, the emitter and collector of PNP transistor 441 is connected with negative electrode with the control utmost point of PNPN transistor 442 respectively.The base stage of NPN transistor 411 is connected with the base stage of NPN transistor 431 and as the negative sense overvoltage reference potential port G – of protection circuit 400, and the base stage of PNP transistor 421 is connected with the base stage of PNP transistor 441 and is used as the forward overvoltage reference potential port G of protection circuit 400
+The negative electrode of the anode of the negative electrode of the anode of NPNP thyristor 312 and PNPN thyristor 322 and NPNP thyristor 332 and PNPN thyristor 342 links together as the grounding ports A(Ground of protection circuit 400); The anodic bonding of the negative electrode of NPNP thyristor 312 and PNPN thyristor 322 is as the first access interface K1 of protection circuit; The anodic bonding of the negative electrode of NPNP thyristor 332 and PNPN thyristor 342 is as the second access interface K2 of protection circuit.
Preferably, the first protective unit and the second protective unit are two identical protective units.
Fig. 5 is the syndeton with overvoltage protective device of overvoltage protection circuit shown in Figure 4, and as shown in Figure 5, this overvoltage protective device is selected for example wsop-8 type package casing encapsulation.The base stage that comprises 400, two NPN transistor 411,431 of protection circuit shown in Figure 4 in the packaging body connects and draws G as device at pin two
–Port; The transistorized base stage of two PNP connects and draws G as device at pin 3
+Port.The A port of the first protective unit and the second protective unit for example can directly link to each other and at pin 6,7 draw two A ports as device, the corresponding anode of the negative electrode of two NPNP thyristors and two PNPN thyristors for example links to each other by metal welding wire respectively and draws the first and second access interface K1 as device, K2 at pin one and 4.Pin 5,8 vacant.
Specifically describe chip structure according to the overvoltage protective device of the utility model embodiment 2 below with reference to Fig. 6 and Fig. 7.
Below with reference to Fig. 6 A and Fig. 7 A chip structure according to the N-type chip 600 of the utility model embodiment 3 is described.The N-type chip comprises two groups of NPN transistor in the overvoltage protective device 400 and the combination of NPNP thyristor.Fig. 6 A is illustrated in N type semiconductor substrate 9
NThe semiconductor chip vertical view of the N-type chip 600 of upper making, Fig. 7 A are that N-type chip 600 shown in Fig. 6 A is along B
1-B
1The longitudinal sectional drawing of line.As shown in the figure, the transistor area 10 that comprises two NPN transistor in the N-type chip 600
NBe positioned at the middle part of chip and respectively comprise two NPNP thyristor districts 11 of a NPNP thyristor
NBe respectively formed at the both sides of transistor area.Preferably, two NPN transistor/NPNP thyristor combinations have symmetrical structure.
With reference to figure 7A, comprise the NPN transistor district 10 of two NPN transistor
NBe provided with successively from the top down parallel the first and second n type diffused layers 12 that arrange
NWith p type diffused layer 13
N, the first and second n type diffused layers 12
NBetween p type diffused layer 13
NOn be formed with metal level 22
NSubstrate 9
NThe transistor area 10 of reverse side
NBe provided with from bottom to top N
+Diffusion layer 14
N, described transistor area 10
NP type diffused layer 13
NWith N
+Type diffusion layer 14
NBetween substrate 9
NThe N-type doped layer 15 of self
N, with this 10
NTransistor area forms two NPN transistor from top to bottom.Each NPNP thyristor district 11
NBe respectively equipped with from the top down N
+Type diffusion layer 16
NWith p type diffused layer 17
N, substrate 9
NThe thyristor district 11 of reverse side
NBe provided with from bottom to top P
+Type diffusion layer 18
N, described thyristor district 11
NP type diffused layer 17
NAnd P
+Type diffusion layer 18
NBetween substrate 9
NThe N-type doped layer 19 of self
N, with this in thyristor district 11
NConsist of NPNP type thyristor from top to bottom.Preferably, described thyristor district 11
NN
+Type diffusion layer 16
NIn some short circuit circular channels 20 are set at a certain distance
N, each short circuit circular channel 20
NThe upper end all and N
+Type diffusion layer 16
NThe metal level 21 of top
NDirectly electrically contact.N
+Type diffusion layer 16
NThe p type diffused layer 17 of below
NBy above-mentioned short-channel 20
NUpwards be connected to metal level 21
N, the p type diffused layer in described thyristor district and the n type diffused layer of described transistor area are by metal level 23
NBe connected.Substrate 9
NThe back side is provided with metal level 25
N, and with the P that forms from bottom to top
+Type diffusion layer 18
NAnd N
+Type diffusion layer 14
NLink to each other.Described thyristor district 11
NThe P that reverse side diffuses to form from bottom to top
+Type diffusion layer 18
NThe peripheral oxide layer 24 that upwards always extends to the substrate front
N, and 9
NThe front form a P
+The frame 26 of type
N
Below with reference to Fig. 6 B and Fig. 7 B chip structure according to the P cake core 700 of the utility model embodiment 3 is described.P cake core 700 comprises the combination of two groups of PNP transistor/PNPN thyristors in the overvoltage protective device 400.Fig. 6 B is illustrated in P type semiconductor substrate 9
PThe semiconductor chip vertical view of the P cake core 700 of upper making, Fig. 7 B are that P cake core 700 shown in Fig. 6 B is along B
2-B
2The longitudinal sectional drawing of line.As shown in the figure, comprise two transistorized transistor area 10 of PNP in the P cake core 700
PBe positioned at the middle part of chip and two PNPN thyristor districts 11 that respectively comprise a NPNP thyristor
PBe respectively formed at the both sides of transistor area.Preferably, two PNP transistor/PNPN thyristor combinations have symmetrical structure.
With reference to figure 7B, comprise two transistorized PNP transistor area 10 of PNP
PBe provided with successively from the top down parallel the first and second p type diffused layers 12 that arrange
PWith n type diffused layer 13
P, the first and second p type diffused layers 12
PBetween n type diffused layer 13
PUpper formation metal level 22
PSubstrate 9
PThe transistor area 10 of reverse side
PBe provided with from bottom to top P
+Type diffusion layer 14
P, described transistor area 10
PN type diffused layer 13
PAnd P
+Type diffusion layer 14
PBetween be substrate 9
PThe P type doped layer 15 of self
P, consist of two PNP transistors with this from top to bottom in transistor area.Each PNPN thyristor district 11
PBe provided with successively from the top down P
+Type diffusion layer 16
PWith n type diffused layer 17
P, substrate 9
PThe thyristor district 11 of reverse side
PBe provided with from bottom to top N
+Type diffusion layer 18
P, described thyristor district 11
PN type diffused layer 17
PAnd N
+Type diffusion layer 18
PBetween be substrate 9
PThe P type doped layer 19 of self
P, with this in thyristor district 11
PConsist of PNPN type thyristor from top to bottom.Described thyristor district 11
PP
+Type diffusion layer 16
PIn some short circuit circular channels 20 are set at a certain distance
P, each short circuit circular channel 20
PThe upper end all and P
+Type diffusion layer 16
PThe metal level 21 of top
PDirectly electrically contact P
+Type diffusion layer 16
PThe n type diffused layer 17 of below
PBy above-mentioned short circuit circular channel 20
PUpwards be connected to metal level 21
P, the n type diffused layer in described thyristor district and the p type diffused layer of described transistor area are by metal level 23
PBe connected.Substrate 9
PThe back side is provided with metal level 25
PAnd with the N that diffuses to form from bottom to top
+Type diffusion layer 18
PAnd P
+Type diffusion layer 14
PLink to each other.Described thyristor district 11
PThe N that reverse side diffuses to form from bottom to top
+Type diffusion layer 18
PThe peripheral oxide layer 24 that upwards always extends to the substrate front
P, and 9
PThe front form a N
+The frame 26 of type
P
When adopting the encapsulation of aforesaid N-type chip and P cake core to form as shown in Figure 5 the overvoltage protective device, substrate 9
NWith 9
PMetal layer on back 25
NWith 25
PPreferably by the direct grounding ports A that links to each other and lead to the overvoltage protective device of the Ji Dao of plastic packaging lead frame, upper metal level 21
NWith 21
PPreferably connect by welding wire and lead to access interface K1, K2, negative sense overvoltage reference potential port G
–From substrate 9
NMetal level 22
NDraw forward overvoltage reference potential port G
+From substrate 9
PMetal level 22
PDraw.Thus, the two-path bidirectional overvoltage protective device that forms, includes two protective units by a slice N-type chip and a slice P cake core forms at this point.Each protective unit is made of a NPN transistor of making at the N type semiconductor material/NPNP thyristor combination and the PNP transistor of making at a P type semiconductor material/PNPN thyristor combination.Fig. 8 illustrates the earial drainage V-I curve of the overvoltage protection circuit that forms thus, has good bi-directional symmetrical.
Fig. 9 is the application circuit according to the overvoltage protective device G110S of the utility model embodiment 2, this embodiment device has two protective units as shown in the figure, respectively Tip and the Ring port of the programme-controlled subscriber line interface pronounciation processing chip (SLIC chip) of communicating by letter is implemented the overvoltage protection.
When Tip line or Ring line generation forward overvoltage impact, PNP transistor/PNPN thyristor combination P
01Or P
02Rapidly conducting, the forward overvoltage energy of releasing over the ground, the protection pronounciation processing chip is not impacted by overvoltage; When Tip line or Ring line generation negative sense overvoltage impact, NPN transistor/NPNP thyristor combination N
01Or N
02Rapidly conducting, the negative sense overvoltage energy of releasing over the ground, the protection pronounciation processing chip is not impacted by overvoltage and exempts from damage, and overvoltage is impacted and is comprised thunderbolt, mains fluctuations etc.
In actual applications, according to demand, port G can be set flexibly
–And G
+Reference potential, when surge voltage attack impel transistor turns after, just can inject trigger current to thyristor so that the thyristor conducting, the surge voltage energy is released over the ground.
Port G
–Current potential can arrange port G as required between-110V～0V
+Current potential can 0V～+ arrange as required between the 110V, it is convenient, flexibly to use, highly versatile.
It is positive and negative to the asymmetric shortcoming of overvoltage protective capability that the utility model has overcome existing semiconductor overvoltage protective device, realizes bi-directional symmetrical overvoltage protection.According to the utility model, use the diode that comprises the use of the transistorized PNPN thyristor replacement of PNP prior art that the P type semiconductor material is made, discharge capacity and the earial drainage speed of device have been significantly improved on the whole, protection voltage can reach ± 4500v, it is the 8/20us rate request that protection speed can satisfy rising edge/trailing edge, and barrier propterty is improved significantly.
Although foregoing has been described in detail the overvoltage protective device that comprises two identical protective units with reference to Fig. 4 to Fig. 8, one of ordinary skill in the art will readily recognize that said chip structure and explanation are equally applicable to comprise the overvoltage protective device of a protective unit or 4 identical or different protective units.
According to different application scenarios, overvoltage protection circuit as shown in Figure 4 can have different encapsulation connected modes, as shown in figure 10.
Should be appreciated that the above detailed description of the technical solution of the utility model being carried out by preferred embodiment is illustrative and not restrictive.Those of ordinary skill in the art can make amendment to the technical scheme that each embodiment puts down in writing on the basis of reading the utility model specification, perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of each embodiment technical scheme of the utility model.
Claims (10)
1. bi-directional symmetrical overvoltage protective device, this device comprises the first protected location, the second protected location, lead frame and package casing,
It is characterized in that each protected location comprises:
NPN transistor reaches the NPNP thyristor by its control, and
The PNP transistor reaches the PNPN thyristor by its control,
The negative electrode of the NPNP thyristor in described the first protected location links to each other as the first access interface of device with the anode of PNPN thyristor,
The negative electrode of the NPNP thyristor in described the second protected location links to each other as the second access interface of device with the anode of PNPN thyristor,
The base stage of the NPN transistor of described the first protected location and the second protected location is electrically connected the negative sense overvoltage reference potential port as this device,
The transistorized base stage of the PNP of described the first protected location and the second protected location is electrically connected the forward overvoltage reference potential port as this device,
The anode of the NPNP thyristor of the anode of the NPNP thyristor of described the first protected location and the negative electrode of PNPN thyristor and described the second protected location and the negative electrode of PNPN thyristor are electrically connected the grounding ports as device mutually.
2. bi-directional symmetrical overvoltage protective device as claimed in claim 1 is characterized in that, in each of described the first protected location and the second protected location,
The emitter and collector of described NPN transistor respectively with the transistorized control utmost point of described NPNP and anodic bonding, the transistorized emitter and collector of described PNP is connected with negative electrode with the transistorized control utmost point of described PNPN respectively.
3. bi-directional symmetrical overvoltage protective device as claimed in claim 1 is characterized in that, NPN transistor described in the first and second protected locations and by the NPNP thyristor of its control by at N type semiconductor substrate (9
N) the upper NPN transistor district (10 that makes
N) and NPNP thyristor district (11
N) form, PNP transistor described in the first and second protected locations and by the PNPN thyristor of its control by at P type semiconductor substrate (9
P) upper PNP transistor area (10 of making
P) and PNPN thyristor district (11
P) form.
4. bi-directional symmetrical overvoltage protective device as claimed in claim 3 is characterized in that, two groups of NPN transistor and by the NPNP thyristor of its control by at N type semiconductor substrate (9
N) the upper NPN transistor district (10 that makes
N) and lay respectively at two NPNP thyristor districts (11 of both sides, NPN transistor district
N) form, two groups of PNP transistor and by the PNPN thyristor of its control by at P type semiconductor substrate (9
P) upper PNP transistor area (10 of making
P) and lay respectively at two PNPN thyristor districts (11 of PNP transistor area both sides
P) form.
5. bi-directional symmetrical overvoltage protective device as claimed in claim 3 is characterized in that, in described NPN transistor district (10
N) in, be provided with successively from the top down parallel the first and second n type diffused layers (12 that arrange
N) and p type diffused layer (13
N), be provided with from bottom to top N
+Diffusion layer (14
N), p type diffused layer (13
N) and N
+Type diffusion layer (14
N) between N type semiconductor substrate (9
N) self N-type doped layer (15
N), consist of 2 NPN transistor with this from top to bottom in N type semiconductor substrate transistor district; Described P type semiconductor substrate (9
P) transistor area (10
P) in, be provided with successively from the top down parallel the first and second p type diffused layers (12 that arrange
P) and n type diffused layer (13
P), be provided with from bottom to top P
+Diffusion layer (14
P), n type diffused layer (13
P) and P
+Diffusion layer (14
P) between P type semiconductor substrate (9
P) self P type doped layer (15
P), consist of 2 PNP transistors with this from top to bottom in P type semiconductor substrate transistor district.
6. bi-directional symmetrical overvoltage protective device as claimed in claim 5 is characterized in that, described thyristor district (11
N) N
+Type diffusion layer (16
N) in be provided with a plurality of short circuits hole (20
N), each short circuit hole (20
N) the top all and N
+Type diffusion layer (16
N) top metal level (21
N) contact, N
+Type diffusion layer (16
N) below p type diffused layer (17
N) by described short circuit hole (20
N) be connected to N
+Type diffusion layer (16
N) top metal level (21
N); Described thyristor district (11
P) P
+Type diffusion layer (16
P) in be provided with a plurality of short circuits hole (20
P), each short circuit hole (20
P) the top all and P
+Type diffusion layer (16
P) top metal level (21
P) contact, P
+Type diffusion layer (16
N) below n type diffused layer (17
P) by described short circuit hole (20
P) be connected to P
+Type diffusion layer (16
P) top metal level (21
P).
7. bi-directional symmetrical overvoltage protective device as claimed in claim 5 is characterized in that, the first and second n type diffused layers (12
N) between p type diffused layer (13
N) on be formed with metal level (22
N), the first and second p type diffused layers (12
P) between n type diffused layer (13
P) on be formed with metal level (22
p).
8. bi-directional symmetrical overvoltage protective device as claimed in claim 7 is characterized in that N type semiconductor substrate (9
N) below metal level (25
N) and P type semiconductor substrate (9
P) below metal level (25
P) connect and form the grounding ports of this device, N type semiconductor substrate (9
N) N
+Type diffusion layer (16
N) on metal level (21
N) respectively with P type semiconductor substrate (9
P) corresponding P
+Type diffusion layer (16
P) on metal level (21
P) be connected to form access interface.
9. bi-directional symmetrical overvoltage protective device as claimed in claim 7 is characterized in that N type semiconductor substrate (9
N) below metal level (25
N) and P type semiconductor substrate (9
P) below metal level (25
P) Ji Dao by lead frame connects and draw grounding ports as this device, N type semiconductor substrate (9
N) N
+Type diffusion layer (16
N) on metal level (21
N) respectively with P type semiconductor substrate (9
P) corresponding P
+Type diffusion layer (16
P) on metal level (21
P) be connected to form the first and second access interface of this device by welding wire.
10. bi-directional symmetrical overvoltage protective device as claimed in claim 1 is characterized in that, described package casing is 8 terminal package casings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320203878 CN203260575U (en) | 2013-04-19 | 2013-04-19 | Bidirectional symmetrical overvoltage protection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320203878 CN203260575U (en) | 2013-04-19 | 2013-04-19 | Bidirectional symmetrical overvoltage protection device |
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| Publication Number | Publication Date |
|---|---|
| CN203260575U true CN203260575U (en) | 2013-10-30 |
Family
ID=49473117
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|---|---|---|---|
| CN 201320203878 Expired - Lifetime CN203260575U (en) | 2013-04-19 | 2013-04-19 | Bidirectional symmetrical overvoltage protection device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111627901A (en) * | 2020-06-04 | 2020-09-04 | 电子科技大学 | Programmable bidirectional anti-surge protection device triggered by JFET (junction field-effect transistor) |
-
2013
- 2013-04-19 CN CN 201320203878 patent/CN203260575U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111627901A (en) * | 2020-06-04 | 2020-09-04 | 电子科技大学 | Programmable bidirectional anti-surge protection device triggered by JFET (junction field-effect transistor) |
| CN111627901B (en) * | 2020-06-04 | 2022-08-05 | 电子科技大学 | Programmable bidirectional anti-surge protection device triggered by JFET (junction field-effect transistor) |
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| GR01 | Patent grant | ||
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| CX01 | Expiry of patent term |
Granted publication date: 20131030 |