CN203249633U

CN203249633U - Frequency-voltage switching circuit

Info

Publication number: CN203249633U
Application number: CN 201320295456
Authority: CN
Inventors: 吴建辉; 黄丹; 陈超; 娄宁; 李红; 田茜
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2013-05-24
Filing date: 2013-05-24
Publication date: 2013-10-23
Anticipated expiration: 2023-05-24

Abstract

The utility model provides a frequency-voltage switching circuit mainly comprising a logic control circuit and a main circuit. Fixed current is used for charging a capacitor, the discharge is delayed, and the peak voltage of the charging capacitor is stored for a time, so capacitance is collected and voltage values is collected and stored. Meanwhile, in order to prevent a sampling switch from affecting the charging capacitor, an original follower is used as a high-speed buffer to isolate the charging capacitor and a sampling circuit, and a feedback circuit based on an operational amplifier is used for eliminating the sampling level displacement introduced by the original follower and allowing the output voltage to revert to the peak voltage of the charging capacitor. Due to the introduction of the high-speed buffer for isolating the charging capacitor and a collecting switch, compared with a traditional charging type F-V convertor, the frequency-voltage switching circuit has higher precision, and is capable of stably working in a wide range of input frequency due to the delayed charging and the high bandwidth of the buffer.

Description

A kind of frequency-voltage conversion circuit

Technical field

The present invention relates to a kind of frequency-voltage conversion circuit, particularly a kind of frequency-voltage conversion circuit of high-precision wide input range.

Background technology

FV convertor or F-V converter are a kind ofly to have the change of extensive use to send device in control, in detecting.FV convertor is the nucleus module of FLL (Frequency-Locked Loop), and FLL is generally used in the carrier tracking loop, directly follows the tracks of carrier frequency, has preferably dynamic property.The principle of FLL circuit mainly based on voltage to frequency conversion and voltage ratio, is finished by the frequency-voltage conversion circuit in the FLL (FVC) and error amplifier.In order to guarantee the frequency accuracy of FLL output, the precision of frequency-voltage conversion circuit is key wherein.

About the existing pertinent literature of the structure of frequency-voltage conversion circuit some different methods for designing have been proposed.Relatively a kind of method commonly used is to use the frequency of low-pass filter to voltage conversion circuit, the response time of FVC is mainly determined by the time constant of low-pass filter in the method, if time constant is large, then the response time is slow, if but time constant is little, then Voltage-output can produce sizable ripple, and therefore instantaneous frequency measures become impossible.Wanlop has proposed an analog sine formula FV convertor, this main circuit will be by differentiator, integrator, linear transconductance divider and square root the electric circuit constitute, although the method can be measured instantaneous frequency change, but incoming frequency is lower, and only for 50Hz arrives 5KHz, and the restriction input signal must be sine wave.Djemouai has proposed dynamical CMOS frequency to electric pressure converter.This architectural configurations is simple, does not need to use low-pass filter and larger electric capacity and resistance, therefore only needs very little circuit area, and output voltage does not exchange ripple.The method adopts the charge redistribution principle, and to capacitor charging and gather voltage on the electric capacity, the voltage that finally gathers on the electric capacity is output voltage.If but the method needs to reduce error, must increase the periodicity of conversion, thereby reduce slewing rate.And because the too much charge injection effect introduced of switch, reduced the output accuracy of this structure.

Summary of the invention

Goal of the invention: the problem and shortage for above-mentioned prior art exists the purpose of this invention is to provide the frequency-voltage conversion circuit that a kind of conversion accuracy is high, incoming frequency is wide.

Technical scheme: for achieving the above object, the invention provides a kind of frequency-voltage conversion circuit, comprise logic control circuit and main body circuit;

Wherein, described logic control circuit is the square-wave signal VCKPP of input fixed frequency, obtain signal VCKP through the two-stage phase inverter, signal VCKP obtains signal VCKN through the one-level phase inverter, signal VCKN inputs as the first rejection gate one end through nine grades of inverter delay unit outputs again, the first rejection gate other end is input as VCKPP, the rejection gate output signal is VCKN1, VCKN1 and VCKPP are as the input of second level rejection gate, output signal is VCKSP1, and VCKSP1 obtains signal VCKSP through the one-level phase inverter again;

Described main body circuit comprises: current biasing circuit, steady current source circuit, transmission gate switch, charging capacitor, discharge switch, source follower, sample circuit, level displacement circuit and RC filter network, wherein, described current biasing circuit provides biasing for described steady current source circuit, in front half input cycle, described transmission gate switch makes described steady current source circuit to described charging capacitor charging according to the control signal that described logic control circuit provides; In rear half period, described transmission gate switch switches to ground according to the control signal that described logic control circuit provides with steady current, by delayed discharge, crest voltage on the described charging capacitor keeps, the control signal conducting that sampling switch in the described sample circuit of while provides according to described logic control circuit, so that the crest voltage on the described charging capacitor flows into described sample circuit behind described source follower, described sample circuit collection is also stored this magnitude of voltage, after the sample circuit sampling finishes, described sampling switch disconnects according to the control signal that described logic control circuit provides, the control signal conducting that discharge switch provides according to described logic control circuit, described charging capacitor discharge, the voltage of simultaneously described sample circuit output are successively through exporting behind described level displacement circuit and the described RC filter network.

Described steady current source circuit comprises the 5th PMOS pipe (M5), the 6th PMOS pipe (M6), the 7th PMOS pipe (M7), the 8th PMOS pipe (M8) and the 20 NMOS pipe (M20), the common-source amplifier of current source load the 20 NMOS pipe (M20) that wherein said the 5th PMOS pipe (M5) and the 6th PMOS pipe (M6) consist of, described common-source amplifier and the 8th PMOS pipe (M8) consist of feedback loop, and described feedback loop is clamped at the drain voltage that the 7th PMOS manages (M7) on the fixed value.The fluctuation of the drain voltage of the 8th PMOS pipe (M8) is under the effect of feedback loop, automatically adjust the variation of the 8th PMOS pipe (M8) grid voltage through common-source amplifier output, to offset the curent change that is brought by the fluctuation of the 8th PMOS pipe (M8) drain voltage.Only cause the very little variation of the 7th PMOS pipe (M7) drain terminal voltage because the output end voltage of steady current source circuit changes, so the steady current source circuit externally shows the current value of approximately constant, equivalent output impedance obtains to significantly improve.

Principle of work: the present invention uses fixed current that charging capacitor is charged in front half input clock cycle, gathers and store the crest voltage of charging capacitor as output voltage.When charge cycle finishes, by delayed discharge, the crest voltage on the charging capacitor preserved a period of time so that late-class circuit collection and store this magnitude of voltage, after gathering the sequential end, the charging capacitor discharge, discharge enters the next cycle after finishing, continue charging, gather the process of discharge; For fear of the impact on crest voltage of the charge injection effect of sampling switch, used voltage follower as the impact damper between the collection electric capacity of charging capacitor and sample circuit, the Acquisition Circuit collection is also stored the crest voltage that this impact damper is exported, process is based on the degenerative level shift circuit of amplifier, and the output end voltage value returns to the crest voltage on the charging capacitor.

Beneficial effect: compared with prior art, the present invention is owing to having introduced high-speed buffer isolation charging capacitor and having gathered switch, so that frequency inverted becomes the precision of voltage higher, simultaneously because the high bandwidth of delayed discharge and impact damper, the present invention can be under wide incoming frequency scope reliably working.

Description of drawings

Fig. 1 is main body circuit theory diagrams of the present invention;

Fig. 2 is logic control circuit schematic diagram of the present invention;

Fig. 3 is each output control terminal simulation waveform figure of logic control circuit of the present invention;

Fig. 4 is the voltage simulation waveform figure that charging capacitor voltage of the present invention and main body main circuit are wanted control end;

Fig. 5 is the simulation waveform figure of charging capacitor voltage of the present invention and output voltage;

Fig. 6 is the variation diagram of circuit incoming frequency of the present invention output voltage when changing in the 10MHz-120MHz scope.

Embodiment

Below in conjunction with the drawings and specific embodiments, further illustrate the present invention.

The main circuit of frequency-voltage conversion circuit as shown in Figure 1, comprise current biasing circuit 1, steady current source circuit 2, transmission gate switch 3, charging capacitor 4, sample circuit 5, source follower 6, level displacement circuit 7, RC filter network 8 and discharge quick closing valve 9, current biasing circuit 1 provides biasing for described steady current source circuit 2, in front half input cycle, described transmission gate switch 3 makes described steady current source circuit 2 to described charging capacitor 4 chargings according to the control signal that described logic control circuit provides; In rear half period, described transmission gate switch 3 switches to ground according to the control signal that described logic control circuit provides with steady current, by delayed discharge, crest voltage on the described charging capacitor 4 keeps, the control signal conducting that sampling switch in the described sample circuit 5 of while provides according to described logic control circuit, so that the crest voltage on the described charging capacitor flows into described sample circuit 5 behind described source follower 6, described sample circuit 5 gathers and stores this magnitude of voltage, after sample circuit 5 samplings finish, described sampling switch disconnects according to the control signal that described logic control circuit provides, the control signal conducting that discharge switch 9 provides according to described logic control circuit, described charging capacitor 4 discharges, the voltage of simultaneously described sample circuit 5 outputs is successively through output behind described level displacement circuit 7 and the described RC filter network 8.

The end that main circuit is specially reference current source meets respectively described NMOS pipe M1, the grid of described the 2nd NMOS pipe M2 and described the 20 NMOS pipe M20, the source electrode of the drain electrode of the drain electrode of the one NMOS pipe M1 and the 2nd NMOS pipe M2 and described the 3rd NMOS pipe M3, link to each other after the drain electrode of the 3rd NMOS pipe M3 and the 4th PMOS pipe M4 and the source shorted, the 4th PMOS manages M4, the 7th PMOS pipe M7 connects with the grid of the 6th PMOS pipe M6, the grid of the 5th PMOS pipe M5 connects respectively the drain electrode of the 7th PMOS pipe M7 and the source electrode of the 8th PMOS pipe M8, the drain electrode of the 5th PMOS pipe M5 connects respectively the drain electrode of grid and the 20 NMOS pipe M20 of the 8th PMOS pipe M8, the drain electrode of the 8th PMOS pipe M8 meets respectively the 9th NMOS pipe M9, the drain electrode of the 12 NMOS pipe M12 and the tenth PMOS pipe M10, the source electrode of the 13 PMOS pipe M13, the drain electrode of the 11 NMOS pipe M11 connects respectively the source electrode of the 9th NMOS pipe M9, the drain electrode of the tenth PMOS pipe M10, the grid of the end of charging capacitor C0 and the 14 NMOS pipe M14, the source electrode of 11 NMOS pipe M11, the source electrode of the 12 NMOS pipe M12, the drain electrode of the 13 PMOS pipe M13, the drain electrode of the 14 NMOS pipe M14 and the other end ground connection of charging capacitor, the source electrode of the 14 NMOS pipe M14 connects respectively the drain electrode of the 15 PMOS pipe M15 and the 17 PMOS pipe M17 and the source electrode of the 16 NMOS pipe M16, the source electrode of M17 is managed respectively in the drain electrode of the 16 NMOS pipe M16 with the 17 PMOS, sampling capacitance C1 one end is connected electrode input end and is connected with operational amplifier, the output terminal of operational amplifier is connected with the end that the grid of the 19 PMOS pipe M19 is connected with resistance R respectively, the source electrode of the 19 PMOS pipe M19 is connected negative input with the drain electrode of the 18 PMOS pipe M18 respectively and is connected with operational amplifier, the other end of resistance R 0 is connected with an end of the second capacitor C 2, the other end ground connection of the second capacitor C 2.

Wherein, current biasing circuit 1 is comprised of reference current source, a NMOS pipe M1, the 2nd NMOS pipe M2, the 3rd NMOS pipe M3 and the 4th PMOS pipe M4, the 3rd NMOS pipe M3 is so that the 2nd NMOS pipe M2 is similar to the voltage between the source electrode to the drain electrode of the 4th PMOS pipe M4, thereby so that the current mirror replica current is more accurate.Steady current source circuit 2 adopts the gain bootstrap technology, to increase the output impedance of this current source circuit, this steady current source circuit 2 comprises the 5th PMOS pipe M5, the 6th PMOS pipe M6, the 7th PMOS pipe M7, the 8th PMOS pipe M8 and the 20 NMOS pipe M20, the common-source amplifier of current source load the 20 NMOS pipe M20 that wherein said the 5th PMOS pipe M5 and the 6th PMOS pipe M6 consist of, described common-source amplifier and the 8th PMOS pipe M8 consist of feedback loop, and described feedback loop is clamped at the drain voltage of the 7th PMOS pipe M7 on the fixed value.The fluctuation of the drain voltage of the 8th PMOS pipe M8 is adjusted the variation of the grid voltage of the 8th PMOS pipe M8 automatically through common-source amplifier output under the effect of feedback loop, to offset the curent change that is brought by the fluctuation of the 8th PMOS pipe M8 drain voltage.Because the output end voltage of this current source circuit changes the very little variation of drain voltage that only causes the 7th PMOS pipe M7, this current source circuit externally shows the current value of approximately constant, and equivalent output impedance obtains to significantly improve.

As shown in Figure 2, logic control circuit is the square-wave signal VCKPP of input fixed frequency, obtain signal VCKP through the two-stage phase inverter, signal VCKP obtains signal VCKN through the one-level phase inverter, signal VCKN inputs as the first rejection gate one end through nine grades of inverter delay unit outputs again, the first rejection gate other end is input as VCKPP, the rejection gate output signal is VCKN1, VCKN1 and VCKPP are as the input of second level rejection gate, output signal is VCKSP1, and VCKSP1 obtains signal VCKSP through the one-level phase inverter again;

Wherein, square-wave signal VCKPP obtains the grid that signal VCKP inputs the 9th NMOS pipe M9 and the 13 PMOS pipe M13 from the input end of logic control circuit through two phase inverters, another control signal VCKN opposite with VCKP inputs the grid of the tenth PMOS pipe M10 and the 12 NMOS pipe M12, the 9th NMOS pipe M9 and the tenth PMOS pipe M10 form transmission gate switch, connect charging capacitor C0.In front half input clock cycle, the 9th NMOS pipe M9 and the tenth PMOS pipe M10 form the transmission gate switch conducting, are charged to charging capacitor C0 by the steady current source circuit; Rear half input cycle, the 9th NMOS pipe M9 and the tenth PMOS pipe M10 form transmission gate switch and disconnect, charging finishes, and the voltage peak on the charging capacitor C0 keeps a period of time, the transmission gate switch conducting that this moment, the 12 NMOS pipe M12 and the 13 PMOS pipe M13 formed, late-class circuit begins sampling, bias current sources is formed into the path on ground simultaneously, charging capacitor C0 connects first order source follower, the output of first order source follower connects the transmission gate switch of the 17 PMOS pipe M17 and the 16 NMOS pipe M16 composition, wherein, the signal VCKSP1 of logic control circuit output inputs the grid of the 16 NMOS pipe M16, VCKSP1 obtains signal VCKSP through the one-level phase inverter again and is input to the 17 PMOS pipe M17, the electrode input end of the output termination operational amplifier of the 17 PMOS pipe M17, the output terminal of operational amplifier connects second level source follower, and the negative pole input of the output termination operational amplifier of second level source follower forms negative feedback; Simultaneously the output terminal of operational amplifier and resistance R 0 are connected the RC filter network of composition and are connected with capacitor C; After gathering the sequential end, charging capacitor C0 is by the 11 NMOS pipe M11 discharge; Discharge enters the next cycle after finishing, and continues charging, and crest voltage keeps, the process of discharge;

Wherein, first order source follower is comprised of the 14 NMOS pipe M14 and the 15 PMOS pipe M15, second level source follower is comprised of the 18 PMOS pipe M18 and the 19 PMOS pipe M19, first order source follower produces the level shift of Vgs and is offset by the level displacement circuit that amplifier and second level source follower form by rear class, thereby guarantees that the voltage of operational amplifier output terminal and the voltage on the charging capacitor C0 equate.

Each output control terminal simulation waveform figure of logical circuit is followed successively by the VCKPP signal, the VCKP signal from top to bottom as shown in Figure 3, the VCKN signal, VCKN1 signal, VCKSP1 signal and VCKSP signal, wherein the VCKPP signal is input square-wave signal, the as shown in Figure 3 time sequence status of each signal.Charging capacitor C0 voltage and main body main circuit are wanted the voltage simulation waveform figure of control end in inventing as shown in Figure 4, are followed successively by from top to bottom charging capacitor C0 voltage among the figure, VCKP, VCKN1 and VCKSP1; When the VCKP signal was high level, charging capacitor C0 was in charged state as seen from the figure, and when the VCKSP1 signal was high level, charging capacitor C0 was in the voltage hold mode, and when the VCKN1 signal was high level, charging capacitor C0 was in discharge condition.The charging capacitor C0 voltage of inventing as shown in Figure 5 and the simulation waveform figure of output voltage, as can be seen from the figure, output voltage raises gradually, tends towards stability at 5 all after dates, stable value equates with the peak value of charging capacitor (C0), so the voltage to frequency conversion is more accurate.As shown in Figure 6, when circuit incoming frequency of the present invention changes in the 10MHz-120MHz scope, the variation diagram of output voltage, solid line partly is the relation curve of output voltage and frequency input signal, dotted portion is for asking result reciprocal to this curve, in incoming frequency is 10MHz-110MHz, be the straight line of a fixed slope, verified the inverse relation of output voltage and incoming frequency.As can be seen from the figure, this slope is substantially constant in the incoming frequency scope of 10MHz-110MHz, so this FV convertor can accurately distinguish the incoming frequency of 10MHz-110MHz, has shown the incoming frequency scope wider.

Claims

1. frequency-voltage conversion circuit is characterized in that: comprise logic control circuit and main body circuit,

Described main body circuit comprises: current biasing circuit, steady current source circuit, transmission gate switch, discharge switch, charging capacitor, source follower, sample circuit, level displacement circuit and RC filter network, wherein, described current biasing circuit provides biasing for described steady current source circuit, in front half input cycle, described transmission gate switch makes described steady current source circuit to described charging capacitor charging according to the control signal that described logic control circuit provides; In rear half period, described transmission gate switch switches to ground according to the control signal that described logic control circuit provides with steady current, by delayed discharge, crest voltage on the described charging capacitor keeps, the control signal conducting that sampling switch in the described sample circuit of while provides according to described logic control circuit, so that the crest voltage on the described charging capacitor flows into described sample circuit behind described source follower, described sample circuit collection is also stored this magnitude of voltage, after the sample circuit sampling finishes, described sampling switch disconnects according to the control signal that described logic control circuit provides, the control signal conducting that discharge switch provides according to described logic control circuit, described charging capacitor discharge, the voltage of simultaneously described sample circuit output are successively through exporting behind described level displacement circuit and the described RC filter network.

2. frequency-voltage conversion circuit according to claim 1, it is characterized in that: described steady current source circuit comprises the 5th PMOS pipe (M5), the 6th PMOS manages (M6), the 7th PMOS manages (M7), the 8th PMOS pipe (M8) and the 20 NMOS pipe (M20), the common-source amplifier of current source load the 20 NMOS pipe (M20) that wherein said the 5th PMOS pipe (M5) and the 6th PMOS pipe (M6) consist of, described common-source amplifier and the 8th PMOS pipe (M8) consist of feedback loop, and described feedback loop is clamped at the drain voltage that the 7th PMOS manages (M7) on the fixed value.