CN203180884U - Chaos analog circuit realizing natural exponent - Google Patents
Chaos analog circuit realizing natural exponent Download PDFInfo
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- CN203180884U CN203180884U CN 201320157784 CN201320157784U CN203180884U CN 203180884 U CN203180884 U CN 203180884U CN 201320157784 CN201320157784 CN 201320157784 CN 201320157784 U CN201320157784 U CN 201320157784U CN 203180884 U CN203180884 U CN 203180884U
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Abstract
The utility model discloses a chaos analog circuit realizing natural exponent. According to the utility model, with a single diode, voltage natural exponent calculation is realized. With a PN junction thermal voltage compensation circuit, an exponent chaotic circuit is simpler, more precise, and more stable. With the natural exponent chaotic circuit, more complicated chaotic signals can be produced. The circuit can be used in confidential communication and information encryption based on chaos, such that information safety is higher. According to the utility model, chaotic system types and number are enriched, and circuit type realizing chaotic system is increased. The method and circuit realizing exponentiation calculation can be applied in other fields requiring exponentiation calculation.
Description
Technical field
The utility model relates to a kind of method that realizes chaos circuit, is specifically related to a kind of chaos analog circuit of realizing the nature index.
Background technology
Chaotic signal has continuous wide range and class stochastic behaviour, can be applicable to secure communication.The required chaotic signal of secure communication is produced by chaos circuit, and its fail safe depends on the complexity of chaotic signal, has just produced complicated chaotic signal just because of system self non-linear.Existing chaos system generally have piecewise linearity,
XYOr
,
The nonlinear terms of type, and the chaos that natural index nonlinear terms produce is more complicated.Contain at present
The chaos system of nonlinear terms is reported, but its index is realized circuit two triodes and two diodes, and circuit is complicated and be difficult to coupling, and natural index chaos system is also fewer, and this is the deficiencies in the prior art parts.Therefore, construct the chaos system of new natural index, especially provide a kind of optimization method that designs the index chaos circuit and be very important.
Summary of the invention
The utility model has proposed a kind of chaos analog circuit of realizing the nature index at the deficiencies in the prior art.
A kind of chaos analog circuit of realizing the nature index of the utility model comprises the first integrated operational amplifier U1, the second integrated operational amplifier U2, the 3rd integrated operational amplifier U3, the first multiplier U4, the second multiplier U5, the 3rd multiplier U6, the first build-out resistor R1, the second build-out resistor R2, the 3rd build-out resistor R3, the 4th build-out resistor R4, the 5th build-out resistor R7, the 6th build-out resistor R8, the 7th build-out resistor R13, the 8th build-out resistor R15, the 9th build-out resistor R16, the tenth build-out resistor R17, the 11 build-out resistor R18, the 12 build-out resistor R19, the 13 build-out resistor R20, the first variable resistor R5, the second adjustable resistance R6, the 3rd variable resistor R9, the 4th variable resistor R10, the 5th variable resistor R11, the 6th variable resistor R12, the 7th variable resistor R14, the 8th variable resistor R21, the 9th variable resistor R22, first capacitor C 1, second capacitor C 2, the 3rd capacitor C 3 and diode D1; It is LF347 that the described first integrated operational amplifier U1, the second integrated operational amplifier U2, the 3rd integrated operational amplifier U3 adopt signal, and the signal that the described first multiplier U4, the second multiplier U5, the 3rd multiplier U6 adopt is AD633JN;
1 pin of the described first integrated operational amplifier U1 is connected with the end of the 5th build-out resistor R7, the end of the 6th build-out resistor R8, the other end of the 5th build-out resistor R7 is connected with the end of the 3rd variable resistor R9, the end of the 4th variable resistor R10 and 2 pin of the first integrated operational amplifier U1, the other end of the 3rd variable resistor R9 is connected with an end of second capacitor C 2,1 pin of the second integrated operational amplifier U2, the end of the first variable resistor R5 and 3 pin of the second multiplier U5, and the other end of the 4th variable resistor R10 is connected with 7 pin of the first multiplier U4; 3 pin of the first integrated operational amplifier U1,5 pin, 10 pin, 12 pin ground connection, 4 pin connect+the 15V power supply, 11 pin connect-the 15V power supply, the end of 6 pin and the second build-out resistor R2, one end of first capacitor C 1 connects, the end of the other end of the second build-out resistor R2 and the first build-out resistor R1,14 pin of the first integrated operational amplifier U1 connect, 1 pin of the other end of first capacitor C 1 and the second multiplier U5,7 pin of the first integrated operational amplifier U1 are connected with the end of the 3rd build-out resistor R3, the other end of the other end of the first build-out resistor R1 and the first variable resistor R5, the end of the second adjustable resistance R6 is connected with 13 pin of the first integrated operational amplifier U1,8 pin of the other end of the second adjustable resistance R6 and the first integrated operational amplifier U1, the end of the 4th build-out resistor R4,1 pin of the first multiplier U4 is connected with the end of the 7th variable resistor R14,9 pin of the first integrated operational amplifier U1 and the other end of the 3rd build-out resistor R3, the other end of the 4th build-out resistor R4 connects;
2 pin of the described first multiplier U4,4 pin, 6 pin ground connection, 3 pin of the first multiplier U4 are connected with an end of the end of the 12 build-out resistor R19, the 3rd capacitor C 3 and 8 pin of the second integrated operational amplifier U2; 5 pin of the first multiplier U4 connect-the 15V power supply, and 8 pin connect+the 15V power supply;
2 pin of the described second integrated operational amplifier U2 and the other end of the 6th build-out resistor R8, the other end of second capacitor C 2 connects, 3 pin, 5 pin, 10 pin, 12 pin ground connection, 4 pin connect the 15V power supply, the 11st pin connects-the 15V power supply, the end of 6 pin and the 9th build-out resistor R16, the end of the 8th variable resistor R21, the end of the 9th variable resistor R22 is connected with the end of the tenth build-out resistor R17,8 pin of the other end of the 9th build-out resistor R16 and the 3rd integrated operational amplifier U3, the end of the 7th build-out resistor R13 connects, 14 pin of the other end of the 8th variable resistor R21 and the second integrated operational amplifier U2, the 13 build-out resistor R20 connects, and the other end of the 9th variable resistor R22 is connected with 7 pin of the second multiplier U5; 7 pin of the second integrated operational amplifier U2 are connected with the end of the other end of the tenth build-out resistor R17, the 11 build-out resistor R18,13 pin are connected with the other end of the 12 build-out resistor R19, the other end of the 13 build-out resistor R20, and 9 pin are connected with the other end of the 3rd capacitor C 3, the other end of the 11 build-out resistor R18;
2 pin of the described second multiplier U5,4 pin, 6 pin ground connection, 5 pin connect-the 15V power supply, and 8 pin connect+the 15V power supply;
The end of 1 pin of described the 3rd integrated operational amplifier U3 and the 5th variable resistor R11,1 pin of the 3rd multiplier U6,3 pin connect, the other end of 2 pin and the 5th variable resistor R11, the other end of the 7th variable resistor R14 connects, 3 pin, 5 pin, 10 pin ground connection, 4 pin connect+the 15V power supply, 11 pin connect-the 15V power supply, the end of 6 pin and the 6th variable resistor R12, the negative electrode of diode D1 connects, the other end of 7 pin and the 6th variable resistor R12, the end of the 8th build-out resistor R15 connects, the other end of 9 pin and the 7th build-out resistor R13, the other end of the 8th build-out resistor R15 connects, 12 pin, 13 pin, 14 foot rest skies;
2 pin of described the 3rd multiplier U6,4 pin, 6 pin ground connection, 5 pin connect-the 15V power supply, and 8 pin connect+the 15V power supply, and 7 pin are connected with the anode of diode D1.
The beneficial effects of the utility model:
Index chaos analog circuit of the present utility model only contains a diode, simple in structure, computing is accurate, good stability, can produce in the more complicated chaotic signal supply usefulness and select, increase the circuit types of chaos system and realization chaos system, and can form automatically switched chaotic system with existing chaos system.
Description of drawings
Fig. 1 is structure chart of the present utility model;
Fig. 2 is schematic diagram of the present utility model.
Embodiment
As shown in Figure 1, a kind of chaos analog circuit of realizing the nature index of the utility model comprises the first integrated operational amplifier U1, the second integrated operational amplifier U2, the 3rd integrated operational amplifier U3, the first multiplier U4, the second multiplier U5, the 3rd multiplier U6, the first build-out resistor R1, the second build-out resistor R2, the 3rd build-out resistor R3, the 4th build-out resistor R4, the 5th build-out resistor R7, the 6th build-out resistor R8, the 7th build-out resistor R13, the 8th build-out resistor R15, the 9th build-out resistor R16, the tenth build-out resistor R17, the 11 build-out resistor R18, the 12 build-out resistor R19, the 13 build-out resistor R20, the first variable resistor R5, the second adjustable resistance R6, the 3rd variable resistor R9, the 4th variable resistor R10, the 5th variable resistor R11, the 6th variable resistor R12, the 7th variable resistor R14, the 8th variable resistor R21, the 9th variable resistor R22, first capacitor C 1, second capacitor C 2, the 3rd capacitor C 3 and diode D1; It is LF347 that the described first integrated operational amplifier U1, the second integrated operational amplifier U2, the 3rd integrated operational amplifier U3 adopt signal, and the signal that the described first multiplier U4, the second multiplier U5, the 3rd multiplier U6 adopt is AD633JN;
1 pin of the described first integrated operational amplifier U1 is connected with the end of the 5th build-out resistor R7, the end of the 6th build-out resistor R8, the other end of the 5th build-out resistor R7 is connected with the end of the 3rd variable resistor R9, the end of the 4th variable resistor R10 and 2 pin of the first integrated operational amplifier U1, the other end of the 3rd variable resistor R9 is connected with an end of second capacitor C 2,1 pin of the second integrated operational amplifier U2, the end of the first variable resistor R5 and 3 pin of the second multiplier U5, and the other end of the 4th variable resistor R10 is connected with 7 pin of the first multiplier U4; 3 pin of the first integrated operational amplifier U1,5 pin, 10 pin, 12 pin ground connection, 4 pin connect+the 15V power supply, 11 pin connect-the 15V power supply, the end of 6 pin and the second build-out resistor R2, one end of first capacitor C 1 connects, the end of the other end of the second build-out resistor R2 and the first build-out resistor R1,14 pin of the first integrated operational amplifier U1 connect, 1 pin of the other end of first capacitor C 1 and the second multiplier U5,7 pin of the first integrated operational amplifier U1 are connected with the end of the 3rd build-out resistor R3, the other end of the other end of the first build-out resistor R1 and the first variable resistor R5, the end of the second adjustable resistance R6 is connected with 13 pin of the first integrated operational amplifier U1,8 pin of the other end of the second adjustable resistance R6 and the first integrated operational amplifier U1, the end of the 4th build-out resistor R4,1 pin of the first multiplier U4 is connected with the end of the 7th variable resistor R14,9 pin of the first integrated operational amplifier U1 and the other end of the 3rd build-out resistor R3, the other end of the 4th build-out resistor R4 connects;
2 pin of the described first multiplier U4,4 pin, 6 pin ground connection, 3 pin of the first multiplier U4 are connected with an end of the end of the 12 build-out resistor R19, the 3rd capacitor C 3 and 8 pin of the second integrated operational amplifier U2; 5 pin of the first multiplier U4 connect-the 15V power supply, and 8 pin connect+the 15V power supply;
2 pin of the described second integrated operational amplifier U2 and the other end of the 6th build-out resistor R8, the other end of second capacitor C 2 connects, 3 pin, 5 pin, 10 pin, 12 pin ground connection, 4 pin connect the 15V power supply, the 11st pin connects-the 15V power supply, the end of 6 pin and the 9th build-out resistor R16, the end of the 8th variable resistor R21, the end of the 9th variable resistor R22 is connected with the end of the tenth build-out resistor R17,8 pin of the other end of the 9th build-out resistor R16 and the 3rd integrated operational amplifier U3, the end of the 7th build-out resistor R13 connects, 14 pin of the other end of the 8th variable resistor R21 and the second integrated operational amplifier U2, the 13 build-out resistor R20 connects, and the other end of the 9th variable resistor R22 is connected with 7 pin of the second multiplier U5; 7 pin of the second integrated operational amplifier U2 are connected with the end of the other end of the tenth build-out resistor R17, the 11 build-out resistor R18,13 pin are connected with the other end of the 12 build-out resistor R19, the other end of the 13 build-out resistor R20, and 9 pin are connected with the other end of the 3rd capacitor C 3, the other end of the 11 build-out resistor R18;
2 pin of the described second multiplier U5,4 pin, 6 pin ground connection, 5 pin connect-the 15V power supply, and 8 pin connect+the 15V power supply;
The end of 1 pin of described the 3rd integrated operational amplifier U3 and the 5th variable resistor R11,1 pin of the 3rd multiplier U6,3 pin connect, the other end of 2 pin and the 5th variable resistor R11, the other end of the 7th variable resistor R14 connects, 3 pin, 5 pin, 10 pin ground connection, 4 pin connect+the 15V power supply, 11 pin connect-the 15V power supply, the end of 6 pin and the 6th variable resistor R12, the negative electrode of diode D1 connects, the other end of 7 pin and the 6th variable resistor R12, the end of the 8th build-out resistor R15 connects, the other end of 9 pin and the 7th build-out resistor R13, the other end of the 8th build-out resistor R15 connects, 12 pin, 13 pin, 14 foot rest skies;
2 pin of described the 3rd multiplier U6,4 pin, 6 pin ground connection, 5 pin connect-the 15V power supply, and 8 pin connect+the 15V power supply, and 7 pin are connected with the anode of diode D1.
As shown in Figure 2, a kind of method that realizes the chaos analog circuit of nature index, multiplier U6 realizes voltage
, and keep voltage permanent in just; The positive voltage of multiplier U6 output
Be added on the diode D1, make forward current by diode by natural index variation:
Diode D1 electric current is converted to voltage by index variation by the change-over circuit in the integrated operational amplifier U3, thereby realizes the exponent arithmetic of voltage, and the inverter in the integrated operational amplifier U3 is to voltage
Amplify the thermal voltage in the compensation diode index electric current in advance
, described I
SIt is the characteristic current of diode;
4 operational amplifiers are arranged in the integrated chip LF347, and integrated operational amplifier U1 the 12nd, 13,14 pins and peripheral resistance R 1 thereof, R5, R6 constitute first adder, realize Y+ (X) add operation; The 5th, 6,7 pins of integrated operational amplifier U1 and peripheral resistance R 2 thereof, capacitor C 1 constitute first integrator, and first integrator is output as X; 8th, 9,10 pins and peripheral resistance R 3 thereof, R4 constitute first reverser, X are reversed-X and offer the pin of required-X; First adder, first integrator and first inverter have been realized the computing of first equation of index chaos system:
The 1st, 2,3 pins of integrated operational amplifier U1 and peripheral resistance R 7 thereof, R9, R10 constitute second adder, multiplier U4 realization-XZ computing is also given second adder output, the 1st, 2,3 pins of integrated operational amplifier U2 and peripheral resistance R 8 thereof, capacitor C 2 constitute the second integral device, and the second integral device is output as Y; This second adder and second integral device have been realized the computing of second equation of index chaos system:
The 5th, 6,7 pins of integrated operational amplifier U2 and peripheral resistance R 16 thereof, R17, R21, R22 constitute the 3rd adder, multiplier U5 realizes the XY computing and gives the 3rd adder output, the 8th, 9,10 pins of integrated operational amplifier U2 and peripheral resistance R 18 thereof, capacitor C 3 constitute the third integral device, integrator is output as Z, and the 12nd, 13,14 pins of integrated operational amplifier U2 and peripheral resistance R 19 thereof, R20 constitute second reverser; The 1st, 2,3 pins of integrated operational amplifier U3 and peripheral resistance R 11 thereof, R14 constitute first sign-changing amplifier, deliver to multiplier U6 the 1st, 2 pins after-X is amplified, the voltage of multiplier U6 the 7th pin output
Be added on the diode D1, the index electric current that produces is converted to exponential voltage by the change-over circuit that integrated operational amplifier U3 the 5th, 6,7 pins constitute, this exponential voltage is delivered to the addition that is made of integrated operational amplifier U2 the 5th, 6,7 pins by the negater circuit that integrated operational amplifier U3 the 8th, 9,10 pins constitute, and finishes the computing of the 3rd equation of index chaos system at last:
Above-mentioned explanation is not the restriction to utility model; the utility model also is not limited only to above-mentioned giving an example; the variation that those skilled in the art make in essential scope of the present utility model, remodeling, interpolation or replacement also belong to protection range of the present utility model.
Claims (1)
1. a chaos analog circuit of realizing the nature index comprises the first integrated operational amplifier U1, the second integrated operational amplifier U2, the 3rd integrated operational amplifier U3, the first multiplier U4, the second multiplier U5, the 3rd multiplier U6, the first build-out resistor R1, the second build-out resistor R2, the 3rd build-out resistor R3, the 4th build-out resistor R4, the 5th build-out resistor R7, the 6th build-out resistor R8, the 7th build-out resistor R13, the 8th build-out resistor R15, the 9th build-out resistor R16, the tenth build-out resistor R17, the 11 build-out resistor R18, the 12 build-out resistor R19, the 13 build-out resistor R20, the first variable resistor R5, the second adjustable resistance R6, the 3rd variable resistor R9, the 4th variable resistor R10, the 5th variable resistor R11, the 6th variable resistor R12, the 7th variable resistor R14, the 8th variable resistor R21, the 9th variable resistor R22, first capacitor C 1, second capacitor C 2, the 3rd capacitor C 3 and diode D1; It is LF347 that the described first integrated operational amplifier U1, the second integrated operational amplifier U2, the 3rd integrated operational amplifier U3 adopt signal, and the signal that the described first multiplier U4, the second multiplier U5, the 3rd multiplier U6 adopt is AD633JN;
It is characterized in that: the end of 1 pin of the described first integrated operational amplifier U1 and the 5th build-out resistor R7, the end of the 6th build-out resistor R8 connects, the end of the other end of the 5th build-out resistor R7 and the 3rd variable resistor R9, the end of the 4th variable resistor R10 is connected with 2 pin of the first integrated operational amplifier U1, one end of the other end of the 3rd variable resistor R9 and second capacitor C 2,1 pin of the second integrated operational amplifier U2, the end of the first variable resistor R5 is connected with 3 pin of the second multiplier U5, and the other end of the 4th variable resistor R10 is connected with 7 pin of the first multiplier U4; 3 pin of the first integrated operational amplifier U1,5 pin, 10 pin, 12 pin ground connection, 4 pin connect+the 15V power supply, 11 pin connect-the 15V power supply, the end of 6 pin and the second build-out resistor R2, one end of first capacitor C 1 connects, the end of the other end of the second build-out resistor R2 and the first build-out resistor R1,14 pin of the first integrated operational amplifier U1 connect, 1 pin of the other end of first capacitor C 1 and the second multiplier U5,7 pin of the first integrated operational amplifier U1 are connected with the end of the 3rd build-out resistor R3, the other end of the other end of the first build-out resistor R1 and the first variable resistor R5, the end of the second adjustable resistance R6 is connected with 13 pin of the first integrated operational amplifier U1,8 pin of the other end of the second adjustable resistance R6 and the first integrated operational amplifier U1, the end of the 4th build-out resistor R4,1 pin of the first multiplier U4 is connected with the end of the 7th variable resistor R14,9 pin of the first integrated operational amplifier U1 and the other end of the 3rd build-out resistor R3, the other end of the 4th build-out resistor R4 connects;
2 pin of the described first multiplier U4,4 pin, 6 pin ground connection, 3 pin of the first multiplier U4 are connected with an end of the end of the 12 build-out resistor R19, the 3rd capacitor C 3 and 8 pin of the second integrated operational amplifier U2; 5 pin of the first multiplier U4 connect-the 15V power supply, and 8 pin connect+the 15V power supply;
2 pin of the described second integrated operational amplifier U2 and the other end of the 6th build-out resistor R8, the other end of second capacitor C 2 connects, 3 pin, 5 pin, 10 pin, 12 pin ground connection, 4 pin connect the 15V power supply, the 11st pin connects-the 15V power supply, the end of 6 pin and the 9th build-out resistor R16, the end of the 8th variable resistor R21, the end of the 9th variable resistor R22 is connected with the end of the tenth build-out resistor R17,8 pin of the other end of the 9th build-out resistor R16 and the 3rd integrated operational amplifier U3, the end of the 7th build-out resistor R13 connects, 14 pin of the other end of the 8th variable resistor R21 and the second integrated operational amplifier U2, the 13 build-out resistor R20 connects, and the other end of the 9th variable resistor R22 is connected with 7 pin of the second multiplier U5; 7 pin of the second integrated operational amplifier U2 are connected with the end of the other end of the tenth build-out resistor R17, the 11 build-out resistor R18,13 pin are connected with the other end of the 12 build-out resistor R19, the other end of the 13 build-out resistor R20, and 9 pin are connected with the other end of the 3rd capacitor C 3, the other end of the 11 build-out resistor R18;
2 pin of the described second multiplier U5,4 pin, 6 pin ground connection, 5 pin connect-the 15V power supply, and 8 pin connect+the 15V power supply;
The end of 1 pin of described the 3rd integrated operational amplifier U3 and the 5th variable resistor R11,1 pin of the 3rd multiplier U6,3 pin connect, the other end of 2 pin and the 5th variable resistor R11, the other end of the 7th variable resistor R14 connects, 3 pin, 5 pin, 10 pin ground connection, 4 pin connect+the 15V power supply, 11 pin connect-the 15V power supply, the end of 6 pin and the 6th variable resistor R12, the negative electrode of diode D1 connects, the other end of 7 pin and the 6th variable resistor R12, the end of the 8th build-out resistor R15 connects, the other end of 9 pin and the 7th build-out resistor R13, the other end of the 8th build-out resistor R15 connects, 12 pin, 13 pin, 14 foot rest skies;
2 pin of described the 3rd multiplier U6,4 pin, 6 pin ground connection, 5 pin connect-the 15V power supply, and 8 pin connect+the 15V power supply, and 7 pin are connected with the anode of diode D1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320157784 CN203180884U (en) | 2013-04-01 | 2013-04-01 | Chaos analog circuit realizing natural exponent |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320157784 CN203180884U (en) | 2013-04-01 | 2013-04-01 | Chaos analog circuit realizing natural exponent |
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|---|---|
| CN203180884U true CN203180884U (en) | 2013-09-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201320157784 Expired - Fee Related CN203180884U (en) | 2013-04-01 | 2013-04-01 | Chaos analog circuit realizing natural exponent |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104035745B (en) * | 2014-06-05 | 2017-01-11 | 杭州电子科技大学 | Logarithm loga x operating circuit and implementation method thereof |
-
2013
- 2013-04-01 CN CN 201320157784 patent/CN203180884U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104035745B (en) * | 2014-06-05 | 2017-01-11 | 杭州电子科技大学 | Logarithm loga x operating circuit and implementation method thereof |
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