CN203104411U - A phase-locking frequency synthesizer and an adaptive frequency calibrating circuit - Google Patents
A phase-locking frequency synthesizer and an adaptive frequency calibrating circuit Download PDFInfo
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- CN203104411U CN203104411U CN 201220745723 CN201220745723U CN203104411U CN 203104411 U CN203104411 U CN 203104411U CN 201220745723 CN201220745723 CN 201220745723 CN 201220745723 U CN201220745723 U CN 201220745723U CN 203104411 U CN203104411 U CN 203104411U
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Abstract
The utility model discloses a phase-locking frequency synthesizer and an adaptive frequency calibrating circuit. The phase-locking frequency synthesizer containing the adaptive frequency calibrating circuit comprises a phase frequency detector, a charge pump, a loop filter, a variable counter, a voltage-controlled oscillator, an adaptive frequency calibrating circuit, and a control switch and is characterized in that the adaptive frequency calibrating circuit comprises a counter, a comparator, and a state machine, that the voltage-controlled oscillator receives a reference voltage signal with the control switch and generates a frequency signal in order to output the frequency signal to the variable counter, and that after performing frequency division processing on the received signal, the variable counter outputs a frequency division clock signal of the voltage-controlled oscillator to the counter and the phase frequency detector. The output frequency of the voltage-controlled oscillator is firstly controlled by the digital signal outputted by the adaptive frequency calibrating circuit in order that the frequency division clock signal of the voltage-controlled oscillator is adjusted to be similar to the frequency of a reference clock signal. Then the frequency of the voltage-controlled oscillator is further adjusted by a control voltage outputted by the loop filter.
Description
Technical field
The utility model relates to frequency synthesizer of phase locking, is specifically related to frequency synthesizer of phase locking and adaptive frequency calibration circuit.
Background technology
Frequency synthesizer of phase locking is a kind of frequency synthesizer that adopts phase-locked loop (PL) to carry out frequency synthesis, and it is present frequency synthesizer main flow.Phase-locking type integer frequency synthesizer by phase frequency detector (PFD), charge pump (CP), variable counter (/N), loop filter (LPF), voltage controlled oscillator parts such as (VCO) form.Frequency synthesizer of phase locking is a phase error control system, the phase difference between its comparator input signal and the voltage controlled oscillator output signal, thus produce the frequency that error control voltage is adjusted voltage controlled oscillator, to reach and input signal frequency together.When loop is started working, if the input reference clock frequency is different with the VCO clock frequency, then owing to have intrinsic difference on the frequency between two signals, the phase difference between them certainly will change always, and the error voltage of phase frequency detector output as a result just changes within the specific limits.Under the control of this error voltage, the frequency of voltage controlled oscillator is also changing.
And the operating frequency of voltage controlled oscillator is very responsive to technology, and particularly the frequency of oscillation of voltage controlled oscillator is more than 1000MHz, and the process deviation that different batches chip and technology itself is caused can influence the consistency of VCO frequency.Increase the frequency coverage of voltage controlled frequency gain can the increasing VCO of VCO, offset the influence of process deviation to a certain extent, but the voltage controlled gain of increase VCO can increase the phase noise of VCO the VCO frequency.
Its function of AFC (calibration of Adaptive Frequency Calibration adaptive frequency) is at the phase-locked initial stage of frequency locking, produce the voltage-controlled voltage of a certain fixed voltage by reference circuit as VCO, compare by the clock frequency of certain algorithm after, thereby adjust the frequency of oscillation of voltage controlled oscillator reference clock and VCO frequency division.
The utility model content
One of technical problem to be solved in the utility model is to provide the frequency synthesizer of phase locking with adaptive frequency calibration circuit.
Two of technical problem to be solved in the utility model is to provide segmented voltage controlled oscillator adaptive frequency calibration circuit.
In order to solve the problems of the technologies described above, first technical scheme of the present utility model is, frequency synthesizer of phase locking with adaptive frequency calibration circuit, comprise phase frequency detector, charge pump, loop filter, variable counter, voltage controlled oscillator, adaptive frequency calibration circuit and control switch, it is characterized in that: the adaptive frequency calibration circuit comprises counter, comparator and state machine;
Voltage controlled oscillator receives reference voltage signal by control switch, produces frequency signal and outputs to variable counter;
Variable counter is carried out frequency division with the signal of receiving and is handled the sub-frequency clock signal of back output voltage controlled oscillator to counter and phase frequency detector;
Counter receives the sub-frequency clock signal of reference clock signal and voltage controlled oscillator simultaneously and counts, and when one of them clock signal counting finished, counter produced a pulse signal and outputs to comparator;
Comparator compares after receiving the pulse signal of counter output, produces index signal and produces the state machine clock signal simultaneously according to comparative result again and export to state machine in the lump;
State machine is subjected to the control of the state machine clock signal of comparator output, and according to index signal, produces control signal and output to voltage controlled oscillator, to adjust the clock signal frequency of voltage controlled oscillator; When the sub-frequency clock signal frequency of voltage controlled oscillator equals the reference clock signal frequency, the state machine output switch control signal, make the disconnection of control switch and reference voltage signal and connect the control voltage signal that voltage controlled oscillator is exported by control switch reception loop filter with loop filter.
The utility model adopts voltage controlled oscillator is divided into some frequency ranges, to increase the frequency range of voltage controlled oscillator, each frequency range of voltage controlled oscillator all has less voltage controlled frequency gain, and a plurality of frequency range can cover required frequency range fully and keep certain surplus; Compare with the conventional P L loop that adopts phase frequency detector, the voltage controlled oscillator output frequency is at first controlled by the digital signal of adaptive frequency calibration circuit output, automatically seek the frequency range of suitable target frequency, it is close with the reference clock signal frequency that the sub-frequency clock signal frequency of voltage controlled oscillator can be adjusted to, and remain operating in this frequency range; Further adjust the frequency of voltage controlled oscillator again by the control voltage of loop filter output, reach stable after, frequency difference between reference clock signal and the voltage controlled oscillator sub-frequency clock signal is zero, differ no longer in time and change, error voltage is a fixed value, and at this moment loop just enters " locking " state.Adopt frequency segmentation structure and adaptive frequency calibration circuit, can avoid the VC0 frequency to be subjected to the influence of process deviation, even the inconsistent frequency change that causes voltage controlled oscillator of technology, in setting range, always make voltage controlled oscillator satisfy required frequency requirement, guarantee the chip consistency, improve the finished product rate; And whole calibration operation is finished automatically by chip internal, need not external control, has both satisfied the consistency problem of pressuring controlling oscillator frequency, has simplified application scheme simultaneously.
Described state machine comprises logical circuit, registers group one and registers group two; Registers group one and registers group two all are subjected to the control of the state machine clock signal of comparator output; Registers group one adds/register of subtrahend as storage; The data of logical circuit receiving register group one output, and receive the index signal of comparator output simultaneously, carry out outputing to registers group two after the logical operation, registers group two produces control signal and outputs to voltage controlled oscillator, to adjust the clock signal frequency of voltage controlled oscillator.
Described registers group one is by n register, n-1 register, n-2 register ... first register, the 0th register are formed; Registers group two is by m register, m-1 register ... the 1st register is formed; Logical circuit by n logic circuit unit and the 0th or the door constitute, wherein: the natural number of n 〉=2; M=n; Each logic circuit unit include one with the door, one or and an XOR gate; N register, n-1 register, n-2 register ... first register, the 0th register adopt the serial annular to connect; N is connected the output Q of n-1 register with 1 input of door, n is connected the comparison index signal output of comparator with other 1 input of door; N is connected an input of n or door with the output of door, another input of n or door connects the output Q of n register, the output of n or door connects an input of n XOR gate, another input of n XOR gate connects the output Q of m register, and the output of n XOR gate connects the input D of m register; And the like, first is connected the output Q of the 0th register with 1 input of door, first with other 1 input be connected the comparison index signal output of comparator; First with the door output is connected first or an input, first or another input of door connect the output Q of first register, first or the output of door connect an input of first XOR gate, another input of first XOR gate connects the output Q of the 1st register, and the output of first XOR gate connects the input D of the 1st register; M register, m-1 register ... the output Q of the 1st register exports n position control signal altogether to voltage controlled oscillator; N register, n-1 register, n-2 register ... the clock signal input terminal of first register, the 0th register and m register, m-1 register ... the clock signal input terminal of the 1st register all connects the state machine clock signal output part of comparator; The n register, the n-2 register ... first register, the reset terminal CLR of the 0th register, the set end SET and the m-1 register of n-1 register ... the reset terminal CLR of the 1st register and the set end SET of m register all are connected reset signal, this reset signal is imported by the outside, the identical index signal output connection the 0th of comparator or an input of door, the 0th or another input of door connect the output Q of n register, the 0th or the output output switch control signal of door to control switch, control control switch and be connected with reference voltage signal or be connected with variable counter.
Second technical scheme of the present utility model is that segmented voltage controlled oscillator adaptive frequency calibration circuit comprises comparator, counter and state machine, is characterized in:
The sub-frequency clock signal of reference clock signal and voltage controlled oscillator enter counter is simultaneously counted, and when one of them clock signal counting finished, counter produced a pulse signal and outputs to comparator; Represent that one of them clock signal counting finishes;
Comparator compares after receiving the pulse signal of counter output, to be the counting end earlier of which clock in the sub-frequency clock signal of determining reference clock signal and voltage controlled oscillator or to count simultaneously and finish, the frequency size that promptly compares the sub-frequency clock signal of reference clock signal and voltage controlled oscillator produces index signal and produces the state machine clock signal simultaneously according to comparative result again and exports to state machine in the lump;
State machine is subjected to the control of the state machine clock signal of comparator output, and according to index signal, produces control signal and output to voltage controlled oscillator, to adjust the clock signal frequency of voltage controlled oscillator.
The beneficial effect of described frequency synthesizer of phase locking of utility model and adaptive frequency calibration circuit is: the utility model is compared with the conventional P LL loop that adopts phase frequency detector, the voltage controlled oscillator output frequency is at first controlled by the digital signal of adaptive frequency calibration circuit output, it is close with the reference clock signal frequency that the sub-frequency clock signal frequency of voltage controlled oscillator can be adjusted to, and remain operating in this frequency range.Further adjust the frequency of voltage controlled oscillator again by the control voltage of loop filter output, until loop " locking "; Adopt frequency segmentation structure and adaptive frequency calibration circuit, can avoid pressuring controlling oscillator frequency to be subjected to the influence of process deviation, guarantee the chip consistency, improve the finished product rate; And whole calibration operation is finished automatically by chip internal, need not external control, has both satisfied the consistency problem of pressuring controlling oscillator frequency, has simplified application scheme simultaneously; The utility model is simple in structure, and cost is low, performance is excellent, has a good application prospect.
Description of drawings
Fig. 1 is the theory diagram of segmented voltage controlled oscillator adaptive frequency calibration circuit described in the utility model.
Fig. 2 is the schematic diagram of state machine described in the utility model.
Fig. 3 is the theory diagram with frequency synthesizer of phase locking of adaptive frequency calibration circuit described in the utility model.
The frequency of Fig. 4 segmented voltage controlled oscillator and voltage-controlled voltage curve.
Fig. 5 is the state machine control flow chart.
Embodiment
Referring to Fig. 1 to Fig. 3, frequency synthesizer of phase locking with adaptive frequency calibration circuit, comprise phase frequency detector 14, charge pump 15, loop filter 16, variable counter 17, voltage controlled oscillator 18, adaptive frequency calibration circuit 10 and control switch 19, wherein: adaptive frequency calibration circuit 10 comprises counter 11, comparator 12 and state machine 13;
Voltage controlled oscillator 18 receives reference voltage signal by control switch 19, produces frequency signal and outputs to variable counter 17;
In specific embodiment, state machine 13 comprises logical circuit 33, registers group 1 and registers group 2 32; Registers group 1 and registers group 2 32 all are subjected to the control of the state machine clock signal of comparator 12 outputs; Registers group 1 adds/register of subtrahend as storage; The data of logical circuit 33 receiving register groups one 31 outputs, and receive the index signal of comparator 12 output simultaneously, carry out outputing to registers group 2 32 after the logical operation, registers group 2 32 produces control signal and outputs to voltage controlled oscillator 18, to adjust the clock signal frequency of voltage controlled oscillator 18.
Described registers group 1 is by n register DSn, n-1 register DSn-1, n-2 register DSn-2 ... the first register DS1, the 0th register DS0 form; Registers group 2 32 is by m register DOn, m-1 register D0n-1 ... the 1st register D01 forms; Logical circuit by n logic circuit unit and the 0th or the door 0R constitute; Wherein: the natural number of n 〉=2; M=n; Each logic circuit unit include one with the door, one or and an XOR gate; N register DSn, n-1 register DSn-1, n-2 register DSn-2 ... the first register DS1, the 0th register DS0 adopt the serial annular to connect; N is connected the output Q of n-1 register DSn-1 with 1 input of door ANDn, n is connected the comparison index signal output of comparator 12 with other 1 input of door ANDn; Relatively the sub-frequency clock signal frequency of index signal output " 1 " expression voltage controlled oscillator is higher than the reference clock signal frequency; The sub-frequency clock signal frequency of output " 0 " expression voltage controlled oscillator is lower than the reference clock signal frequency; N is connected the input of n or door ORn with the output of door ANDn, another input of n or door ORn connects the output Q of n register DSn, the output of n or door ORn connects the input of n XOR gate XORn, another input of n XOR gate XORn connects the output Q of m register DOn, and the output of n XOR gate XORn connects the input D of m register DOn; And the like, first is connected the output Q of the 0th register DS0 with 1 input of door AND1, and first is connected the comparison index signal output of comparator 12 with other 1 input of an AND1; First is connected first or the input of OR1 with the output of door AND1, first or another input of door OR1 connect the output Q of the first register DS1, first or the output of door OR1 connect the input of the first XOR gate XOR1, another input of the first XOR gate XOR1 connects the output Q of the 1st register D01, and the output of the first XOR gate XOR1 connects the input D of the 1st register D01; M register DOn, m-1 register D0n-1 ... the output Q of the 1st register D01 exports n position control signal altogether to voltage controlled oscillator; N register DSn, n-1 register DSn-1, n-2 register DSn-2 ... the clock signal input terminal of the first register DS1, the 0th register DS0 and m register DOn, m-1 register D0n-1 ... the clock signal input terminal of the 1st register D01 all connects the state machine clock signal output part of comparator 12; N register DSn, n-2 register DSn-2 ... the reset terminal CLR of the first register DS1, the 0th register DS0, set end SET and the m-1 register D0n-1 of n-1 register DSn-1 ... the reset terminal CLR of the 1st register D01 all is connected reset signal with the set end SET of m register D0n, this reset signal is provided by the outside, this signal begins state machine is resetted before each selections function on automatically, reset finish after state machine begin to rework; The identical index signal output connection the 0th of comparator 12 or the input of door 0R, the 0th or another input of door 0R connect the output Q of n register DSn, the 0th or the door the output output switch control signal to control switch 19, control control switch 19 is connected with reference voltage signal or is connected with variable counter 17, and the work of output " 1 " expression state machine is finished; Control control switch 19 disconnects with reference voltage signal, is connected with variable counter 17.
Referring to Fig. 1, frequency synthesizer of phase locking segmented voltage controlled oscillator adaptive frequency calibration circuit comprises counter 11, comparator 12 and state machine 13, wherein:
The sub-frequency clock signal of reference clock signal and voltage controlled oscillator enter counter 11 is simultaneously counted, and when one of them clock signal counting finished, counter 11 produced a pulse signal and outputs to comparator 12;
The utility model adopts the scheme that VCO is divided into some frequency ranges to increase the frequency range of VCO, and each frequency range of VCO all has less voltage controlled frequency gain, and a plurality of frequency range can cover required frequency range fully and keep certain surplus.Because VCO is divided into plurality of sections, at a time have only a VCO frequency range in work, select the work of VCO frequency range to finish by the AFC circuit.Referring to Fig. 3, Fig. 4, Fig. 3 is the theory diagram with frequency synthesizer of phase locking of adaptive frequency calibration circuit, the frequency of Fig. 4 segmented voltage controlled oscillator and voltage-controlled voltage curve, and the x axle is voltage-controlled voltage V among Fig. 4, the y axle is VCO frequency MHz.
In specific embodiment, described state machine 13 comprises logical circuit 33, registers group 1 and registers group 2 32; Registers group 1 and registers group 2 32 all are subjected to the control of the state machine clock signal of comparator 12 outputs; Registers group 1 adds/register of subtrahend as storage; The data of logical circuit 33 receiving register groups one 31 outputs, and receive the index signal of comparator 12 output simultaneously, carry out outputing to registers group 2 32 after the logical operation, registers group 2 32 produces control signal and outputs to voltage controlled oscillator 18, to adjust the clock signal frequency of voltage controlled oscillator 18.
In the specific implementation, referring to Fig. 2, described registers group one is by n register DSn, n-1 register DSn-1, n-2 register DSn-2 ... the first register DS1, the 0th register DS0 form; Registers group two is by m register DOn, m-1 register D0n-1 ... the 1st register D01 forms; Logical circuit by n logic circuit unit and the 0th or the door 0R constitute; Wherein: the natural number of n 〉=2; M=n; Each logic circuit unit include one with the door, one or and an XOR gate; N register DSn, n-1 register DSn-1, n-2 register DSn-2 ... the first register DS1, the 0th register DS0 adopt the serial annular to connect; N is connected the output Q of n-1 register DSn-1 with 1 input of door ANDn, n is connected the comparison index signal output of comparator with other 1 input of door ANDn; Relatively the sub-frequency clock signal frequency of index signal output " 1 " expression voltage controlled oscillator is higher than reference clock frequency; The sub-frequency clock signal frequency of output " 0 " expression voltage controlled oscillator is lower than reference clock frequency; N is connected the input of n or door ORn with the output of door ANDn, another input of n or door ORn connects the output Q of n register DSn, the output of n or door ORn connects the input of n XOR gate XORn, another input of n XOR gate XORn connects the output Q of m register DOn, and the output of n XOR gate XORn connects the input D of m register DOn; And the like, first is connected the output Q of the 0th register DS0 with 1 input of door AND1, and first is connected the comparison index signal output of comparator 12 with other 1 input of an AND1; First is connected first or the input of OR1 with the output of door AND1, first or another input of door 0R1 connect the output Q of the first register DS1, first or the output of door OR1 connect the input of the first XOR gate XOR1, another input of the first XOR gate XOR1 connects the output Q of the 1st register D01, and the output of the first XOR gate XOR1 connects the input D of the 1st register D01; M register DOn, m-1 register D0n-1 ... the output Q of the 1st register D01 exports n position control signal altogether to voltage controlled oscillator; N register DSn, n-1 register DSn-1, n-2 register DSn-2 ... the clock signal input terminal of the first register DS1, the 0th register DS0 and m register DOn, m-1 register D0n-1 ... the clock signal input terminal of the 1st register D01 all connects the state machine clock signal output part of comparator 12; N register DSn, n-2 register DSn-2 ... the reset terminal CLR of the first register DS1, the 0th register DS0, set end SET and the m-1 register D0n-1 of n-1 register DSn-1 ... the reset terminal CLR of the 1st register D01 all is connected reset signal with the set end SET of m register D0n, this reset signal is imported by the outside, this signal begins state machine 13 is resetted before each selections function on automatically, reset finish after state machine 13 begin to rework; The identical index signal output connection the 0th of comparator 12 or the input of door 0R, the 0th or another input of door 0R connect the output Q of n register DSn, the 0th or the door 0R the output output switch control signal to control switch 19, control control switch 19 is connected with reference voltage signal or is connected with variable counter 17, and the work of output " 1 " expression state machine is finished; Control control switch 19 disconnects with reference voltage signal, is connected with variable counter 17.
The input/output signal of state machine 13 is as shown in table 1.
Table 1
The operation principle of state machine 13 is: for sake of convenience, registers group one is abbreviated as DS[n:0]; Registers group two is abbreviated as D0[n:1].Registers group DS[n:0] add/register of subtrahend DS[n:1 wherein as storage] output Q[n:1] default value be 2
N-2, promptly the initial value of Qn-1 is 1, and other initial value is 0, is the value that adds/subtract after relatively first, and the purpose that the 0th register DS0 is set is to realize the computing of last ± 1, avoids the situation of state machine output 0 to leak choosing.Registers group DS[n:0] adopt the serial annular to connect, move down one after each computing, n register DSn is output as 1 after carrying out n computing, the expression computing finishes, whether the output signal of n register DSn indicates the selections process of adaptive frequency calibration circuit to finish with the output signal that the identical index signal of comparator 12 outputs carries out obtaining behind the exclusive disjunction, and control control switch 19 is connected with reference voltage signal or is connected with variable counter 17.
Registers group D0[n:1] output Qout[n:1] the n position output of expression state machine, its output default value is 2
N-1, promptly the initial value of Qoutn is 1, other initial value is 0; The function of logic circuit unit is to realize adding deduct of carry-out bit.When relatively index signal is " 1 ", the sub-frequency clock signal frequency f of expression voltage controlled oscillator
VCOGreater than reference clock frequency f
REF, registers group D0[n:1] deduct registers group DS[n:1] value, if last computing then is registers group D0[n:1] deduct the value of the 0th register DS0; When relatively index signal is " 0 ", the sub-frequency clock signal frequency f of expression voltage controlled oscillator
VCOLess than reference clock frequency f
REF, then for registers group D0[n:1] add registers group DS[n:1] value, be if last computing then is registers group D0[n:1] add that the 0th adds the value of register DS0.
In the technical program, drafting state machine output is n position n 〉=2, and promptly voltage controlled oscillator adopts the structure of 2n section, and for fear of taking place to leak situation frequently, each frequency range will overlap to some extent.The every increase of control code " 1 ", under fixing voltage-controlled voltage condition, the output frequency of voltage controlled oscillator 18 increases △ f, therefore can cover 2
nThe frequency range of * △ f.After the work of adaptive frequency calibration circuit is finished, output a control signal to charge pump by phase frequency detector again, charge pump produces control voltage and by loop filter output control voltage voltage controlled oscillator 18 is controlled, adjust output frequency, can reduce the phase-locked time of whole frequency synthesizer like this.
Referring to Fig. 5, in the specific implementation, the work-based logic of state machine circuit of the present utility model mainly is the principle that adopts dichotomy, reduces and judges number of times.With n position control code is example, and maximum is 2
n-1, minimum value is 0.The initial value of the voltage controlled oscillator control signal of state machine output is 2
N-1, just the original frequency with the sub-frequency clock signal of voltage controlled oscillator is located at median.After comparator provided the state machine clock signal, state machine was adjusted the value of voltage controlled oscillator control signal according to the output of comparator.Initial value with control signal is 2
N-1Be example, adopt the principle of dichotomy, the adjustment number of control signal is δ n each time, and δ n is followed successively by 2
N-2, 2
N-3, 2
N-142
1, 2
0Concrete steps are:
The first step: initialization, establish N=2
N-1, δ n=2
N-2Wherein N is the control code value of the control signal of state machine output, and δ n is the adjustment number of control code value of the control signal of state machine output;
Second step: the signal that receives comparator 12 outputs;
The 3rd step: the sub-frequency clock signal frequency f of judging voltage controlled oscillator
VCOWhether equal the reference clock signal frequency f
REFIf, equate, entered for the 7th step; If unequal, judge and adjust whether number δ n is 2
0If adjusting number is 2
0, entered for the 6th step; If adjusting number δ n is not 2
0, entered for the 4th step;
The 4th step: the sub-frequency clock signal frequency f of judging voltage controlled oscillator
VCOWhether less than the reference clock signal frequency f
REF, if less than, adjust N=N+ δ n, entered for the 5th step; If f
VCOGreater than f
REF, adjust N=N-δ n, entered for the 5th step;
The 5th step: establish δ n=δ n/2, returned for second step;
The 6th step: the sub-frequency clock signal frequency f of judging voltage controlled oscillator
VCOWhether less than the reference clock signal frequency f
REF, if less than, adjust N=N+1, entered for the 7th step; If f
VCOGreater than f
REF, adjust N=N-1, entered for the 7th step;
The 7th step: calibration finishes, and makes the voltage-controlled voltage of voltage controlled oscillator 18 switch to the control voltage that loop filter 16 produces from normal voltage.
Adopt the adaptive frequency calibration circuit, even the inconsistent pressuring controlling oscillator frequency that causes of technology changes, 0～2
nAlways make voltage controlled oscillator satisfy required frequency requirement in-1 scope.And whole calibration operation is finished automatically by chip internal, need not external control, has both satisfied the consistency problem of pressuring controlling oscillator frequency, has simplified application scheme simultaneously.
Above embodiment of the present utility model is described, still, the scope that is not limited only to embodiment of the utility model protection.
Claims (6)
1. the frequency synthesizer of phase locking that has the adaptive frequency calibration circuit, comprise phase frequency detector (14), charge pump (15), loop filter (16), variable counter (17), voltage controlled oscillator (18), adaptive frequency calibration circuit (10) and control switch (19), it is characterized in that: adaptive frequency calibration circuit (10) comprises counter (11), comparator (12) and state machine (13);
Voltage controlled oscillator (18) receives reference voltage signal by control switch (19), produces frequency signal and outputs to variable counter (17);
Variable counter (17) is carried out frequency division with the signal of receiving and is handled the sub-frequency clock signal of back output voltage controlled oscillator to counter (11) and phase frequency detector (14);
Counter (11) receives the sub-frequency clock signal of reference clock signal and voltage controlled oscillator simultaneously and counts, and when one of them clock signal counting finished, counter (11) produced a pulse signal and outputs to comparator (12);
Comparator (12) compares after receiving the pulse signal of counter (11) output, produces index signal and produces the state machine clock signal simultaneously according to comparative result again and export to state machine (13) in the lump;
State machine (13) is subjected to the control of the state machine clock signal of comparator (12) output, and according to index signal, produces control signal and output to voltage controlled oscillator (18), to adjust the clock signal frequency of voltage controlled oscillator (18); When the sub-frequency clock signal frequency of voltage controlled oscillator equals the reference clock signal frequency, state machine (13) output switch control signal, control switch (19) is connected with the reference voltage signal disconnection and with loop filter (16), and voltage controlled oscillator (18) receives the control voltage signal of loop filter (16) output by control switch (19).
2. the frequency synthesizer of phase locking with adaptive frequency calibration circuit according to claim 1, described state machine (13) comprise logical circuit (33), registers group one (31) and registers group two (32); Registers group one (31) and registers group two (32) all are subjected to the control of the state machine clock signal of comparator (12) output; Registers group one (31) adds/register of subtrahend as storage; The data of logical circuit (33) receiving register group one (31) output, and receive the index signal of comparator (12) output simultaneously, carry out outputing to registers group two (32) after the logical operation, registers group two (32) produces control signal and outputs to voltage controlled oscillator (18), to adjust the clock signal frequency of voltage controlled oscillator (18).
3. the frequency synthesizer of phase locking with adaptive frequency calibration circuit according to claim 2, described registers group one (31) is by n register, n-1 register, n-2 register ... first register, the 0th register are formed; Registers group two (32) is by m register, m-1 register ... the 1st register is formed; Logical circuit by n logic circuit unit and the 0th or the door constitute, wherein: the natural number of n 〉=2; M=n; Each logic circuit unit include one with the door, one or and an XOR gate; N register, n-1 register, n-2 register ... first register, the 0th register adopt the serial annular to connect; N is connected the output Q of n-1 register with 1 input of door, n is connected the comparison index signal output of comparator with other 1 input of door; N is connected an input of n or door with the output of door, another input of n or door connects the output Q of n register, the output of n or door connects an input of n XOR gate, another input of n XOR gate connects the output Q of m register, and the output of n XOR gate connects the input D of m register; And the like, first is connected the output Q of the 0th register with 1 input of door, first with other 1 input be connected the comparison index signal output of comparator; First with the door output is connected first or an input, first or another input of door connect the output Q of first register, first or the output of door connect an input of first XOR gate, another input of first XOR gate connects the output Q of the 1st register, and the output of first XOR gate connects the input D of the 1st register; M register, m-1 register ... the output Q of the 1st register exports n position control signal altogether to voltage controlled oscillator (18); N register, n-1 register, n-2 register ... the clock signal input terminal of first register, the 0th register and m register, m-1 register ... the clock signal input terminal of the 1st register all connects the state machine clock signal output part of comparator (12); The n register, the n-2 register ... first register, the reset terminal CLR of the 0th register, the set end SET and the m-1 register of n-1 register ... the reset terminal CLR of the 1st register and the set end SET of m register all are connected reset signal, this reset signal is imported by the outside, the identical index signal output connection the 0th of comparator (12) or an input of door, the 0th or another input of door connect the output Q of n register, the 0th or the output output switch control signal of door to control switch (19), control control switch (19) and be connected with reference voltage signal or be connected with variable counter (17).
4. frequency synthesizer of phase locking segmented voltage controlled oscillator adaptive frequency calibration circuit comprises counter (11), comparator (12) and state machine (13), it is characterized in that:
The sub-frequency clock signal of reference clock signal and voltage controlled oscillator enter counter (11) is simultaneously counted, and when one of them clock signal counting finished, counter (11) produced a pulse signal and outputs to comparator (12);
Comparator (12) compares after receiving the pulse signal of counter (11) output, produces index signal and produces the state machine clock signal simultaneously according to comparative result again and export to state machine (13) in the lump;
State machine (13) is subjected to the control of the state machine clock signal of comparator (12) output, and according to index signal, produces control signal and output to voltage controlled oscillator (18), to adjust the clock signal frequency of voltage controlled oscillator (18).
5. frequency synthesizer of phase locking segmented voltage controlled oscillator adaptive frequency calibration circuit according to claim 4, it is characterized in that: described state machine (13) comprises logical circuit (33), registers group one (31) and registers group two (32); Registers group one (31) and registers group two (32) all are subjected to the control of the state machine clock signal of comparator (12) output; Registers group one (31) adds/register of subtrahend as storage; The data of logical circuit (33) receiving register group one (31) output, and receive the index signal of comparator (12) output simultaneously, carry out outputing to registers group two (32) after the logical operation, registers group two (32) produces control signal and outputs to voltage controlled oscillator (18), to adjust the clock signal frequency of voltage controlled oscillator (18).
6. frequency synthesizer of phase locking segmented voltage controlled oscillator adaptive frequency calibration circuit according to claim 5 is characterized in that: described registers group one (31) is by n register, n-1 register, n-2 register ... first register, the 0th register are formed; Described registers group two (32) is by m register, m-1 register ... the 1st register is formed; Logical circuit by n logic circuit unit and the 0th or the door constitute, wherein: the natural number of n 〉=2; M=n; Each logic circuit unit include one with the door, one or and an XOR gate; N register, n-1 register, n-2 register ... first register, the 0th register adopt the serial annular to connect; N is connected the output Q of n-1 register with 1 input of door, n is connected the comparison index signal output of comparator with other 1 input of door; N is connected an input of n or door with the output of door, another input of n or door connects the output Q of n register, the output of n or door connects an input of n XOR gate, another input of n XOR gate connects the output Q of m register, and the output of n XOR gate connects the input D of m register; And the like, first is connected the output Q of the 0th register with 1 input of door, first with other 1 input be connected the comparison index signal output of comparator; First with the door output is connected first or an input, first or another input of door connect the output Q of first register, first or the output of door connect an input of first XOR gate, another input of first XOR gate connects the output Q of the 1st register, and the output of first XOR gate connects the input D of the 1st register; M register, m-1 register ... the output Q of the 1st register exports n position control signal altogether to voltage controlled oscillator; N register, n-1 register, n-2 register ... the clock signal input terminal of first register, the 0th register and m register, m-1 register ... the clock signal input terminal of the 1st register all connects the state machine clock signal output part of comparator (12); The n register, the n-2 register ... first register, the reset terminal CLR of the 0th register, the set end SET and the m-1 register of n-1 register ... the reset terminal CLR of the 1st register and the set end SET of m register all are connected reset signal, this reset signal is imported by the outside, the identical index signal output connection the 0th of comparator (12) or an input of door, the 0th or another input of door connect the output Q of n register, the 0th or the output output switch control signal of door to control switch (19), control control switch (19) and be connected with reference voltage signal or be connected with variable counter (17).
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| CN 201220745723 CN203104411U (en) | 2012-12-28 | 2012-12-28 | A phase-locking frequency synthesizer and an adaptive frequency calibrating circuit |
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| CN 201220745723 CN203104411U (en) | 2012-12-28 | 2012-12-28 | A phase-locking frequency synthesizer and an adaptive frequency calibrating circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103095295A (en) * | 2012-12-28 | 2013-05-08 | 重庆西南集成电路设计有限责任公司 | Phase-locking frequency synthesizer, self-adaptation frequency calibration circuit and calibration method |
| CN109921790A (en) * | 2019-01-30 | 2019-06-21 | 芯原微电子(上海)股份有限公司 | Fast start circuit, adaptive phase locked loop and quick start method |
-
2012
- 2012-12-28 CN CN 201220745723 patent/CN203104411U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103095295A (en) * | 2012-12-28 | 2013-05-08 | 重庆西南集成电路设计有限责任公司 | Phase-locking frequency synthesizer, self-adaptation frequency calibration circuit and calibration method |
| CN103095295B (en) * | 2012-12-28 | 2015-09-23 | 重庆西南集成电路设计有限责任公司 | Frequency synthesizer of phase locking and adaptive frequency calibration circuit and calibration steps |
| CN109921790A (en) * | 2019-01-30 | 2019-06-21 | 芯原微电子(上海)股份有限公司 | Fast start circuit, adaptive phase locked loop and quick start method |
| CN109921790B (en) * | 2019-01-30 | 2023-04-28 | 芯原微电子(上海)股份有限公司 | Quick start circuit, self-adaptive phase-locked loop and quick start method |
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