CN202854331U - Radar echo real-time simulator based on FPGA - Google Patents
Radar echo real-time simulator based on FPGA Download PDFInfo
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- CN202854331U CN202854331U CN 201220453013 CN201220453013U CN202854331U CN 202854331 U CN202854331 U CN 202854331U CN 201220453013 CN201220453013 CN 201220453013 CN 201220453013 U CN201220453013 U CN 201220453013U CN 202854331 U CN202854331 U CN 202854331U
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Abstract
The utility model discloses a radar echo real-time simulator based on FPGA. The radar echo real-time simulator comprises an FPGA signal processor, an A/D converter, a D/A converter, a first down-conversion circuit, a second down-conversion circuit and a host computer, wherein a signal input terminal of the first down-conversion circuit is used for the input of a radio frequency signal, a signal output terminal of the first down-conversion circuit is connected with a signal input terminal of the A/D converter and a signal input terminal of the second down-conversion circuit, a signal output terminal of the A/D converter and a signal output terminal of the host computer are connected with a signal input terminal of the FPGA signal processer, a signal output terminal of the FPGA signal processer is connected with a signal input terminal of the D/A converter, a signal output terminal of the D/A converter is connected with the signal input terminal of the second down-conversion circuit, and a signal output terminal of the second down-conversion circuit is used for outputting a radio frequency echo signal. The utility model provides a general radar echo signal real-time simulation system based on FPGA, and the system has the advantages of low cost, high flexibility, strong real-time capability, high versatility and capability of adapting to conditions of complex and changeable parameters.
Description
Technical field
The utility model relates to a kind of simulator, relates in particular to a kind of radar return real time simulator based on FPGA.
Background technology
Simulator can be divided into three kinds of implementations such as software simulation, hardware simulation and soft or hard combination usually.Software simulation has the advantages such as cost is low, dirigibility is strong, but real-time is poor, generally can not be directly used in real-time debug and the test of radar system.The soft or hard combination take high-performance embedded processor as arithmetic element, have good real-time, but versatility is poor take multi-purpose computer as the master control platform, can not satisfy parameter situation complicated and changeable.
Summary of the invention
The purpose of this utility model provides a kind of radar return real time simulator based on FPGA with regard to being in order to address the above problem.
The utility model is achieved through the following technical solutions above-mentioned purpose:
The utility model comprises the FPGA signal processor, A/D converter, D/A converter, the first lower frequency changer circuit, the second lower frequency changer circuit and host computer, the signal input part of described the first lower frequency changer circuit is used for the input radio frequency signal, the signal output part of described the first lower frequency changer circuit respectively with the signal input part of described A/D converter be connected the signal input part of the second lower frequency changer circuit and be connected, the signal output part of described A/D converter be connected the signal output part of host computer and be connected with the signal input part of described FPGA signal processor respectively, the signal output part of described FPGA signal processor is connected with the signal input part of described D/A converter, the signal output part of described D/A converter is connected with the signal input part of described the second lower frequency changer circuit, and the signal output part of described the second lower frequency changer circuit is used for the output rf echo signal.
Particularly, described host computer is PC.
The beneficial effects of the utility model are:
The utility model provides a kind of general radar echo signal Real-time Simulation System by FPGA for core.The utlity model has that cost is low, dirigibility is strong, real-time, highly versatile and can satisfy the advantage of parameter situation complicated and changeable.
Description of drawings
Fig. 1 is the structured flowchart of the radar return real time simulator based on FPGA described in the utility model.
Embodiment
The utility model is described in further detail below in conjunction with accompanying drawing:
As shown in Figure 1: the utility model comprises the FPGA signal processor, A/D converter, D/A converter, the first lower frequency changer circuit, the second lower frequency changer circuit and host computer, the signal input part of described the first lower frequency changer circuit is used for the input radio frequency signal, the signal output part of described the first lower frequency changer circuit respectively with the signal input part of described A/D converter be connected the signal input part of the second lower frequency changer circuit and be connected, the signal output part of described A/D converter be connected the signal output part of host computer and be connected with the signal input part of described FPGA signal processor respectively, the signal output part of described FPGA signal processor is connected with the signal input part of described D/A converter, the signal output part of described D/A converter is connected with the signal input part of described the second lower frequency changer circuit, the signal output part of described the second lower frequency changer circuit is used for the output rf echo signal, and described host computer is PC.
The utility model provides a kind of general radar echo signal Real-time Simulation System by FPGA for core.The utlity model has have that cost is low, dirigibility is strong, real-time, highly versatile and can satisfy the advantage of parameter situation complicated and changeable.
Claims (2)
1. radar return real time simulator based on FPGA, it is characterized in that: comprise the FPGA signal processor, A/D converter, D/A converter, the first lower frequency changer circuit, the second lower frequency changer circuit and host computer, the signal input part of described the first lower frequency changer circuit is used for the input radio frequency signal, the signal output part of described the first lower frequency changer circuit respectively with the signal input part of described A/D converter be connected the signal input part of the second lower frequency changer circuit and be connected, the signal output part of described A/D converter be connected the signal output part of host computer and be connected with the signal input part of described FPGA signal processor respectively, the signal output part of described FPGA signal processor is connected with the signal input part of described D/A converter, the signal output part of described D/A converter is connected with the signal input part of described the second lower frequency changer circuit, and the signal output part of described the second lower frequency changer circuit is used for the output rf echo signal.
2. the radar return real time simulator based on FPGA according to claim 1, it is characterized in that: described host computer is PC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220453013 CN202854331U (en) | 2012-09-07 | 2012-09-07 | Radar echo real-time simulator based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220453013 CN202854331U (en) | 2012-09-07 | 2012-09-07 | Radar echo real-time simulator based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202854331U true CN202854331U (en) | 2013-04-03 |
Family
ID=47985514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220453013 Expired - Fee Related CN202854331U (en) | 2012-09-07 | 2012-09-07 | Radar echo real-time simulator based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202854331U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111007469A (en) * | 2019-12-25 | 2020-04-14 | 上海铭剑电子科技有限公司 | Receiver of radar simulator |
-
2012
- 2012-09-07 CN CN 201220453013 patent/CN202854331U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111007469A (en) * | 2019-12-25 | 2020-04-14 | 上海铭剑电子科技有限公司 | Receiver of radar simulator |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130403 Termination date: 20130907 |