CN202121570U - High-speed large-scale digital signal processing chip - Google Patents
High-speed large-scale digital signal processing chip Download PDFInfo
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- CN202121570U CN202121570U CN2011202094679U CN201120209467U CN202121570U CN 202121570 U CN202121570 U CN 202121570U CN 2011202094679 U CN2011202094679 U CN 2011202094679U CN 201120209467 U CN201120209467 U CN 201120209467U CN 202121570 U CN202121570 U CN 202121570U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
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Abstract
The utility model discloses a high-speed large-scale digital signal processing chip, which is characterized by comprising an AD interface module used for carrying out DDR sampling of 1Gbps data, a parameter configuration SPI module used for carrying out chip parameter configuration, a signal detection module used for detecting frequency domains of signals, a parameter detection module used for carrying out time domain parameter measuring, a phase measuring module and a report SPI module used for reporting results, wherein an input end of the signal detection module is respectively connected with an output end of the AD interface module and an output end of the parameter configuration SPI module, an output end of the signal detection module is respectively connected with an input end of the parameter detection module and an input end of the phase measuring module, and an input end of the report SPI module is respectively connected with an output end of the parameter detection module and an output end of the phase measuring module. The high-speed large-scale digital signal processing chip is small, ultra low in power consumption, rapid in processing speed, instant in responding, highly integrated in signal processing function and low in cost.
Description
Technical field
The utility model relates to the high-speed digital signal processing technology field, is specifically related to a kind of high speed large scale digital signal processing chip that is applied in the fields such as radar, electronic warfare.
Background technology
Along with radar; The develop rapidly of electronic warfare art; Actual application demand is had higher requirement to present conventional digital signal handling equipment, particularly integrated in miniaturization, low-power consumption, real time response speed, systemic-function height, cost control, anti-spoke aspect such as make an uproar.At present traditional based on FPGA, the digital signal processing appts that DSP association handles all can not satisfy actual application demand above aspect several, and has a long way to go with user's actual requirement.
For solving above-mentioned defective of the prior art, the utility model provides a kind of new solution.
Summary of the invention
The utility model technical problem to be solved is: the deficiency that how to be directed to existing digital signal processing appts; A kind of high speed large scale digital signal processing chip is provided, advantages such as this high speed large scale digital signal processing chip has that miniaturization, super low-power consumption, processing speed are fast, real-time response, signal processing function height are integrated, low cost.
For reaching the foregoing invention purpose; The technical scheme that the utility model adopted is: a kind of high speed large scale digital signal processing chip is provided, it is characterized in that: comprise the DDR sampling that is used to carry out the 1Gbps data the AD interface module, be used to carry out the chip parameter configuration parameter configuration SPI module, be used to carry out signal detection module that signal frequency-domain detects, be used to carry out parameter detection module that time domain parameter measures, survey phase module and be used for that the result reports report the SPI module; The input of said signal detection module is connected with the output of AD interface module with parameter configuration SPI module respectively, and the output of signal detection module is connected with the input of surveying phase module with parameter detection module respectively; The input of the said SPI of reporting module is connected with the output of surveying phase module with parameter detection module respectively.
In sum, this practical high speed large scale digital signal processing chip that provides has following advantage than existing device:
1, adopts low power consumption design method, make chip power-consumption have only 10% of original digital device;
The digital processing function of 4 FPGA before 2, single-chip is accomplished, the systemic-function height is integrated;
3, chip has been realized miniaturization, and chip adopts 17mm*17mm BGA encapsulation, and volume ratio is original to be reduced greatly (monolithic FPGA 35mm*35mm);
4, processing speed has promoted 2 times, can the real-time response system command;
5, be suitable for mass production, production cost reduces greatly, is applicable in all kinds of digital information processing systems such as radar, electronic countermeasures.
Description of drawings
Fig. 1 is the modular structure figure of high speed large scale digital signal processing chip.
Embodiment
Below in conjunction with accompanying drawing the utility model is further described.
As shown in Figure 1, this high speed large scale digital signal processing chip comprise the DDR sampling that is used to carry out the 1Gbps data the AD interface module, be used to carry out the chip parameter configuration parameter configuration SPI module, be used to carry out signal detection module that signal frequency-domain detects, be used to carry out parameter detection module that time domain parameter measures, survey phase module and be used for that the result reports report the SPI module; The input of said signal detection module is connected with the output of AD interface module with parameter configuration SPI module respectively, and the output of signal detection module is connected with the input of surveying phase module with parameter detection module respectively; The input of the said SPI of reporting module is connected with the output of surveying phase module with parameter detection module respectively.
Adopt this digital signal processing chip can replace 4 V5 fpga chips in original design; A chip can be accomplished all signal processing functions of original device; Reduced the PCB area occupied greatly, it is original 10% that power consumption has only, and speed is original 2 times; And the application technology index is more excellent, and cost is lower after the volume production.
The utility model is above through the embodiment by the accompanying drawing illustrated embodiment, is the further explain that the foregoing of the utility model is made, but should this be interpreted as that the scope of the theme that the utility model is above-mentioned only limits to described instance.
Claims (1)
1. high speed large scale digital signal processing chip is characterized in that: comprise the DDR sampling that is used to carry out the 1Gbps data the AD interface module, be used to carry out the chip parameter configuration parameter configuration SPI module, be used to carry out signal detection module that signal frequency-domain detects, be used to carry out parameter detection module that time domain parameter measures, survey phase module and be used for that the result reports report the SPI module; The input of said signal detection module is connected with the output of AD interface module with parameter configuration SPI module respectively, and the output of signal detection module is connected with the input of surveying phase module with parameter detection module respectively; The input of the said SPI of reporting module is connected with the output of surveying phase module with parameter detection module respectively.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN2011202094679U CN202121570U (en) | 2011-06-21 | 2011-06-21 | High-speed large-scale digital signal processing chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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CN2011202094679U CN202121570U (en) | 2011-06-21 | 2011-06-21 | High-speed large-scale digital signal processing chip |
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CN202121570U true CN202121570U (en) | 2012-01-18 |
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CN2011202094679U Expired - Lifetime CN202121570U (en) | 2011-06-21 | 2011-06-21 | High-speed large-scale digital signal processing chip |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102931842A (en) * | 2012-10-12 | 2013-02-13 | 华为技术有限公司 | Chip dynamic voltage regulating circuit and terminal equipment |
-
2011
- 2011-06-21 CN CN2011202094679U patent/CN202121570U/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102931842A (en) * | 2012-10-12 | 2013-02-13 | 华为技术有限公司 | Chip dynamic voltage regulating circuit and terminal equipment |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CX01 | Expiry of patent term |
Granted publication date: 20120118 |
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CX01 | Expiry of patent term |