CN203720355U

CN203720355U - FPGA and ARM architecture-based satellite navigation interference-resisting circuit

Info

Publication number: CN203720355U
Application number: CN201320847857.8U
Authority: CN
Inventors: 齐彩利; 王朝勋; 柴彩娟; 刘魏成; 张刚; 于大蔚; 张敬明; 陈大恺
Original assignee: Tianjin 764 Communication and Navigation Technology Corp
Current assignee: Tianjin 764 Communication and Navigation Technology Corp
Priority date: 2013-12-22
Filing date: 2013-12-22
Publication date: 2014-07-16
Anticipated expiration: 2023-12-22

Abstract

The utility model relates to an FPGA and ARM architecture-based satellite navigation interference-resisting circuit. A DA converter, a clock power divider, and four AD converters are connected with an FPGA. The FPGA is connected with an RS422 interface circuit, an RS232 interface circuit, and a reset circuit through an ARM. An SDRAM and a NOR FLASH are connected with the FPGA and the ARM. An NAND FLASH is connected with the ARM. The clock power divider is connected with the four AD converters. The power circuit supplies 3.3 V, 1.8 V, and 1.2 V power voltages to the whole circuit. The satellite navigation interference-resisting circuit is characterized in that the circuit is combined with other radio frequency modules of a satellite navigation interference-resisting antenna to resist suppressive interferences from three directions. The satellite navigation interference-resisting circuit is also characterized by small size, low power consumption, high universality, and the like, and can satisfy the requirements of multiple projects. The signal processing part adopts a scheme of employing the single FPGA and the single ARM, thereby saving the resources, reducing the cost, and decreasing the pressure of circuit board layout. The mainstream FPGA and ARM chips on the market are selected as the processors so that the project requirements are satisfied while the development difficulty level is lowered.

Description

A kind of satellite navigation anti-jamming circuit based on FPGA, ARM framework

Technical field

The utility model relates to a kind of satellite navigation anti-jamming circuit based on FPGA, ARM framework, is the digital anti-jamming circuit of the Big Dipper B3 frequency based on FPGA, ARM hardware platform, for a kind of satellite navigation anti-interference antenna.

Background technology

" No. two, the Big Dipper " is the satellite navigation system that China develops voluntarily, can provide high-precision navigation, location and time service service to user.The satellite-signal of Big Dipper B3 frequency is more widely used in military domain.But because satellite-signal power is very faint, be very easily subject to various potential having a mind to or disturb unintentionally, thereby affect the accuracy of its navigation, location and time service, so satellite navigation system Anti-Jamming Technique becomes the essential problem solving.

Summary of the invention

In view of present situation and the development need of prior art, the utility model provides a kind of satellite navigation anti-jamming circuit based on FPGA, ARM framework.

The utility model for achieving the above object, the technical scheme of taking is: a kind of based on FPGA, the satellite navigation anti-jamming circuit of ARM framework, it is characterized in that: comprise AD converter, DA converter, clock power splitter, FPGA, NORFLASH, SDRAM, NANDFLASH, ARM, RS422 interface circuit, RS232 interface circuit, reset circuit, power circuit, described DA converter, clock power splitter is connected with FPGA respectively with four AD converter, described FPGA by ARM respectively with RS422 interface circuit, RS232 interface circuit, reset circuit connects, SDRAM and NORFLASH respectively with FPGA, ARM connects, described NANDFLASH is connected with ARM, described clock power splitter is connected with four AD converter respectively, described power circuit provides 3.3V for whole circuit, 1.8V, tri-kinds of supply voltages of 1.2V.

Feature of the present utility model is: together with the utility model combines with other radio-frequency modules of a kind of satellite navigation anti-interference antenna, resist from the briquettability of three directions and disturb.Have volume little, the feature such as low in energy consumption, highly versatile, can adapt to the demand of a plurality of projects.Signal processing is taked the scheme of single FPGA and single ARM, has not only saved resource, has reduced cost, and has reduced the pressure of circuit board fabric swatch, for the structural design of satellite navigation anti-interference antenna has reserved larger space.Processor selection is FPGA and the ARM chip of main flow on the market, has met project demands, has reduced again development difficulty.

Accompanying drawing explanation

Fig. 1 is that circuit of the present utility model connects block diagram.

Embodiment

As shown in Figure 1, a kind of based on FPGA, the satellite navigation anti-jamming circuit of ARM framework, comprise AD converter, DA converter, clock power splitter, FPGA, NORFLASH, SDRAM, NANDFLASH, ARM, RS422 interface circuit, RS232 interface circuit, reset circuit, power circuit, DA converter, clock power splitter is connected with FPGA respectively with four AD converter, FPGA by ARM respectively with RS422 interface circuit, RS232 interface circuit, reset circuit connects, SDRAM and NORFLASH respectively with FPGA, ARM connects, described NANDFLASH is connected with ARM, described clock power splitter is connected with four AD converter respectively, power circuit provides 3.3V for whole circuit, 1.8V, tri-kinds of supply voltages of 1.2V.

Principle of work: the anti-interference unit of this satellite navigation receives the intermediate-freuqncy signal of 46.52MHz, adopts FPGA and ARM framework, realizes the anti-interference process to Big Dipper satellite signal, then by DA, convert the data after processing to analog signal output.Together with can combining with other radio-frequency modules of a kind of satellite navigation anti-interference antenna, resist from the briquettability of three directions and disturb.

AD converter is selected the AD9268BCPZ-125 of two 16, and simulating signal is inputted by outside, and 16 position digital signals of output are given FPGA and processed;

FPGA selects the chip that the Spartan-6 of Xilinx company serial model No. is XC6SLX150-3FGG484I.

Anti-interference algorithm is mainly realized by FPGA.

ARM selects the chip that NXP Semiconductors company model is LPC3250FET296.It is connected with NAND FLASH, level transferring chip, reset circuit etc.The functions such as ARM mainly realizes that parameter arranges;

DA converter is selected the chip that AD company model is AD9744ACP, exports after the digital signal through anti-interference algorithm process is converted to simulating signal.

Claims

1. one kind based on FPGA, the satellite navigation anti-jamming circuit of ARM framework, it is characterized in that: comprise AD converter, DA converter, clock power splitter, FPGA, NORFLASH, SDRAM, NANDFLASH, ARM, RS422 interface circuit, RS232 interface circuit, reset circuit, power circuit, described DA converter, clock power splitter is connected with FPGA respectively with four AD converter, described FPGA by ARM respectively with RS422 interface circuit, RS232 interface circuit, reset circuit connects, SDRAM and NORFLASH respectively with FPGA, ARM connects, described NANDFLASH is connected with ARM, described clock power splitter is connected with four AD converter respectively, described power circuit provides 3.3V for whole circuit, 1.8V, tri-kinds of supply voltages of 1.2V.