CN202815478U - Low side driving circuit - Google Patents
Low side driving circuit Download PDFInfo
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- CN202815478U CN202815478U CN201220429673.5U CN201220429673U CN202815478U CN 202815478 U CN202815478 U CN 202815478U CN 201220429673 U CN201220429673 U CN 201220429673U CN 202815478 U CN202815478 U CN 202815478U
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Abstract
A low side driving circuit comprises an electrical level conversion unit, an amplifying unit, a driving unit and a feedback unit, wherein the electrical level conversion unit, the amplifying unit and the driving unit are electrically connected in turn, the feedback unit is respectively connected with the electrical level conversion unit and the driving unit, the driving unit is also connected with one end of a load, the other end of the load is connected with a first power supply, the electrical level conversion unit receives and performs the logic operation of a control signal sent from a control unit and a feedback signal fed from the feedback unit, and then outputs an electrical level signal, the electrical level signal is amplified by the amplifying unit, and when short circuit occurs in the driving unit and the first power supply, the driving unit is made to stop driving the load to the work. The driving unit of the low side driving circuit does not need the expensive intelligent power driving chip with the short circuit projection function on the first power supply and when the low side driving circuit is directly shorted with the first power supply, the driving unit is timely and effectively switched off, therefore the driving unit is prevented from being burnt out.
Description
Technical field
The utility model relates to low limit and drives the field, is specifically related to a kind of low limit driving circuit.
Background technology
At present, be used for driving the low limit driving circuit of load (such as the ignition coil on the vehicle, fuel injector and various valve, relay etc.), the driver element of low limit driving circuit links to each other with load, high edge joint first power supply of load, because the situation with the direct short circuit of flash of load unavoidably can appear in driver element, thus may so that driver element burnt.
In order to solve the existing above-mentioned technical matters of above-mentioned low limit driving circuit; low limit driving circuit adopts intelligent power to drive chip more; this intelligent power drives chip self to have the power source short-circuit protection function; but because it is expensive and procurement cycle is long; be difficult to satisfy batch production and low-cost control requirement; and; because this intelligent power drives the integrated fault diagnosis circuit of chip internal; part of module driving chip package is large and radiating effect is relatively poor; therefore need take into full account the PCB layout to satisfy the requirement of thermal diffusivity in development, greatly prolong the R﹠D cycle.
The utility model content
The above-mentioned technical matters that the utility model exists for solving existing low limit driving circuit provides a kind of low limit driving circuit.
The technical solution of the utility model is:
A kind of low limit driving circuit, comprise level conversion unit, amplifying unit, driver element and feedback unit, described level conversion unit, amplifying unit and driver element successively electricity link to each other, described feedback unit links to each other with driver element with level conversion unit respectively, described driver element also links to each other with an end of load, another termination first power supply of described load, wherein
The control signal that described level conversion unit receives and control module is sent and feedback unit feedback of feedback signal carry out outputs level signals after the logical operation, and this level signal makes driver element stop to drive loaded work piece when driver element and the first power supply short circuit after amplifying unit amplifies.
Further, described driver element comprises having first utmost point, the first switching tube of second utmost point and the 3rd utmost point, described feedback unit comprises the first resistance, the second resistance and diode, first utmost point of described the first switching tube links to each other with amplifying unit, the second utmost point ground connection of the first switching tube, the 3rd utmost point of the first switching tube links to each other with the negative electrode of diode and an end of load respectively, the anode of diode links to each other with an end of the first resistance and an end of the second resistance respectively, the other end of described the first resistance all links to each other with the first power supply with the other end of load, and the other end of described the second resistance links to each other with level conversion unit.
Further, described amplifying unit comprises the second switch pipe, the 3rd resistance and the 12 resistance, described level conversion unit comprises the first XOR gate, Sheffer stroke gate, the 4th resistance and the first electric capacity, described second switch pipe has first utmost point, second utmost point and the 3rd utmost point, the control signal that the first input end reception control unit of described the first XOR gate sends, the second input end of the first XOR gate links to each other with the other end of the second resistance, the output terminal of the first XOR gate links to each other with the first input end of Sheffer stroke gate through the 4th resistance, the control signal that the second input end reception control unit of described Sheffer stroke gate sends, the first input end of Sheffer stroke gate is also by the first capacity earth, the output terminal of described Sheffer stroke gate extremely links to each other with first of second switch pipe by the 12 resistance, the second utmost point ground connection of second switch pipe, the 3rd utmost point of second switch pipe extremely links to each other with first of an end of the 3rd resistance and the first switching tube respectively, and the other end of described the 3rd resistance links to each other with second source.
Further, described level conversion unit also comprises the 5th resistance, and the second input end of described Sheffer stroke gate is by the 5th resistance eutral grounding.
Further, described driver element also comprises the 6th resistance and the second electric capacity, and described the 6th resistance is connected between first utmost point of the 3rd utmost point of second switch pipe and the first switching tube, and described the second electric capacity is connected between first utmost point and ground of the first switching tube.
Further, described feedback unit also comprises the 7th resistance and the 3rd electric capacity, and described the 7th resistance and the 3rd electric capacity are attempted by between second input end and ground of the first XOR gate.
Further, described amplifying unit is for having positive input, the operational amplifier of inverting input and output terminal, described level conversion unit comprises the second XOR gate, with door, the 8th resistance and the 4th electric capacity, the control signal that the first input end reception control unit of described the second XOR gate sends, the second input end of the second XOR gate links to each other with the other end of the second resistance, the output terminal of the second XOR gate through the 8th resistance with link to each other with the first input end of door, the control signal that the second input end reception control unit described and door sends, also pass through the 4th capacity earth with the first input end of door, describedly link to each other with the positive input of operational amplifier with the output terminal of door, the inverting input of operational amplifier links to each other with the output terminal of operational amplifier, and the output terminal of described operational amplifier also extremely links to each other with first of the first switching tube.
Further, described level conversion unit also comprises the 9th resistance, and described the second input end with door passes through the 9th resistance eutral grounding.
Further, described driver element also comprises the tenth resistance and the 5th electric capacity, and described the tenth resistance is connected between first utmost point of the output terminal of operational amplifier and the first switching tube, and described the 5th electric capacity is connected between first utmost point and ground of the first switching tube.
Further, described feedback unit also comprises the 11 resistance and the 6th electric capacity, and described the 11 resistance and the 6th electric capacity are attempted by between second input end and ground of the second XOR gate.
The low limit driving circuit of sampling technique scheme; the control signal that described level conversion unit receives and control module is sent and feedback unit feedback of feedback signal carry out outputs level signals after the logical operation; this level signal makes driver element stop to drive loaded work piece when driver element and the first power supply short circuit after amplifying unit amplifies; so that the driver element of low limit of the present utility model driving circuit is not needing to adopt the intelligent power that self has the costliness of the first power source short-circuit protection function to drive under the prerequisite of chip; can guarantee that also driver element turn-offs driver element timely and effectively when situation with the direct short circuit of the first power supply occurring; thereby avoid driver element to be burned; therefore; low limit of the present utility model driver element can adopt circuit simple in structure or chip to realize; namely encapsulate little; good heat dissipation effect; effectively reduce PCB designer's workload, shortened the R﹠D cycle.
Description of drawings
The structural drawing of the embodiment that Fig. 1 provides for the low limit of the utility model driving circuit.
The physical circuit figure of the embodiment that Fig. 2 provides for the low limit of the utility model driving circuit.
The physical circuit figure of another embodiment that Fig. 3 provides for the low limit of the utility model driving circuit.
Embodiment
Clearer for technical matters, technical scheme and beneficial effect that the utility model is solved, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the utility model, and be not used in restriction the utility model.
The low limit driving circuit of an embodiment as shown in Figure 1, comprise level conversion unit 2, amplifying unit 3, driver element 4 and feedback unit 6, described level conversion unit 2, amplifying unit 3 and driver element 4 successively electricity link to each other, described feedback unit 6 links to each other with driver element 3 with level conversion unit 2 respectively, described driver element 3 also links to each other with an end of load 5, another termination first power supply of described load 5, wherein
The control signal that described level conversion unit 2 receives and control module 1 is sent and feedback unit 6 feedback of feedback signals carry out outputs level signals after the logical operation, and this level signal makes driver element 4 stop to drive load 5 after amplifying unit 3 amplifies when driver element 4 and the first power supply short circuit and works.
Be understandable that, under normal circumstances, the control signal that described level conversion unit 2 receives and control module 1 is sent and feedback unit 6 feedback of feedback signals carry out outputs level signals after the logical operation, whether this level signal drives load 5 by driver element 4 and works after amplifying unit 3 amplifies, its specific works principle can referring to following principle of work embodiment illustrated in fig. 2, not done introduction at this.
In the implementation, described driver element 4 comprises having first utmost point, the first switching tube of second utmost point and the 3rd utmost point, described feedback unit 6 comprises the first resistance, the second resistance and diode, first utmost point of described the first switching tube links to each other with amplifying unit 3, the second utmost point ground connection of the first switching tube, the 3rd utmost point of the first switching tube links to each other with the negative electrode of diode and an end of load 5 respectively, the anode of diode links to each other with an end of the first resistance and an end of the second resistance respectively, the other end of the other end of described the first resistance and load 5 all links to each other with the first power supply, and the other end of described the second resistance links to each other with level conversion unit 2.
As a kind of embodiment of the present utility model, described amplifying unit 3 comprises the second switch pipe, the 3rd resistance and the 12 resistance, described level conversion unit 2 comprises the first XOR gate, Sheffer stroke gate, the 4th resistance and the first electric capacity, described second switch pipe has first utmost point, second utmost point and the 3rd utmost point, the control signal that the first input end reception control unit 1 of described the first XOR gate sends, the second input end of the first XOR gate receives the feedback signal of feedback unit 6 outputs, the output terminal of the first XOR gate links to each other with the first input end of Sheffer stroke gate through the 4th resistance, the control signal that the second input end reception control unit 1 of described Sheffer stroke gate sends, the first input end of Sheffer stroke gate is also by the first capacity earth, the output terminal of described Sheffer stroke gate extremely links to each other with first of second switch pipe by the 12 resistance, the second utmost point ground connection of second switch pipe, the 3rd utmost point of second switch pipe links to each other with an end and the driver element 4 of the 3rd resistance respectively, and the other end of described the 3rd resistance links to each other with second source.
As another kind of embodiment of the present utility model, described amplifying unit 3 can also be for having positive input, the operational amplifier of inverting input and output terminal, described level conversion unit 2 can also comprise the second XOR gate, with door, the 8th resistance and the 4th electric capacity, the control signal that the first input end reception control unit 1 of described the second XOR gate sends, the second input end of the second XOR gate receives the feedback signal of feedback unit 6 outputs, the output terminal of the second XOR gate through the 8th resistance with link to each other with the first input end of door, the control signal that the second input end reception control unit 1 described and door sends, also pass through the 4th capacity earth with the first input end of door, describedly link to each other with the positive input of operational amplifier with the output terminal of door, the inverting input of operational amplifier links to each other with the output terminal of operational amplifier, and the output terminal of described operational amplifier also links to each other with driver element 4.
The physical circuit figure of the embodiment that low limit driving circuit as shown in Figure 2 provides, low limit driving circuit comprises level conversion unit 2, amplifying unit 3, driver element 4 and feedback unit 6, described driver element 4 comprises having grid, the first switching tube Q1 of emitter and collector, described amplifying unit 3 comprises second switch pipe Q2, the 3rd resistance R 3 and the 12 resistance R 12, described level conversion unit 2 comprises the first XOR gate U11, Sheffer stroke gate U12, the 4th resistance R 4 and the first capacitor C 1, described feedback unit 6 comprises the first resistance R 1, the second resistance R 2 and diode D1, described second switch pipe Q2 has base stage, emitter and collector, the grounded emitter GND of described the first switching tube Q1, the collector of the first switching tube Q1 links to each other with the negative electrode of diode D1 and an end of load 5 respectively, the anode of diode D1 links to each other with an end of the first resistance R 1 and an end of the second resistance R 2 respectively, the other end of the other end of described the first resistance R 1 and load 5 all links to each other with the first power vd D1, the control signal that the first input end reception control unit 1 of described the first XOR gate U11 sends, the second input end of the first XOR gate U11 links to each other with the other end of the second resistance R 2, the output terminal of the first XOR gate U11 links to each other with the first input end of Sheffer stroke gate U12 through the 4th resistance R 4, the control signal that the second input end reception control unit 1 of described Sheffer stroke gate U12 sends, the first input end of Sheffer stroke gate U12 is also by the first capacitor C 1 ground connection GND, the output terminal of described Sheffer stroke gate U12 links to each other with the base stage of second switch pipe Q2 by the 12 resistance R 12, the grounded emitter GND of second switch pipe Q2, the collector of second switch pipe Q2 links to each other with an end of the 3rd resistance R 3 and the grid of the first switching tube Q1 respectively, the other end of described the 3rd resistance R 3 links to each other with second source VDD2, and the voltage that this second source VDD2 provides can be 5V.
Preferably, described level conversion unit 2 also comprises the 5th resistance R 5, the second input end of described Sheffer stroke gate U12 is by the 5th resistance R 5 ground connection GND, when control module 1 initially powers on (namely not transmitting control signal), because the second input end of Sheffer stroke gate U12 is connected to the 5th resistance R 5(and also claims pull down resistor) effect, so that the second input end of Sheffer stroke gate U12 is low level, thereby turn-offed driver element 4, guaranteed further that namely low limit driving circuit is in off position, reaches safe purpose.
Preferably, described driver element 4 also comprises the 6th resistance R 6 and the second capacitor C 2, described the 6th resistance R 6 is connected between the grid of the collector of second switch pipe Q2 and the first switching tube Q1, described the second capacitor C 2 is connected between the grid and ground GND of the first switching tube Q1, purpose is the switching loss that causes for reducing by the first switching tube Q1 self-characteristic, and the lifting switch plumber makes efficient.
Preferably, described feedback unit 6 also comprises the 7th resistance R 7 and the 3rd capacitor C 3, described the 7th resistance R 7 and the 3rd capacitor C 3 are attempted by between the second input end and ground GND of the first XOR gate U11, the 7th resistance R 7 and the second resistance R 2 consist of bleeder circuits, are used for eliminating the interference that signal that external environment receives 2 pin of the first XOR gate U11 produces; Described the 3rd capacitor C 3 is used for eliminating the interference that produces when the loaded work piece state switches, and guarantees that level conversion unit can misoperation.
The principle of work of embodiment shown in Figure 2 is as follows:
Can adopt single-chip microcomputer according to this control module 1 of control module 1(, following control module 1 usefulness single-chip microcomputer replaces) state classification of the control signal that sends, have four kinds of states during the drive circuit works of this low limit: stable state 1, Single-chip Controlling signal are low level; Transient state 1, the Single-chip Controlling signal is high level by the low level upset; Stable state 2, Single-chip Controlling signal are high level; Transient state 2, the Single-chip Controlling signal is low level by the high level upset.The below sets forth in the situation of the driving circuit normal operation of low limit and abnormal work (driver element occurs and the direct short circuit of the first power vd D1) respectively one by one.
1, low limit driving circuit normal operation:
Before four kinds of duties of narration circuit, narrate first the initial power-up state of single-chip microcomputer, when initially working on power state, can think that the Single-chip Controlling pin do not work, this moment, this dotted state was defined as low level by pull down resistor R5, be that Sheffer stroke gate U12 the 2nd pin is low level, then Sheffer stroke gate U12 the 3rd pin is exported high level; Through after second switch pipe Q2 anti-phase, the control signal of the first switching tube Q1 is low level, and the first switching tube Q1 is in off state, and load 5 is not worked, and the first switching tube Q1 the 3rd pin is high level.
1) when the Single-chip Controlling signal is low level, circuit working is in stable state 1; Circuit working state and the state consistency that initially works on power, load 5 is not worked, and the first switching tube Q1 the 3rd pin is high level.Because the existence of the first resistance R 1, this first resistance R 1 can deserve to be called draws resistance, the 1st pin of diode D1 is high level, because the second resistance R 2 and the 7th resistance R 7 common formation voltage division processing circuit, the 2nd pin of the first XOR gate U11 will obtain the high level of a stable tolerance interval, namely two of the first XOR gate U11 incoming levels are one high and one low, and then the 3rd pin of the first XOR gate U11 is high level; The 1st pin of Sheffer stroke gate U12 is high level, and the 2nd pin is low level, and then the 3rd pin of Sheffer stroke gate U12 is high level; After anti-phase through second switch pipe Q2, the control signal of the first switching tube Q1 is low level, and the first switching tube Q1 is in off state, and load 5 is not worked, and the first switching tube Q1 the 3rd pin is high level, and circuit is in steady-working state.
2) when the Single-chip Controlling signal was high level by the low level upset, circuit working was in transient state 1; Because the existence of circuit delay effects, the late-class circuit level is followed the front stage circuits level translation needs the regular hour, during this period of time, the first switching tube Q1 still is in off state, load 5 is not worked, and namely the 2nd pin of the first XOR gate U11 this moment still is high level, and the 1st pin of the first XOR gate U11 has overturn and is high level, two input signals of the first XOR gate U11 are high level, and its 3rd pin of exporting the first XOR gate U11 is low level; But because the 4th resistance R 4 and RC charge-discharge circuit of the first capacitor C 1 common formation, the 1st pin of Sheffer stroke gate U12 will keep high level a period of time, and the 2nd pin of Sheffer stroke gate U12 has overturn and has been high level at this moment, and then the 3rd pin of its output U12 is low level; After anti-phase through second switch pipe Q2, thereby the upset of the control signal of the first switching tube Q1 makes the first switching tube Q1 conducting for high level, and load 5 control ends i.e. the 3rd pin output switching activity of the first switching tube Q1 are low level, load 5 work; Because diode D1 has forward conduction, so also will overturning, the 1st pin of diode D1 is low level, after the second resistance R 2,7 processing of the 7th resistance R, the 2nd pin of the first XOR gate U11 will obtain a reliable and stable low level, namely the 2nd pin of the first XOR gate U11 will be low level by the high level upset, two incoming levels of the first XOR gate U11 are one high and one low, and the 3rd pin of its output U11 overturns after of short duration low level and is high level; The above-mentioned RC charge-discharge circuit that jointly is made of the 4th resistance R 4 and the first capacitor C 1 is used for guaranteeing that the 1st pin of Sheffer stroke gate U12 is always high level within during this period of time that circuit will enter stable state 2 duties this moment.
3) when the Single-chip Controlling signal is high level, circuit working is in stable state 2; This state is followed transient state 1 duty, the first switching tube Q1 is in conducting state, load 5 work, the first switching tube Q1 the 3rd pin is low level, because diode D1 has the unidirectional general character, so the 1st pin of diode D1 also is low level, after the second resistance R 2,7 processing of the 7th resistance R, the 2nd pin of the first XOR gate U11 will obtain a reliable and stable low level, the 2nd pin of the first XOR gate U11 is low level, namely two of the first XOR gate U11 incoming levels are one high and one low, and the 3rd pin of its output U11 is high level; The 1st pin of Sheffer stroke gate U12 is high level, and the 2nd pin is high level, and the 3rd pin of its output U12 is low level; Through after second switch pipe Q2 anti-phase, the control signal of the first switching tube Q1 is continuously high level, and the first switching tube Q1 continues conducting, load 5 work, and load 5 control ends are that the 3rd pin of the first switching tube Q1 is continuously low level, circuit is in steady-working state.
4) when the Single-chip Controlling signal was low level by the high level upset, circuit working was in transient state 2; Because the existence of circuit delay effects, the late-class circuit level is followed the front stage circuits level translation needs the regular hour, during this period of time, the first switching tube Q1 still is in conducting state, load 5 work, namely the 2nd pin of the first XOR gate U11 this moment still is low level, and the 1st pin of U11 has overturn and is low level, two input signals of U1 are low level, and the 3rd pin of its output U11 is low level; But because RC charge-discharge circuit of the common formation of R4 and C1, the 1st pin of Sheffer stroke gate U12 will keep high level a period of time, and the 2nd pin of U12 has overturn and has been low level at this moment, and then the 3rd pin of its output U12 is high level; Through after second switch pipe Q2 anti-phase, the control signal upset of the first switching tube Q1 is low level, and the first switching tube Q1 turn-offs, and load 5 is not worked, and load 5 control ends i.e. the 3rd pin output switching activity of the first switching tube Q1 are high level; Because load 5 is inductive load 5; this moment, the first switching tube Q1 the 3rd pin will produce higher anti-phase electromotive force; diode D1 has anti-phase turn-off function; suppress this anti-phase electromotive force; protect the first XOR gate U11 chip not affected by it; diode D1 and the first resistance R 1 common definite at this moment the 1st pin of diode D1 are high level; and R2 and R7 consist of the voltage division processing circuit jointly; the 2nd pin of the first XOR gate U11 will obtain the high level of a stable tolerance interval; the 2nd pin that is U11 will be high level by the low level upset; two incoming levels of U11 are one high and one low; the 3rd pin of its output U11 overturns after of short duration low level and is high level, and circuit will enter stable state 1 duty this moment.
2, low limit driving circuit abnormality work, namely driver element occurs and the direct short circuit of the first power vd D1, and namely the 3rd pin of the first switching tube is to the first power vd D1 short circuit:
When the 3rd pin of the first switching tube during to the first power vd D1 short circuit, then the first switching tube Q1 the 3rd pin is always high level, the first XOR gate U11 the 2nd pin also is always high level, be low level and overturn when being low level by high level when the Single-chip Controlling signal this moment, the circuit working state all stable state 1 with the circuit normal operation is consistent, the first switching tube Q1 is in off state, and load 5 is not worked.When the Single-chip Controlling signal is high level by the low level upset, because the 2nd pin of the first XOR gate U11 is always high level, so its output U11 the 3rd pin is low level; But because the 4th resistance R 4 and RC charge-discharge circuit of the first capacitor C 1 common formation, the 1st pin of Sheffer stroke gate U12 will keep high level a period of time, and the 2nd pin of U12 has overturn and has been high level at this moment, and then the 3rd pin of its output U12 is low level; Through after second switch pipe Q2 anti-phase, be high level as the control signal of the first switching tube Q1, namely the first switching tube Q1 is in conducting state; Because the 3rd pin of the first switching tube Q1 is to the first power vd D1 short circuit, so 2 pin of the first XOR gate U11 are always high level, the output that is U11 will remain low level, the 1st pin of Sheffer stroke gate U12 will overturn after the RC circuit discharging is finished and be low level, its output this moment U12 the 3rd pin will overturn after of short duration low level and be high level, and through after second switch pipe Q2 anti-phase, also will overturn after of short duration high level as the control signal of the first switching tube Q1 is low level, thereby turn-offs the first switching tube Q1.When Single-chip Controlling signal when being high, because the 2nd pin of the first XOR gate U11 is always high level, so its output U11 the 3rd pin is low level; The 1st pin of Sheffer stroke gate U12 is low level, the 2nd pin of U12 is high level, the 3rd pin of its output U12 is high level, the control signal through the first switching tube Q1 after second switch pipe Q2 anti-phase is thereby that low level is turn-offed the first switching tube Q1, the 3rd pin of the first switching tube Q1 is always high level, and circuit is in steady-working state.
As from the foregoing; when the 3rd pin of the first switching tube during to the first power vd D1 short circuit; only when the Single-chip Controlling signal is high level by the low level upset; just conducting of the first switching tube Q1; but the discharge time of RC circuit when only being high level for the Single-chip Controlling signal by the low level upset owing to its conducting working time; this RC circuit is made of the 4th resistance R 4 and the first capacitor C 1; the heat that the first switching tube Q1 distributes in this time far is not enough to it is burnt; it should be noted that at this; although when the Single-chip Controlling signal is high level by the low level upset; the first switching tube Q1 conducting; but this is constantly to occur moment; do not affect core concept of the present utility model; namely make when abnormal work (namely the 3rd pin of the first switching tube Q1 is to the first power vd D1 short circuit) driver element 4 stop to drive load 5 work at low limit driving circuit; namely realize stopping to drive load 5 work by turn-offing the first switching tube Q1, thereby realize the function of protection driver element 4.
The physical circuit figure of another embodiment that low limit driving circuit as shown in Figure 3 provides, low limit driving circuit comprises level conversion unit 2, amplifying unit 3, driver element 4 and feedback unit 6, described driver element 4 comprises having grid, the first switching tube Q1 of emitter and collector, described amplifying unit 3 is for having positive input, the operational amplifier BG1 of inverting input and output terminal, described level conversion unit 2 comprises the second XOR gate U21, with door U22, the 8th resistance R 8 and the 4th capacitor C 4, the grounded emitter GND of the first switching tube Q1, the collector of the first switching tube Q1 links to each other with the negative electrode of diode D1 and an end of load 5 respectively, the anode of diode D1 links to each other with an end of the first resistance R 1 and an end of the second resistance R 2 respectively, the other end of the other end of described the first resistance R 1 and load 5 all links to each other with the first power vd D1, the control signal that the first input end reception control unit 1 of described the second XOR gate U21 sends, the second input end of the second XOR gate U21 links to each other with the other end of the second resistance R 2, the output terminal of the second XOR gate U21 links to each other with first input end with door U22 through the 8th resistance R 8, the control signal that the second input end reception control unit 1 described and door U22 sends, also pass through the 4th capacitor C 4 ground connection GND with the first input end of door U22, describedly link to each other with the positive input of operational amplifier BG1 with the output terminal of door U22, the inverting input of operational amplifier BG1 links to each other with the output terminal of operational amplifier BG1, and the output terminal of described operational amplifier BG1 also links to each other with the grid of the first switching tube Q1.
The principle of work of this embodiment is similar to a upper embodiment (embodiment illustrated in fig. 2), does not therefore do specifying at this.
Preferably, described level conversion unit 2 also comprises the 9th resistance R 9, described the second input end with door U22 passes through the 9th resistance R 9 ground connection GND, when control module 1 initially powers on (namely not transmitting control signal), because the second input end of Sheffer stroke gate is connected to the 9th resistance R 9(and also claims pull down resistor) effect so that the second input end of Sheffer stroke gate is low level, thereby turn-offed driver element 4, guaranteed further that namely low limit driving circuit is in off position, reaches safe purpose.
Preferably, described driver element 4 also comprises the tenth resistance R 10 and the 5th capacitor C 5, described the tenth resistance R 10 is connected between the grid of the output terminal of operational amplifier BG1 and the first switching tube Q1, described the 5th capacitor C 5 is connected between the grid and ground GND of the first switching tube Q1, purpose is the switching loss that causes for reducing by the first switching tube Q1 self-characteristic, and the lifting switch plumber makes efficient.
Preferably, described feedback unit 6 also comprises the 11 resistance R 11 and the 6th capacitor C 6, described the 11 resistance R 11 and the 6th capacitor C 6 are attempted by between the second input end and ground GND of the second XOR gate U21, the 7th resistance R 7 and the second resistance R 2 consist of bleeder circuits, are used for eliminating the interference that signal that external environment receives 2 pin of the first XOR gate U11 produces; Described the 3rd capacitor C 3 is used for eliminating the interference that produces when the loaded work piece state switches, and guarantees that level conversion unit can misoperation.
It should be noted that at this first switching tube Q1 among Fig. 2, Fig. 3 adopts the IGBT pipe of N raceway groove, but in the implementation, described the first switching tube Q1 can also adopt the MOSFET of NPN triode, N raceway groove etc.; Described second switch pipe Q2 adopts the NPN triode, certainly can also adopt other switching tube with similar functions, does not do one by one at this and introduces.
The above only is preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of within spirit of the present utility model and principle, doing, be equal to and replace and improvement etc., all should be included within the protection domain of the present utility model.
Claims (10)
1. low limit driving circuit, it is characterized in that, comprise level conversion unit, amplifying unit, driver element and feedback unit, described level conversion unit, amplifying unit and driver element successively electricity link to each other, described feedback unit links to each other with driver element with level conversion unit respectively, and described driver element also links to each other with an end of load, another termination first power supply of described load, wherein
The control signal that described level conversion unit receives and control module is sent and feedback unit feedback of feedback signal carry out outputs level signals after the logical operation, and this level signal makes driver element stop to drive loaded work piece when driver element and the first power supply short circuit after amplifying unit amplifies.
2. low limit according to claim 1 driving circuit, it is characterized in that, described driver element comprises having first utmost point, the first switching tube of second utmost point and the 3rd utmost point, described feedback unit comprises the first resistance, the second resistance and diode, first utmost point of described the first switching tube links to each other with amplifying unit, the second utmost point ground connection of the first switching tube, the 3rd utmost point of the first switching tube links to each other with the negative electrode of diode and an end of load respectively, the anode of diode links to each other with an end of the first resistance and an end of the second resistance respectively, the other end of described the first resistance all links to each other with the first power supply with the other end of load, and the other end of described the second resistance links to each other with level conversion unit.
3. low limit according to claim 2 driving circuit, it is characterized in that, described amplifying unit comprises the second switch pipe, the 3rd resistance and the 12 resistance, described level conversion unit comprises the first XOR gate, Sheffer stroke gate, the 4th resistance and the first electric capacity, described second switch pipe has first utmost point, second utmost point and the 3rd utmost point, the control signal that the first input end reception control unit of described the first XOR gate sends, the second input end of the first XOR gate links to each other with the other end of the second resistance, the output terminal of the first XOR gate links to each other with the first input end of Sheffer stroke gate through the 4th resistance, the control signal that the second input end reception control unit of described Sheffer stroke gate sends, the first input end of Sheffer stroke gate is also by the first capacity earth, the output terminal of described Sheffer stroke gate extremely links to each other with first of second switch pipe by the 12 resistance, the second utmost point ground connection of second switch pipe, the 3rd utmost point of second switch pipe extremely links to each other with first of an end of the 3rd resistance and the first switching tube respectively, and the other end of described the 3rd resistance links to each other with second source.
4. low limit according to claim 3 driving circuit is characterized in that described level conversion unit also comprises the 5th resistance, and the second input end of described Sheffer stroke gate is by the 5th resistance eutral grounding.
5. low limit according to claim 3 driving circuit, it is characterized in that, described driver element also comprises the 6th resistance and the second electric capacity, described the 6th resistance is connected between first utmost point of the 3rd utmost point of second switch pipe and the first switching tube, and described the second electric capacity is connected between first utmost point and ground of the first switching tube.
6. low limit according to claim 3 driving circuit is characterized in that described feedback unit also comprises the 7th resistance and the 3rd electric capacity, and described the 7th resistance and the 3rd electric capacity are attempted by between second input end and ground of the first XOR gate.
7. low limit according to claim 2 driving circuit, it is characterized in that, described amplifying unit is for having positive input, the operational amplifier of inverting input and output terminal, described level conversion unit comprises the second XOR gate, with door, the 8th resistance and the 4th electric capacity, the control signal that the first input end reception control unit of described the second XOR gate sends, the second input end of the second XOR gate links to each other with the other end of the second resistance, the output terminal of the second XOR gate through the 8th resistance with link to each other with the first input end of door, the control signal that the second input end reception control unit described and door sends, also pass through the 4th capacity earth with the first input end of door, describedly link to each other with the positive input of operational amplifier with the output terminal of door, the inverting input of operational amplifier links to each other with the output terminal of operational amplifier, and the output terminal of described operational amplifier also extremely links to each other with first of the first switching tube.
8. low limit according to claim 7 driving circuit is characterized in that described level conversion unit also comprises the 9th resistance, and the second input end of described and door is by the 9th resistance eutral grounding.
9. low limit according to claim 7 driving circuit, it is characterized in that, described driver element also comprises the tenth resistance and the 5th electric capacity, described the tenth resistance is connected between first utmost point of the output terminal of operational amplifier and the first switching tube, and described the 5th electric capacity is connected between first utmost point and ground of the first switching tube.
10. low limit according to claim 7 driving circuit is characterized in that described feedback unit also comprises the 11 resistance and the 6th electric capacity, and described the 11 resistance and the 6th electric capacity are attempted by between second input end and ground of the second XOR gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201220429673.5U CN202815478U (en) | 2012-08-28 | 2012-08-28 | Low side driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201220429673.5U CN202815478U (en) | 2012-08-28 | 2012-08-28 | Low side driving circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202815478U true CN202815478U (en) | 2013-03-20 |
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ID=47874331
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201220429673.5U Expired - Lifetime CN202815478U (en) | 2012-08-28 | 2012-08-28 | Low side driving circuit |
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| Country | Link |
|---|---|
| CN (1) | CN202815478U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108173248A (en) * | 2018-01-18 | 2018-06-15 | 联合汽车电子有限公司 | Switch protecting circuit |
| CN117477916A (en) * | 2023-12-21 | 2024-01-30 | 拓尔微电子股份有限公司 | Low-side driving circuit and motor driving circuit |
-
2012
- 2012-08-28 CN CN201220429673.5U patent/CN202815478U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108173248A (en) * | 2018-01-18 | 2018-06-15 | 联合汽车电子有限公司 | Switch protecting circuit |
| CN108173248B (en) * | 2018-01-18 | 2023-11-10 | 联合汽车电子有限公司 | Switch protection circuit |
| CN117477916A (en) * | 2023-12-21 | 2024-01-30 | 拓尔微电子股份有限公司 | Low-side driving circuit and motor driving circuit |
| CN117477916B (en) * | 2023-12-21 | 2024-03-12 | 拓尔微电子股份有限公司 | Low-side driving circuit and motor driving circuit |
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