CN202771695U - Demonstration teaching tool used for improving digital circuit application capability - Google Patents

Demonstration teaching tool used for improving digital circuit application capability Download PDF

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Publication number
CN202771695U
CN202771695U CN 201220048908 CN201220048908U CN202771695U CN 202771695 U CN202771695 U CN 202771695U CN 201220048908 CN201220048908 CN 201220048908 CN 201220048908 U CN201220048908 U CN 201220048908U CN 202771695 U CN202771695 U CN 202771695U
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China
Prior art keywords
chip
digital circuit
circuit application
demonstration teaching
chips
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Expired - Fee Related
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CN 201220048908
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Chinese (zh)
Inventor
赵德才
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Individual
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Individual
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Priority to CN 201220048908 priority Critical patent/CN202771695U/en
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Publication of CN202771695U publication Critical patent/CN202771695U/en
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Abstract

The utility model relates to the field of electronic technology and provides a demonstration teaching tool used for improving a digital circuit application capability. Digital circuit course is a key required course for students majored in electronics in university. Chips provided in usual experiments are the good ones selected in advance by a teacher through using an integrated circuit tester. Chips with even minor damages are treated as discards. An inner logical structure map of the chips is also given in experiments. A student only needs to connect lines according to the map when performing an experiment. The capability of the student is improved by a limited degree slowly. The demonstration teaching tool used for improving the digital circuit application capability provided by the utility model can be used for teaching the student how to detect the chip in a condition without the tester and how to detect functions of pins in a condition of having no knowledge of the inner logical structure map of the chips. The demonstration teaching tool used for improving the digital circuit application capability provided by the utility model includes a first IC testing area 1, a second IC testing area 2, a truth table area 3, a power source area 4, an LED indicator light 5, a first chip socket 6, a second chip socket 7, a state recording lamp 8 and a converting switch 9. In experiment demonstration, the related chips and leads need to be equipped according to requirements. Whether the chips are good or not and the pin functions can be judged according to an output condition through inputting electrical levels to corresponding pins in the experiments.

Description

A kind of demonstration teaching aid that improves the digital circuit application power
Technical field
The utility model belongs to electronic technology field, relates to a kind of demonstration teaching aid that improves the digital circuit application power.
Background technology
Digital Circuits Course is the emphasis compulsory course of university's Electronics Specialties, this course is a class that practicality is very strong, must start more, it is good that many experiments could be learned, the chip of giving in experiment at ordinary times all is the good chip that teacher filters out with integrated circuit tester in advance, also will work as the discard processing even there is sub-fraction to damage, doing when experiment given chip internal building-block of logic also, the student does experiment just according to the drawing line, ability improves slow and limited, this experiment method is unfavorable for improving undergraduate application power and professional adaptability to changes, runs into some problems and just can't process, and is unfavorable for cultivating creative university student.
Summary of the invention
For a kind of demonstration teaching aid that improves the digital circuit application power that provides is provided, the technical scheme of employing is as described below just for the utility model.
A kind of demonstration teaching aid that improves the digital circuit application power as shown in Figure 1 is characterized in that: comprise an IC test section 1; The 2nd IC test section 2; Truth table district 3; Power supply area 4; LED light 5; The first chip carrier socket 6; The second chip carrier socket 7; State recording lamp 8; Switch 9.
The one IC test section 1 provides one of 14 pin chip carrier socket, and it is inner that this socket is positioned at a large chip outline, and the back side is corresponding continuous one by one with wire, and there is corresponding plug wire hole the chip outline outside; The one IC test section 1 also comprises LED light 5, and this lamp has a plug wire hole.
The 2nd IC test section 2 provides one of 14 pin chip carrier socket, and this socket is positioned at the graphics chip inside of an amplification, and chip internal structure figure is decorated with in the graphics chip inside of amplification, and the back side is corresponding continuous one by one with wire, and there is corresponding plug wire hole the chip outline outside;
Truth table district 3 is characterised in that: there is a plug wire hole on the various combinations next door of AB variable, and corresponding provides and the unified level of next door figure notation; The state of output variable Y is with 4 following state recording lamp 8 records, the bright expression 1 of lamp, and the lamp expression 0 of going out, the change of state is to realize by switch 9.
Description of drawings
Fig. 1 is front of the present utility model layout;
Among the figure, an IC test section 1; The 2nd IC test section 2; Truth table district 3; Power supply area 4; LED light 5; The first chip carrier socket 6; The second chip carrier socket 7; State recording lamp 8; Switch 9
Embodiment
Below be specific embodiment of the utility model and by reference to the accompanying drawings, the technical solution of the utility model is further described, but the utility model be not limited to these embodiment.
Embodiment 1
Utilize the utility model test chip quality
A given chip 74LS08, if known its inner structure, whether the device of not knowing this chip internal is intact, can insert chip 74LS08 on the core socket of the second chip carrier socket 7, connects the GND of the second chip carrier socket 7 and the GND of power supply area 4 with a wire; Again with a wire connect the VCC of the second chip carrier socket 7 and power supply area 4+5V; Connect the 3rd pin of the second chip carrier socket 7 and the plug wire hole of LED light 5 with a wire; Connect respectively 1 of the second chip carrier socket 7 with 2 wires again, 00 two terminals in 2 pin and truth table district 3, observe the state of LED light 5, record this experimental state by switch 9 corresponding to 00 state back of stirring truth table district 3, remove 2 wires just now, press same method, connect respectively 1 of the second chip carrier socket 7 with these 2 wires again, two terminals of 01 correspondence in 2 pin and truth table district 3, observe the state of LED light 5, record this experimental state by switch 9 corresponding to 01 state back of stirring truth table district 3 again ... situation by observation state recording lamp 8, in conjunction with the logical expression Y=AB of chip 74LS08, can judge namely whether first set is intact with door. in like manner can test the quality of other 3 cover and door.
Embodiment 2
Utilize the utility model test chip pin
A given chip 74LS08 is and the door chip not know this chip internal structure and pin function if only know it.Can insert chip 74LS08 on the core socket of the first chip carrier socket 6, connect the GND of the first chip carrier socket 6 and the GND of power supply area 4 with a wire; Again with a wire connect the VCC of the first chip carrier socket 6 and power supply area 4+5V; The plug wire hole that connects LED light 5 with wire one end, the other end touches at 1-6 and the 8-13 plug wire hole of the first chip carrier socket 6 successively, note observing LED light 5, it is bright that discovery has four LED light 5, and these four inside corresponding to plug wire hole are exactly the lead-out terminal of this chip internal quadruplet and door so; Next step experiment is definite and is connected four input terminals that lead-out terminal is corresponding: connect LED light 5 and an output terminal with a wire, this moment, LED light 5 was bright, use again a wire, the GND in one termination power district 4, the other end touches remaining 8 plug wire holes successively, have to touch for 2 times LED light 5 is extinguished, twice correspondence of this that extinguishes be exactly this cover and 2 input terminals of door, in like manner can measure the pin function of its excess-three cover and door.
Different as required, the utility model can also use 74LS32 etc. chip to demonstrate, and can also judge the quality of chip etc.
Specific embodiment described herein only is to the explanation for example of the utility model spirit.The utility model person of ordinary skill in the field can make various modifications or replenishes or adopt similar mode to substitute described specific embodiment, but can't depart from the defined scope of spirit of the present utility model.

Claims (4)

1. a demonstration teaching aid that improves the digital circuit application power is characterized in that comprising: an IC test section (1), the 2nd IC test section (2), truth table district (3), power supply area (4), LED light (5), the first chip carrier socket (6), the second chip carrier socket (7), state recording lamp (8), switch (9); Power supply area (4).
2. a kind of demonstration teaching aid that improves the digital circuit application power according to claim 1, its IC test section (1) provides 14 pin chip carrier sockets: the first chip carrier socket (6), it is inner that this socket is positioned at a large chip outline, the back side is corresponding continuous one by one with wire, and there is corresponding plug wire hole the chip outline outside; The one IC test section (1) also comprises LED light (5), and this lamp has a plug wire hole.
3. a kind of demonstration teaching aid that improves the digital circuit application power according to claim 1, its the 2nd IC test section (2) provides one of 14 pin chip carrier socket: the second chip carrier socket (7), this socket is positioned at the graphics chip inside of an amplification, chip internal structure figure is decorated with in the graphics chip inside of amplifying, the back side is corresponding continuous one by one with wire, and there is corresponding plug wire hole the chip outline outside.
4. a kind of demonstration teaching aid that improves the digital circuit application power according to claim 1, its truth table district (3) is characterised in that: there is a plug wire hole on the various combinations next door of AB variable, and corresponding provides and the unified level of next door figure notation; The state of output variable Y is with following 4 state recording lamps (8) record, the bright expression 1 of lamp, and the lamp expression 0 of going out, the change of state is to realize by switch (9).
CN 201220048908 2012-02-16 2012-02-16 Demonstration teaching tool used for improving digital circuit application capability Expired - Fee Related CN202771695U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201220048908 CN202771695U (en) 2012-02-16 2012-02-16 Demonstration teaching tool used for improving digital circuit application capability

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201220048908 CN202771695U (en) 2012-02-16 2012-02-16 Demonstration teaching tool used for improving digital circuit application capability

Publications (1)

Publication Number Publication Date
CN202771695U true CN202771695U (en) 2013-03-06

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201220048908 Expired - Fee Related CN202771695U (en) 2012-02-16 2012-02-16 Demonstration teaching tool used for improving digital circuit application capability

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CN (1) CN202771695U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103915023A (en) * 2014-03-17 2014-07-09 山东师范大学 Digital circuit experiment device and experiment method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103915023A (en) * 2014-03-17 2014-07-09 山东师范大学 Digital circuit experiment device and experiment method
CN103915023B (en) * 2014-03-17 2015-12-09 山东师范大学 Digital circuit experiment device and experimental technique

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GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20130306

Termination date: 20140216