CN202758619U - Static random access memory preservation state low electricity leakage power circuit - Google Patents
Static random access memory preservation state low electricity leakage power circuit Download PDFInfo
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- CN202758619U CN202758619U CN201220422635.7U CN201220422635U CN202758619U CN 202758619 U CN202758619 U CN 202758619U CN 201220422635 U CN201220422635 U CN 201220422635U CN 202758619 U CN202758619 U CN 202758619U
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- preservation state
- state low
- nmos
- nmos pipe
- static ram
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Abstract
The utility model applies to the field of integrated circuits and provides a static random access memory preservation state low electricity leakage power circuit which comprises a power control circuit. The power control circuit is formed by connection of tops of N-channel metal oxide semiconductor (NMOS) tubes. According to the static random access memory preservation state low electricity leakage power circuit, connection of the tops of the NMOS tubes is adopted, when the NOMS is relatively strong due to craft deviation, electricity leakage can effectively be followed up, and rail-to-rail pressure of a static random access memory is enabled not to be lowered quickly, meanwhile, due to the fact that substrate bias effect exists, the threshold value is enabled to rise along with rising of the power supply voltage, and maintaining leakage current under high voltage is reduced.
Description
Technical field
The utility model belongs to integrated circuit fields, relates in particular to a kind of static RAM preservation state low leakage electrode source circuit.
Background technology
Static RAM (Static RAM, SRAM) preservation state low leakage electrode source circuit can be divided into two large classes, and a class is top (header) design, and another kind of is afterbody (footer) design.Circuit generally has three kinds of main structures, as shown in Figure 1.
Power control circuit 100 is the header design of standard, and power control circuit 101 is standard footer design, and 10 are diode (diode) connection with being connected, and make threshold value of the rail-to-rail voltage drop of static RAM.10,11 threshold value under the high power supply voltage state with the low supply voltage state under basically identical keep leakage current limited so that supply voltage when higher, reduces.
Power control circuit 102 improves connection for footer, and also for diode connects, still 12 exist the substrate bias effect, and its threshold value is risen with supply voltage, can effectively reduce under the high voltage to keep leakage current.It is leading that but N-type metal-oxide semiconductor transistor (NMOS) electric leakage of considering static RAM accounts for, and when having process deviation and mains voltage variations, leakage current can be followed its variation.
Summary of the invention
Technical problem to be solved in the utility model provides a kind of static RAM preservation state low leakage electrode source circuit, be intended to solve in the existing static RAM preservation state low leakage electrode source circuit, when NMOS existed process deviation and mains voltage variations, leakage current can be followed the problem of its variation.
The technical solution of the utility model is achieved in that a kind of static RAM preservation state low leakage electrode source circuit, comprises power control circuit, and described power control circuit is that NMOS pipe top connects.
Further, described power control circuit comprises that a NMOS diode connects.
The drain electrode of described NMOS pipe connects power supply, and drain electrode is connected with the continuous NMOS diode that forms of grid, and source electrode is connected with SRAM, and substrate links to each other with ground wire.
Described NMOS pipe is level threshold value NMOS pipe, low threshold value NMOS pipe, perhaps high threshold NMOS pipe.
Described power control circuit comprises that the NMOS diode of two series connection connects.
Described NMOS pipe is low threshold value device or level threshold value NMOS pipe.
The utility model embodiment adopts NMOS pipe top to connect, when NMOS is stronger owing to process deviation is in, can effectively follow electric leakage, can not make the rail-to-rail voltage drop of SRAM too fast, there is equally substrate bias effect, its threshold value can be risen with supply voltage, keep leakage current under the reduction high voltage.
Description of drawings
Fig. 1 is the realization schematic diagram of the static RAM preservation state low leakage electrode source circuit that provides of prior art
Fig. 2 is the realization schematic diagram of the static RAM preservation state low leakage electrode source circuit that provides of the utility model the first embodiment;
Fig. 3 is the realization schematic diagram of the static RAM preservation state low leakage electrode source circuit that provides of the utility model the second embodiment;
Fig. 4 is the realization schematic diagram of the static RAM preservation state low leakage electrode source circuit that provides of the utility model the 3rd embodiment.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the utility model, and be not used in restriction the utility model.
Static RAM preservation state low leakage electrode source circuit among the utility model embodiment adopts NMOS pipe top to connect.
Fig. 2 has provided the realization schematic diagram of the static RAM preservation state low leakage electrode source circuit that the utility model the first embodiment provides.
This static RAM preservation state low leakage electrode source circuit adopts NMOS pipe top to connect, and comprises power control circuit 201 and SRAM.
In the power control circuit 201, the drain electrode of NMOS pipe connects power supply, and drain electrode is connected 20 with the continuous NMOS diode that forms of grid, and source electrode is connected with SRAM, and substrate links to each other with ground wire.
SRAM is in hold mode when work, and NMOS diode connection 20 makes at least one threshold voltage of rail-to-rail lower voltage of SRAM.Can not make the track to track voltage drop of SRAM too fast.When supply voltage raise or reduce, the threshold voltage of NMOS pipe also can be followed the variation of supply voltage and be risen or descend.So just can effectively reduce the maintenance leakage current.
As an embodiment of the present utility model, the NMOS pipe among Fig. 2 can adopt level threshold value NMOS pipe or hang down threshold value NMOS pipe.
When adopting low threshold value NMOS pipe, this power control circuit NMOS threshold voltage is low during work, and rail-to-rail voltage drop amplitude that can SRAM diminishes.
Fig. 3 is the realization principle of static RAM preservation state low leakage electrode source circuit among the utility model the second embodiment.
Among this embodiment, in power control circuit 202, what the NMOS diode connected 22 employings is high threshold NMOS pipe.
During work, the NMOS of this power control circuit can guarantee to offer SRAM under high voltage electric current is not subjected to the impact of mains voltage variations substantially.
The realization principle of static RAM preservation state low leakage electrode source circuit among Fig. 4 utility model the 3rd embodiment.
Among this embodiment, in power control circuit 202, the NMOS diode connects the series connection of employing NMOS diode, and soon NMOS diode connection 23 is connected 24 with the NMOS diode and links to each other.The NMOS pipe can be low threshold value NMOS pipe or level threshold value NMOS pipe.
The series connection of NMOS diode makes two threshold voltages of the rail-to-rail voltage drop of SRAM during work, and when process deviation is in stronger state, or under the low voltage condition of high temperature, still have very strong hold facility.
The utility model embodiment adopts NMOS pipe top to connect, when NMOS is stronger owing to process deviation is in, can effectively follow electric leakage, can not make the rail-to-rail voltage drop of SRAM too fast, there is equally substrate bias effect, its threshold value can be risen with supply voltage, keep leakage current under the reduction high voltage.
The above only is preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of within spirit of the present utility model and principle, doing, be equal to and replace and improvement etc., all should be included within the protection domain of the present utility model.
Claims (6)
1. a static RAM preservation state low leakage electrode source circuit comprises power control circuit, it is characterized in that, described power control circuit is that NMOS pipe top connects.
2. static RAM preservation state low leakage electrode source circuit as claimed in claim 1 is characterized in that, described power control circuit comprises that a NMOS diode connects.
3. static RAM preservation state low leakage electrode source circuit as claimed in claim 2 is characterized in that, the drain electrode of described NMOS pipe connects power supply, and drain electrode is connected with the continuous NMOS diode that forms of grid, and source electrode is connected with SRAM, and substrate links to each other with ground wire.
4. static RAM preservation state low leakage electrode source circuit as claimed in claim 1 is characterized in that, described NMOS pipe is level threshold value NMOS pipe, low threshold value NMOS pipe, perhaps high threshold NMOS pipe.
5. static RAM preservation state low leakage electrode source circuit as claimed in claim 1 is characterized in that, described power control circuit comprises that the NMOS diode of two series connection connects.
6. static RAM preservation state low leakage electrode source circuit as claimed in claim 5 is characterized in that, described NMOS pipe is low threshold value device or level threshold value NMOS pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201220422635.7U CN202758619U (en) | 2012-08-24 | 2012-08-24 | Static random access memory preservation state low electricity leakage power circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201220422635.7U CN202758619U (en) | 2012-08-24 | 2012-08-24 | Static random access memory preservation state low electricity leakage power circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202758619U true CN202758619U (en) | 2013-02-27 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201220422635.7U Expired - Lifetime CN202758619U (en) | 2012-08-24 | 2012-08-24 | Static random access memory preservation state low electricity leakage power circuit |
Country Status (1)
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| CN (1) | CN202758619U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102789809A (en) * | 2012-08-24 | 2012-11-21 | 苏州兆芯半导体科技有限公司 | Low-leakage power supply circuit in save state of static random access memory |
-
2012
- 2012-08-24 CN CN201220422635.7U patent/CN202758619U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102789809A (en) * | 2012-08-24 | 2012-11-21 | 苏州兆芯半导体科技有限公司 | Low-leakage power supply circuit in save state of static random access memory |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130227 |
|
| CX01 | Expiry of patent term |