CN202678946U - Power supply failure recoil protection circuit - Google Patents

Abstract

Provided is a power supply failure recoil protection circuit which can protect a power supply device in case of power failure and comprises a maximum voltage selection circuit and a power supply failure turn-off circuit. The maximum voltage selection circuit is composed of a voltage comparator COMP1, an inverter INV1, a first PMOS field-effect tube M1 and a second PMOS field-effect tube M2; a positive input terminal of the comparator COMP1 is connection with a power supply Vin, and a negative input terminal is in connection with an output terminal Vout of a device to be protected; an output terminal of the comparator COMP1 is connection with an input terminal of the inverter INV1; an output terminal of the inverter INV1 is in connection with a grid of the second PMOS field-effect tube M2. The power supply failure turn-off circuit is composed of a current source I0, a third PMOS field-effect tube M3 and a fourth PMOS field-effect tube M4; a negative electrode of the current source I0 is grounding and a positive electrode is in connection with a drain electrode of the third PMOS field-effect tube M3; a source electrode of the fourth PMOS field-effect tube M4 is in short connection with a substrate and is in connection with the power supply Vin, and a drain electrode is in connection with a grid electrode of a power tube M0 of the device to be protected. The power supply failure recoil protection circuit is suitable for power supply management products.

Description

Power supply power-fail recoil protective circuit

Technical field

The utility model relates to protective circuit, particularly power supply power-fail recoil protective circuit.

Background technology

In the use procedure of power management product, the situation of the rapid power down of supply voltage sometimes can occur, for example the Cold Start of automobile.Traditional power source design power flow schematic diagram is as shown in Figure 1: internal control circuit wherein is the grid voltage of power ratio control pipe M0; Generally speaking, the substrate of power supply product power tube all is direct and source shorted, in case power supply power-fail, owing to the output parallel connection of power tube M0 a large capacitor C 0 output voltage is changed slowly, output voltage will be higher than input voltage and make the parasitic diode D2 conducting of power tube M0 so, produce very large recoil electric current, cause power tube M0 to be burnt chip failure.

Summary of the invention

The utility model will solve in the use procedure of power management product; when the rapid power down of power supply occurs; the output voltage of power tube is higher than input voltage; the power tube problem that very large recoil electric current is burnt because its parasitic diode conducting produces provides a kind of power supply power-fail recoil protective circuit of the present utility model for this reason.

In order to address the above problem, its special character of the technical solution adopted in the utility model is to comprise maximum voltage selection circuit and a power remove circuit, the substrate electric potential of circuit in order to provide a Buck voltage to remove to control protected power tube is provided for described maximum voltage, and described power remove circuit is in order to turn-off protected device when the power supply power-fail;

Described maximum voltage selects circuit to be comprised of voltage comparator COMP1, inverter INV1, a PMOS field effect transistor M1 and the 2nd PMOS field effect transistor M2; The positive input termination power supply Vin of voltage comparator COMP1, the output end vo ut of the negative input termination protected device of voltage comparator COMP1, the input of the output termination inverter INV1 of voltage comparator COMP1, the grid of output termination the 2nd PMOS field effect transistor M2 of inverter INV1, the grid of the one PMOS field effect transistor M1 and described voltage comparator COMP1 output are connected with inverter INV1 input and are connect end and be connected, meet the substrate electric potential Buck of protected device behind the source electrode of the one PMOS field effect transistor M1 and the substrate short circuit, the drain electrode of the one PMOS field effect transistor M1 meets the output end vo ut of protected device, meet the substrate electric potential Bcuk of protected device behind the source electrode of the 2nd PMOS field effect transistor M2 and the substrate short circuit, the drain electrode of the 2nd PMOS field effect transistor M2 meets power supply Vin;

Described power remove circuit is comprised of current source I0, the 3rd PMOS field effect transistor M3 and the 4th PMOS field effect transistor M4; The minus earth of current source I0; the positive pole of current source I0 connects the drain electrode of the 3rd PMOS field effect transistor M3; the source electrode of the 3rd PMOS field effect transistor M3 meets the output end vo ut of protected device; the grid of the 3rd PMOS field effect transistor M3 meets power supply Vin; the substrate of the 3rd PMOS field effect transistor M3 selects the end that connects of circuit output end Buck to link to each other with the substrate of protected device and maximum voltage; meet power supply Vin behind the source electrode of the 4th PMOS field effect transistor M4 and the substrate short circuit; the grid of the 4th PMOS field effect transistor M4 links to each other with the drain electrode of described the 3rd PMOS field effect transistor M3 and the end that connects of current source I0 positive pole, and the drain electrode of the 4th PMOS field effect transistor M4 connects the grid of protected device power tube M0.

The power tube M0 that protected device described in the utility model is protected power management chip.

It is to select the maximum of supply voltage Vin and protected power tube M0 output voltage V out as output Buck voltage that maximum voltage described in the utility model is selected the function of circuit, and the Buck voltage of output removes to control the substrate electric potential of protected power tube M0.In the normal situation about using of power management chip, supply voltage Vin is greater than protected power tube M0 output voltage V out, maximum voltage selects the output voltage Buck of circuit to equal supply voltage Vin, this moment protected power tube M0 source electrode to the parasitic diode D1 of substrate be in the short circuit state, the parasitic diode D2 of the substrate that drains is in cut-off state; In the situation of the rapid power down of power supply; protected power tube M0 output voltage V out is greater than supply voltage Vin; maximum voltage selects the output voltage Buck of circuit to equal protected power tube M0 output voltage V out, this moment protected power tube M0 source electrode to the parasitic diode D1 of substrate be in cut-off, the parasitic diode D2 of the substrate that drains is in the short circuit state.So no matter when, the parasitic diode that can both guarantee protected power tube M0 can forward conduction, and the protection power tube is not burnt.

For the power remove circuit, under the normal operating position of power management chip, supply voltage Vin is greater than the output voltage V out of protected power tube M0, the 3rd PMOS field effect transistor M3 is in cut-off state, the drain electrode output high level of the 3rd PMOS field effect transistor M3 removes to drive the grid of the 4th PMOS field effect transistor M4, the 4th PMOS field effect transistor M4 also is in cut-off state, and this moment, power-down protection circuit was inoperative; In the situation of the rapid power down of power supply; protected power tube M0 output voltage V out is greater than supply voltage Vin; when the output voltage V out of protected power tube M0 and the difference between the supply voltage Vin during greater than the threshold voltage vt h of the 3rd PMOS field effect transistor M3; the 3rd PMOS field effect transistor M3 is in conducting state; the drain electrode output low level of the 3rd PMOS field effect transistor M3 removes to drive the grid of the 4th PMOS field effect transistor M4; the 4th PMOS field effect transistor M4 also is in conducting state; and to the gate charges of protected power tube M0 until the grid of protected power tube M0 is pulled to supply voltage; thereby turn-off protected power tube M0, realize the function that power supply power-fail just turn-offs protected power tube M0.

Description of drawings

Fig. 1 is the power flow schematic diagram of conventional power source scheme;

Fig. 2 is that the maximum voltage in the utility model is selected the circuit diagram structure principle;

Fig. 3 is the utility model power supply power-fail recoil protective circuit structure principle chart.

Embodiment

Power supply power-fail recoil protective circuit, comprise a maximum voltage selection circuit and a power remove circuit, the substrate electric potential of circuit in order to provide a Buck voltage to remove to control protected device is provided for described maximum voltage, and described power remove circuit is in order to switch-off power pipe when the power supply power-fail;

Described maximum voltage selects circuit to be comprised of voltage comparator COMP1, inverter INV1, a PMOS field effect transistor M1 and the 2nd PMOS field effect transistor M2; The positive input termination power supply Vin of voltage comparator COMP1, the output end vo ut of the negative input termination protected device of voltage comparator COMP1, the input of the output termination inverter INV1 of voltage comparator COMP1, the grid of output termination the 2nd PMOS field effect transistor M2 of inverter INV1, the grid of the one PMOS field effect transistor M1 and described voltage comparator COMP1 output are connected with inverter INV1 input and are connect end and be connected, meet the substrate electric potential Buck of protected device behind the source electrode of the one PMOS field effect transistor M1 and the substrate short circuit, the drain electrode of the one PMOS field effect transistor M1 meets the output end vo ut of protected device, meet the substrate electric potential Bcuk of protected device behind the source electrode of the 2nd PMOS field effect transistor M2 and the substrate short circuit, the drain electrode of the 2nd PMOS field effect transistor M2 meets power supply Vin;

Described power remove circuit is comprised of current source I0, the 3rd PMOS field effect transistor M3 and the 4th PMOS field effect transistor M4; The minus earth of current source I0; the positive pole of current source I0 connects the drain electrode of the 3rd PMOS field effect transistor M3; the source electrode of the 3rd PMOS field effect transistor M3 meets the output end vo ut of protected device; the grid of the 3rd PMOS field effect transistor M3 meets power supply Vin; the substrate of the 3rd PMOS field effect transistor M3 selects the end that connects of circuit output end Buck to link to each other with the substrate of protected device and maximum voltage; meet power supply Vin behind the source electrode of the 4th PMOS field effect transistor M4 and the substrate short circuit; the grid of the 4th PMOS field effect transistor M4 links to each other with the drain electrode of described the 3rd PMOS field effect transistor M3 and the end that connects of current source I0 positive pole, and the drain electrode of the 4th PMOS field effect transistor M4 connects the grid of protected device power tube M0.

When the rapid power down of power supply, protected power tube M0 output voltage V out is greater than supply voltage Vin, maximum voltage selects the output voltage Buck of circuit to equal the output voltage V out of protected power tube M0, this moment, protected power tube M0 source electrode was in cut-off to the parasitic diode D1 of substrate, drain electrode is in the short circuit state to the parasitic diode D2 of substrate, does not have the phenomenon of protected power tube M0 parasitic diode conducting; Simultaneously; when the output voltage V out of protected power tube M0 and the difference between the supply voltage Vin during greater than the threshold voltage vt h of the 3rd PMOS field effect transistor M3; the 3rd PMOS field effect transistor M3 is in conducting state; the drain electrode output low level of the 3rd PMOS field effect transistor M3 removes to drive the grid of the 4th PMOS field effect transistor M4; the 4th PMOS field effect transistor M4 also is in conducting state; by the 4th PMOS field effect transistor M4 to the gate charges of protected power tube M0 until the grid of power tube M0 is pulled to supply voltage, thereby turn-off protected power tube M0.

Claims (2)

1. power supply power-fail recoil protective circuit, it is characterized in that comprising maximum voltage selection circuit and a power remove circuit, described maximum voltage selects circuit in order to providing a Buck voltage to remove to control the substrate electric potential of protected device, and described power remove circuit is in order to turn-off protected device when the power supply power-fail;

Described maximum voltage selects circuit to be comprised of voltage comparator COMP1, inverter INV1, a PMOS field effect transistor M1 and the 2nd PMOS field effect transistor M2; The positive input termination power supply Vin of voltage comparator COMP1, the output end vo ut of the negative input termination protected device of voltage comparator COMP1, the input of the output termination inverter INV1 of voltage comparator COMP1, the grid of output termination the 2nd PMOS field effect transistor M2 of inverter INV1, the grid of the one PMOS field effect transistor M1 and described voltage comparator COMP1 output are connected with inverter INV1 input and are connect end and be connected, meet the substrate electric potential Buck of protected device behind the source electrode of the one PMOS field effect transistor M1 and the substrate short circuit, the drain electrode of the one PMOS field effect transistor M1 meets the output end vo ut of protected device, meet the substrate electric potential Bcuk of protected device behind the source electrode of the 2nd PMOS field effect transistor M2 and the substrate short circuit, the drain electrode of the 2nd PMOS field effect transistor M2 meets power supply Vin;

Described power remove circuit is comprised of current source I0, the 3rd PMOS field effect transistor M3 and the 4th PMOS field effect transistor M4; The minus earth of current source I0; the positive pole of current source I0 connects the drain electrode of the 3rd PMOS field effect transistor M3; the source electrode of the 3rd PMOS field effect transistor M3 meets the output end vo ut of protected device; the grid of the 3rd PMOS field effect transistor M3 meets power supply Vin; the substrate of the 3rd PMOS field effect transistor M3 selects the end that connects of circuit output end Buck to link to each other with the substrate of protected device and maximum voltage; meet power supply Vin behind the source electrode of the 4th PMOS field effect transistor M4 and the substrate short circuit; the grid of the 4th PMOS field effect transistor M4 links to each other with the drain electrode of described the 3rd PMOS field effect transistor M3 and the end that connects of current source I0 positive pole, and the drain electrode of the 4th PMOS field effect transistor M4 connects the grid of protected device power tube M0.

2. circuit as claimed in claim 1 is characterized in that the power tube M0 that described protected device is protected power management chip.

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