CN202600591U - PXIe-based control chassis - Google Patents
PXIe-based control chassis Download PDFInfo
- Publication number
- CN202600591U CN202600591U CN 201120545649 CN201120545649U CN202600591U CN 202600591 U CN202600591 U CN 202600591U CN 201120545649 CN201120545649 CN 201120545649 CN 201120545649 U CN201120545649 U CN 201120545649U CN 202600591 U CN202600591 U CN 202600591U
- Authority
- CN
- China
- Prior art keywords
- circuit
- clock
- chip
- pci
- fan
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model relates to a PXIe-based control chassis, comprising a housing, and a power unit, a fan control panel and a rear panel disposed in the housing. The power unit supplies power to the fan control panel and rear panel; the fan control panel comprises a wind speed selection circuit, a temperature detection circuit and a fan speed control circuit; output ends of the wind speed selection circuit and the temperature detection circuit are connected with an input end of the fan speed control circuit; the fan speed control circuit is used for controlling the revolving speed of a fan; the rear panel comprises a clock management circuit and a signal route circuit, wherein the clock management circuit comprises a clock generating circuit, a 100MHz clock drive circuit, a 10M clock drive circuit, a 100MHz synchronous signal drive circuit, a 10MHz clock switching circuit, a 10MHz clock drive circuit and an FPGA and the signal route circuit comprises a PCI Express signal route circuit and PCI expander circuits. The PXIe-based control chassis enables a computer to analyze and store up test results and is suitable for situations requiring high collection speed and high performance.
Description
Technical field
The utility model relates to a kind of control cabinet based on PXIe.
Background technology
PCI Express (PCIe) is a kind of sata standard of main flow, and it is the third generation I/O interconnection technique that comes out in 2002.The standard interconnection technique people that PCIe has become the PC industry require growingly to conventional P CI architecture bandwidth and seamless transplanting, add the develop rapidly of silicon technology, have all promoted the widespread use of PCI Express.
The bus transfer bandwidth is up to the PXIe cabinet of 4GB/s, and it is interconnected mainly to provide a kind of bus, is used for realizing that desk-top computer or industrial computer directly control the PXIe functional cards.
PXI Express technology is the technology of the up-to-date introduction of PXI platform.PCI Express is integrated into the PXI standard, thereby Gbps has been promoted 45 times, bring up to 6GB/s from 132MB/s.Except existing timing of PXI and synchronizing function, PXI Express also provides additional timing and triggering bus, comprises 100MHz differential system clock, difference synchronizing signal etc.Through using differential clocks, PXI Express system has increased the noise resisting ability to the instrument clock, and can transmit the clock signal of higher frequency.Existing P XI Express cabinet is a core of setting up PXI Express system.
Summary of the invention
Based on PCI Express (PCIe) standard, the utility model provides a kind of control cabinet based on PXIe.
The technical solution of the utility model:
A kind of control cabinet based on PXIe, its special character is: comprise housing and be arranged on power supply unit, fan control board and the backboard in the housing, said power supply unit is given fan control board and backboard power supply,
Said fan control board comprises wind speed selection circuit, temperature sensing circuit and fan speed control circuit; Said wind speed selects the output terminal of circuit and temperature sensing circuit to be connected with the input end of fans degree control circuit; The rotating speed of the control fan of said fan control circuitry
Said backboard comprises Clock management circuit and signal routing circuit,
Said Clock management circuit comprises clock generation circuit, 100MHz clock driver circuit, 10M clock driver circuit, 100MHz synchronizing signal driving circuit, 10MHz clock switch circuit, 10MHz clock driver circuit and FPGA;
Said clock generation circuit is used to produce the differential clocks of 100MHz; The 100MHz clock driver circuit is used for providing the differential clocks of 100MHz to each groove position; 100MHz synchronizing signal driving circuit is used to export the 100MHz synchronizing signal; 100MHz synchronizing signal driving circuit is used for providing the synchronizing signal of 100MHz to each groove position; 10MHz clock automatic switch-over circuit is used for the clock signal according to priority automatic switchover generation 10MHz, and the 10MHz clock driver circuit is used to the clock signal that each groove position provides 10MHz;
Said signal routing circuit comprises PCI Express signal routing circuit and PCI expanded circuit, and said signal routing circuit comprises a PCI Express expanded circuit, the 2nd PCI Express expanded circuit and the 3rd PCI Express and PCI expanded circuit,
A said PCI Express expanded circuit comprises an EEPROM interface, first alteration switch, first reference clock, a JTAG mouth, a PCI Express interface; Said first alteration switch exports first reference clock, a JTAG mouth and an EEPROM interface respectively to, and a said JTAG mouth exports a PCI Express interface to;
Said the 2nd PCI Express expanded circuit comprises the 2nd EEPROM interface, second alteration switch, second reference clock, the 2nd JTAG mouth, the 2nd PCI Express interface; Said second alteration switch exports second reference clock, the 2nd JTAG mouth and the 2nd EEPROM interface respectively to, and said the 2nd JTAG mouth exports the 2nd PCI Express interface to;
Said the 3rd PCI Express and PCI expanded circuit comprise the 3rd EEPROM interface, the 3rd alteration switch, the 3rd reference clock, the 3rd JTAG mouth, the 3rd PCI Express interface, PCI expansion, configuration circuit and pci interface; Said the 3rd alteration switch exports the 3rd reference clock, the 3rd JTAG mouth and the 3rd EEPROM interface respectively to; Said the 3rd JTAG mouth exports the 3rd PCI Express interface and PCI expansion to; Said PCI expansion exports pci interface to, and said configuration circuit inputs to the PCI expansion.
The said fans control panel comprises that it is fan speed SS (SW1) that wind speed is selected circuit, and the cautious circuit of said temperature comprises thermo-sensitive resistor, the 3rd interface (JP3), first bleeder circuit,
Said thermo-sensitive resistor is inserted in the 3rd interface (JP3), and the output terminal of said the 3rd interface (JP3) is connected with the input end of bleeder circuit, said bleeder circuit output terminal output sense signal;
Said fan speed control circuit comprises the first fan control chip (U101), the second fan control chip (U102), first metal-oxide-semiconductor (Q1) that is connected with first fan control chip (U101) output terminal and second metal-oxide-semiconductor (Q2) that is connected with second fan control chip (U102) output terminal; The control signal of said fan speed SS (SW1) exports the first fan control chip (U101) and the second fan control chip (U102) to, and said sense signal is exported to the first fan control chip (U101) and the second fan control chip (U102) simultaneously; The said first fan control chip U101 is inserted into the fan in first interface (JP1) through control first metal-oxide-semiconductor (Q1) control, and the said second fan control chip (U102) is inserted into the fan in second interface (JP1) through control second metal-oxide-semiconductor (Q2) control.
Above-mentioned clock generation circuit comprises voltage controlled oscillator, the first resistor network circuit, clock synchronizer (U2) and low-pass filter; Said voltage controlled oscillator is connected with clock synchronizer (U2) through resistor network, and said clock synchronizer U2 feeds back to voltage controlled oscillator through low-pass filter.
Above-mentioned 100MHz clock driver circuit comprises the second resistor network circuit and first clock driver chip (U3); The input termination differential clock signal of the said second resistor network circuit; The output termination clock driver chip (U3) of the said second resistor network circuit; Said clock driver chip (U3) is exported to FPGA, and produces PXIe_CLK2～PXIe_CLK8 differential clock signal.
Above-mentioned FPGA comprises the 3rd resistor network circuit and fpga chip (U7); The input end of said the 3rd resistor network circuit is connected with first clock driver chip (U3); The output terminal of said the 3rd resistor network circuit is connected with the input end of fpga chip U7, and the output terminal output synchronizing signal of said fpga chip (U7) is given 100MHz synchronizing signal driving circuit.
Above-mentioned 100MHz synchronizing signal driving circuit comprises the 4th resistor network circuit and second clock chip for driving (U1); The input end of said the 4th resistor network circuit is connected with fpga chip (U7); The output terminal of said the 4th resistor network circuit is connected with the input end of second clock chip for driving (U1), and the output terminal of second clock chip for driving (U1) produces PXIe_SYNC100_2～PXIe_SYNC100_8 difference synchronizing signal.
The 10MHz clock driver circuit comprises the 3rd clock driver chip (U17); The input termination 10MHz clock automatic switch-over circuit of said the 3rd clock driver chip (U17), the output terminal of said the 3rd clock driver chip (U17) is connected with the input end of first clock driver chip (U3).
Above-mentioned PCI expanded circuit comprises the configuring chip (U21) of pci signal extended chip U19 and extended chip; Said pci signal extended chip comprises (U19A, U19B, U19C, U19D, U19E), and the configuring chip of extended chip (U21) is connected with the pci signal extended chip.
The advantage that the utility model had:
1, the utility model provides signal interconnected mainly for PXIe functional cards and zero groove, makes things convenient for the user in testing laboratory or other working environments, measurand to be tested.The utility model designs based on PCIe Gen2; Maximum transmission bandwidth is up to 4GB/s; Help that power that the user relies on computing machine is analyzed test result and operation such as storage; Can be applicable to need to gather a plurality of data, and high to acquisition rate and performance requirement, interchannel needs synchronously, occasion regularly.
2, the utility model adopts two generation PCIe switch chips, makes that the bandwidth of cabinet is higher, and time delay is littler;
3, the utility model adopts differential clocks, makes the antijamming capability of clock strengthen greatly;
4, the utility model adopts clock synchronizer to carry out making that the signal Synchronization property of a plurality of clocks is better synchronously.
Description of drawings
Fig. 1 the utility model general function structural representation.
Fig. 2 Clock management block diagram.
Fig. 3 signal route block diagram.
Fig. 4 fan control board circuit theory diagrams.
Figure 51 00MHz clock generation circuit schematic diagram.
Figure 61 00MHz clock driver circuit schematic diagram.
Fig. 7 FPGA circuit theory diagrams.
Figure 81 00MHz synchronizing signal driving circuit schematic diagram.
Figure 91 0MHz clock driver circuit schematic diagram.
One of Figure 10 PCIe alteration switch and configuration circuit schematic diagram thereof.
Two of Figure 11 PCIe alteration switch and configuration circuit schematic diagram thereof.
Figure 12 PCIe groove position catenation principle figure.
One of Figure 13 PCI expanded circuit schematic diagram.
Two of Figure 14 PCI expanded circuit schematic diagram.
Embodiment
As shown in Figure 1, the PXIe cabinet comprises the backboard that provides signal interconnected, the fan control board of control housing temperature and power supply and the housing that provides cabinet, integrated circuit board to supply power.Fan control board is made up of following part: it comprises wind speed selection circuit, temperature sensing circuit, fan speed control circuit.Backboard is made up of following part: it comprises that Clock management circuit, signal routing circuit, power conversion and filtering circuit three parts form.
As shown in Figure 2, Clock management partly comprises: by the 100MHz clock generation circuit that voltage controlled oscillator and clock synchronizer U2 form, synchronous clock driving circuit; The 100MHz clock driver circuit; Automatic switch-over circuit, 10MHz clock driver circuit, outside shaping circuit.
Signal routing circuit as shown in Figure 3 comprises that PCI Express expansion 1, PCI Express expansion 2 and PCI Express and PCI expand three parts.PCI Express expansion is realized that by three alteration switches to guarantee that signal can not block up match, the downstream port of every alteration switch can be connected to 2 PCI Express interfaces.
As shown in Figure 4, this circuit is the fan control board schematic diagram.SW1 is the fan speed SS in this circuit, can select automatically, closes and three kinds of functions of high speed.Thermo-sensitive resistor inserts JP3, and R1, and " sense " signal that the R3 dividing potential drop produces is input to fan control chip U101; The input control end of U102; U101, the output signal of U102 pass through conducting and the shutoff of control metal-oxide-semiconductor Q1, Q2, thereby can control the rotating speed that is inserted into the fan among JP2, the JP3.
As shown in Figure 5, this circuit is the realization schematic diagram of the 100MHz clock generation circuit part shown in Fig. 2.The major function of this circuit is the differential clocks that produces 100MHz.Y1 is a voltage controlled oscillator among the figure, and the clock that voltage controlled oscillator produces is through the first resistor network circuit R7, R11, and R12 is input in the pin 42,43 of U3 after the R13 coupling, and carries out synchronously with REF_IN, clock Y0, the Y0B of generation 100MHz.Wherein 31 pins of U3 are exported signal CP_OUT through R14, R15, and C40, C41 feeds back to behind the low-pass filter that C42 forms in the voltage controlled oscillator and exports with the frequency of adjustment Y1.
As shown in Figure 6, this circuit is a 100MHz clock driver circuit schematic diagram.The major function of this circuit is the differential clocks that 100MHz is provided to each groove position.100MHz differential clocks Y0, Y0B are through the second resistor network circuit R8 among this figure; R9; R10; Be input to after the R397 coupling in the pin two 8, pin two of clock driver chip U4, then at U4 output signal PXIe_CLK100_2+～PXIe_CLK100_8+, PXIe_CLK100_2-～PXIe_CLK100_8-, PXIe_CLK100_FPGA+, PXIe_CLK100_FPGA-.
As shown in Figure 7, U4 output signal PXIe_CLK100_FPGA+, PXIe_CLK100_FPGA-.Be input among the fpga chip U7, handle the back through FPGA output 100MHz synchronizing signal PXIe_SYNC100_FPGA+, PXIe_SYNC100_FPGA-through FPGA, U4 also provides the management that resets, the clock automatic switching function simultaneously.
As shown in Figure 8, this circuit is a 100MHz synchronizing signal driving circuit schematic diagram.The major function of this circuit is the synchronizing signal that 100MHz is provided to each groove position.The 100MHz synchronizing signal PXIe_SYNC100_FPGA+ that is exported by U7 among this figure, PXIe_SYNC100_FPGA-are through the 4th resistor network R2; R3; R4; Be input to after the R5 coupling in the pin two 8, pin two of U1, then U1 output signal PXIe_SYNC100_2+～PXIe_SYNC100_8+, PXIe_SYNC1002_2～PXIe_SYNC100_8-.
As shown in Figure 9, this circuit is a 10MHz clock driver circuit schematic diagram.This circuit mainly is the clock signal that 10MHz is provided for each groove position.The 10MHz signal CLK10 that exports among Fig. 9 is input among the U17, and U17 produces output signal PXI_CLK10_1～PXI_CLK10_8, REF_IN, CLK10_OUT.REF_IN is used as the input signal of U3 in the circuit shown in Figure 5.
Like Figure 10 and shown in Figure 11, this circuit is a PCIe alteration switch schematic diagram.Shown in figure 11, U29A mainly is that a PXIe of zero groove zero groove X4 signal extension is PXIe expansion X4 signal 1, PXIe expansion X4 signal 2 and PCI spread signal.PXIe expansion X4 signal 1, PXIe expansion X4 signal 2 are delivered on the connector of groove position shown in Figure 14.The PCI spread signal is delivered among the U19A shown in Figure 13.Block isolating circuit 1, block isolating circuit 2, the block isolating circuit of being made up of a plurality of electric capacity 3 is used to realize the isolation of signal.Shown in figure 12, comprise the loading configuration circuit that powers on of the PCIe alteration switch chip U29 that forms by U28 in this circuit, also comprised the circuit that is provided with simultaneously to the various function pins of PCIe alteration switch chip U29.
Like Figure 12 and shown in Figure 13, this circuit is a PCI expanded circuit schematic diagram.The major function of this circuit is that the PCIe conversion of signals that Figure 11 sends is become pci signal.
Shown in figure 14; U19A is exactly the part of PCIe to the pci signal extended chip among the figure; It can pass PCIe signal XIO2001_Rn0, the XIO2001_Rp0 that comes with U29 among Figure 11; XIO2001_Tn0, XIO2001_Tp0 convert pci signal to, comprise AD [0]～AD [31], REQ0～REQ3 and other pci signals.U19B, U19C, U19D are other three parts of pci signal extended chip, and the circuit that U21 and R94, R100 form is the configuration circuit of U19.
Claims (8)
1. the control cabinet based on PXIe comprises housing and is arranged on power supply unit, fan control board and the backboard in the housing, and said power supply unit is given fan control board and backboard power supply,
Said fan control board comprises wind speed selection circuit, temperature sensing circuit and fan speed control circuit; Said wind speed selects the output terminal of circuit and temperature sensing circuit to be connected with the input end of fans degree control circuit; The rotating speed of the control fan of said fan control circuitry
Said backboard comprises Clock management circuit and signal routing circuit,
Said Clock management circuit comprises clock generation circuit, 100MHz clock driver circuit, 10M clock driver circuit, 100MHz synchronizing signal driving circuit, 10MHz clock switch circuit, 10MHz clock driver circuit and FPGA;
Said clock generation circuit is used to produce the differential clocks of 100MHz; The 100MHz clock driver circuit is used for providing the differential clocks of 100MHz to each groove position; 100MHz synchronizing signal driving circuit is used to export the 100MHz synchronizing signal; 100MHz synchronizing signal driving circuit is used for providing the synchronizing signal of 100MHz to each groove position; 10MHz clock automatic switch-over circuit is used for the clock signal according to priority automatic switchover generation 10MHz, and the 10MHz clock driver circuit is used to the clock signal that each groove position provides 10MHz;
Said signal routing circuit comprises PCI Express signal routing circuit and PCI expanded circuit, and said signal routing circuit comprises a PCI Express expanded circuit, the 2nd PCI Express expanded circuit and the 3rd PCI Express and PCI expanded circuit,
A said PCI Express expanded circuit comprises an EEPROM interface, first alteration switch, first reference clock, a JTAG mouth, a PCI Express interface; Said first alteration switch exports first reference clock, a JTAG mouth and an EEPROM interface respectively to, and a said JTAG mouth exports a PCI Express interface to;
Said the 2nd PCI Express expanded circuit comprises the 2nd EEPROM interface, second alteration switch, second reference clock, the 2nd JTAG mouth, the 2nd PCI Express interface; Said second alteration switch exports second reference clock, the 2nd JTAG mouth and the 2nd EEPROM interface respectively to, and said the 2nd JTAG mouth exports the 2nd PCI Express interface to;
Said the 3rd PCI Express and PCI expanded circuit comprise the 3rd EEPROM interface, the 3rd alteration switch, the 3rd reference clock, the 3rd JTAG mouth, the 3rd PCI Express interface, PCI expansion, configuration circuit and pci interface; Said the 3rd alteration switch exports the 3rd reference clock, the 3rd JTAG mouth and the 3rd EEPROM interface respectively to; Said the 3rd JTAG mouth exports the 3rd PCI Express interface and PCI expansion to; Said PCI expansion exports pci interface to, and said configuration circuit inputs to the PCI expansion.
2. the control cabinet based on PXIe according to claim 1; It is characterized in that: said fan control board comprises that it is fan speed SS (SW1) that wind speed is selected circuit; The cautious circuit of said temperature comprises thermo-sensitive resistor, the 3rd interface (JP3), first bleeder circuit
Said thermo-sensitive resistor is inserted in the 3rd interface (JP3), and the output terminal of said the 3rd interface (JP3) is connected with the input end of bleeder circuit, said bleeder circuit output terminal output sense signal;
Said fan speed control circuit comprises the first fan control chip (U101), the second fan control chip (U102), first metal-oxide-semiconductor (Q1) that is connected with first fan control chip (U101) output terminal and second metal-oxide-semiconductor (Q2) that is connected with second fan control chip (U102) output terminal; The control signal of said fan speed SS (SW1) exports the first fan control chip (U101) and the second fan control chip (U102) to, and said sense signal is exported to the first fan control chip (U101) and the second fan control chip (U102) simultaneously; The said first fan control chip U101 is inserted into the fan in first interface (JP1) through control first metal-oxide-semiconductor (Q1) control, and the said second fan control chip (U102) is inserted into the fan in second interface (JP1) through control second metal-oxide-semiconductor (Q2) control.
3. the control cabinet based on PXIe according to claim 1 and 2; It is characterized in that: said clock generation circuit comprises voltage controlled oscillator, the first resistor network circuit, clock synchronizer (U2) and low-pass filter; Said voltage controlled oscillator is connected with clock synchronizer (U2) through resistor network, and said clock synchronizer U2 feeds back to voltage controlled oscillator through low-pass filter.
4. the control cabinet based on PXIe according to claim 3; It is characterized in that: said 100MHz clock driver circuit comprises the second resistor network circuit and first clock driver chip (U3); The input termination differential clock signal of the said second resistor network circuit; The output termination clock driver chip (U3) of the said second resistor network circuit, said clock driver chip (U3) is exported to FPGA, and produces PXIe_CLK2～PXIe_CLK8 differential clock signal.
5. the control cabinet based on PXIe according to claim 4; It is characterized in that: said FPGA comprises the 3rd resistor network circuit and fpga chip (U7); The input end of said the 3rd resistor network circuit is connected with first clock driver chip (U3); The output terminal of said the 3rd resistor network circuit is connected with the input end of fpga chip U7, and the output terminal output synchronizing signal of said fpga chip (U7) is given 100MHz synchronizing signal driving circuit.
6. the control cabinet based on PXIe according to claim 5; It is characterized in that: said 100MHz synchronizing signal driving circuit comprises the 4th resistor network circuit and second clock chip for driving (U1); The input end of said the 4th resistor network circuit is connected with fpga chip (U7); The output terminal of said the 4th resistor network circuit is connected with the input end of second clock chip for driving (U1), and the output terminal of second clock chip for driving (U1) produces PXIe_SYNC100_2～PXIe_SYNC100_8 difference synchronizing signal.
7. the control cabinet based on PXIe according to claim 6; It is characterized in that: the 10MHz clock driver circuit comprises the 3rd clock driver chip (U17); The input termination 10MHz clock automatic switch-over circuit of said the 3rd clock driver chip (U17), the output terminal of said the 3rd clock driver chip (U17) is connected with the input end of first clock driver chip (U3).
8. the control cabinet based on PXIe according to claim 7 is characterized in that:
Said PCI expanded circuit comprises the configuring chip (U21) of pci signal extended chip U19 and extended chip; Said pci signal extended chip comprises (U19A, U19B, U19C, U19D, U19E), and the configuring chip of extended chip (U21) is connected with the pci signal extended chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120545649 CN202600591U (en) | 2011-12-20 | 2011-12-20 | PXIe-based control chassis |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120545649 CN202600591U (en) | 2011-12-20 | 2011-12-20 | PXIe-based control chassis |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202600591U true CN202600591U (en) | 2012-12-12 |
Family
ID=47318121
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201120545649 Expired - Fee Related CN202600591U (en) | 2011-12-20 | 2011-12-20 | PXIe-based control chassis |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202600591U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105634635A (en) * | 2014-11-07 | 2016-06-01 | 杭州华为数字技术有限公司 | Real-time clock (RTC) sharing method, device and system |
| US9723727B2 (en) | 2015-02-05 | 2017-08-01 | Keysight Technologies, Inc. | Modular electronic instrumentation chassis with integrated high performance reference clock and associated methods |
-
2011
- 2011-12-20 CN CN 201120545649 patent/CN202600591U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105634635A (en) * | 2014-11-07 | 2016-06-01 | 杭州华为数字技术有限公司 | Real-time clock (RTC) sharing method, device and system |
| CN105634635B (en) * | 2014-11-07 | 2019-02-26 | 杭州华为数字技术有限公司 | A kind of methods, devices and systems of shared RTC |
| US9723727B2 (en) | 2015-02-05 | 2017-08-01 | Keysight Technologies, Inc. | Modular electronic instrumentation chassis with integrated high performance reference clock and associated methods |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102609057B (en) | Control machine box based on PXIe | |
| CN109613491B (en) | High-speed signal acquisition, storage and playback system based on FPGA | |
| CN104915303B (en) | High speed digital I based on PXIe buses/O systems | |
| CN105573949A (en) | Acquiring and processing circuit with JESD204B interface of VPX architecture | |
| CN102023956A (en) | Serial peripheral slave device interface structure in integrated circuit chip and data reading and writing method | |
| CN102725708A (en) | Device configured to switch a clock speed for multiple links running at different clock speeds and method for switching the clock speed | |
| CN103684375B (en) | A kind of clock division switching circuit and clock chip | |
| US6265930B1 (en) | Glitch free clock multiplexer circuit | |
| CN202600591U (en) | PXIe-based control chassis | |
| CN109032548A (en) | It is a kind of that switching architecture is locally displayed based on Loongson server | |
| CN201465109U (en) | High-speed data acquisition card based on optical fibers and PCI-E | |
| CN101183347A (en) | Bridge circuit of self-adapting velocity matching bus | |
| CN201984475U (en) | USB automatic identification multifunction converter | |
| CN107370651B (en) | Communication method between SPI slave machines | |
| CN201440266U (en) | Integrative PCL bus host computer sharing device | |
| CN103226531A (en) | Dual-port peripheral configuration interface circuit | |
| CN213582152U (en) | PCIE signal bit width automatic switching device of desktop and server system | |
| CN203102268U (en) | Control bus with trigger synchronization function and clock synchronization function | |
| CN201909847U (en) | Double-channel digital signal acquisition device on basis of VXI (VME <Virtual Machine Enviroment> bus Extension for Instrumentation) interface | |
| CN107329863A (en) | A kind of measuring instrument general hardware platform based on COMe | |
| CN102521180A (en) | Multi-channel real-time direct reading memory structure | |
| CN203443598U (en) | Star-shaped trigger backboard applied to PXI test platform | |
| CN205829897U (en) | Support the multi-channel video compression processing module of various video pattern of the input | |
| CN203482180U (en) | Communication interface synchronization circuit | |
| CN210109798U (en) | DSP and PC communication system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121212 Termination date: 20151220 |
|
| EXPY | Termination of patent right or utility model |