CN202473930U - Insulated gate bipolar transistor (IGBT) with low turn-on saturation voltage drop - Google Patents
Insulated gate bipolar transistor (IGBT) with low turn-on saturation voltage drop Download PDFInfo
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Abstract
The utility model relates to an insulated gate bipolar transistor (IGBT) with low turn-on saturation voltage drop. A second-conduction type layer is arranged in an active area, and is divided into a plurality of first second-conduction type layer areas and second second-conduction type layer areas by conducting polycrystalline silicon and isolated gate dielectric layers. Insulating dielectric layers cover the first main surface of a semiconductor substrate. Symmetrically distributed first-conduction type injection areas are arranged in the first second-conduction type layer areas, and contact corresponding insulated gate dielectric layers. Emitter contact holes are formed above the first second-conduction type layer areas, penetrate through the insulating dielectric layers, and are extended onto the first main surface. Emitter metal layers are filled in the emitter contact holes, cover the insulating dielectric layers, and form ohmic contact with the first second-conduction type layer areas. The IGBT has low saturation voltage drop Vcesat and high impact resistance.
Description
Technical field
The utility model relates to a kind of IGBT device, and especially a kind of IGBT with low conducting saturation voltage drop belongs to the technical field of power semiconductor.
Background technology
The present main devices structure type of IGBT (Insulated Gate Bipolar Transistor) comprises: punch IGBT (Punch Through IGBT; Abbreviate PT-IGBT as), non-punch through IGBT (Non Punch Through IGBT; Abbreviate NPT-IGBT as) and a cut-off type IGBT (Field Stop IGBT; Abbreviate FS-IGBT as), the primary structure difference between the three is that different backside collector structures and different drift semiconductor district thickness are set.
PT-IGBT is more early stage IGBT structure; Owing to adopted thicker backside collector structure; Therefore it is crossed hyperbaric hole injection current and is unfavorable for the switch power loss of device and the temperature characterisitic of conducting saturation voltage drop Vcesat, and it has used epitaxial wafer materials and carrier lifetime control technology also to increase product cost greatly; NPT-IGBT has adopted thin backside collector structure and thicker drift region; Though the switch power loss of device is improved; Vcesat has also obtained positive temperature characterisitic; But the space that device Vcesat descends has been limited in thicker drift region, thereby has increased the power loss of IGBT, and is as depicted in figs. 1 and 2.
Along with the progress of semiconductor film machining process, FS-IGBT has adopted thinner drift region thickness, so the Vcesat of its conducting saturation voltage drop Vcesat contrast PT-IGBT and NPT-IGBT has obtained tangible decline; IGBT with 1200V25A is an example; The semiconductor crystal wafer thickness of NPT-IGBT is approximately 180um, and FS-IGBT only needs 120um, and thickness has reduced by 1/3rd; Its Vcesat also is reduced to 1.6V from 2.5V, the range of decrease nearly 40%.Yet; The price of wafer processes equipment, process complexity and fragment rate are along with the increase of semiconductor die size and the attenuation of semiconductor crystal wafer thickness all can significantly increase; Become the important bottleneck that the IGBT product further improves cost performance, this also is that IGBT slowly can't (for example 12 inches) promote the major reason of producing on bigger wafer size.
Summary of the invention
The purpose of the utility model is to overcome the deficiency that exists in the prior art, and a kind of IGBT with low conducting saturation voltage drop is provided, and it has lower saturation voltage drop Vcesat and higher impact resistance.
The technical scheme that provides according to the utility model; A kind of IGBT with low conducting saturation voltage drop; On the top plan view of said IGBT device; Comprise the active area and the terminal protection district that are positioned on the semiconductor substrate, said active area is positioned at the central area of semiconductor substrate, and the terminal protection district is around being surrounded by the source region; On the cross section of said IGBT device, said semiconductor substrate has two relative interareas, and said interarea comprises first interarea and second interarea, comprises the first conduction type drift region between first interarea of semiconductor substrate and second interarea; Comprise the conductive polycrystalline silicon that is connected in parallel in the said active area; Its innovation is:
On the cross section of said IGBT device; In the first corresponding conduction type drift region of active area, second conductive type layer is set; Said second conductive type layer is separated into the some second conductive type layer first areas and the second conductive type layer second area through conductive polycrystalline silicon and insulated gate dielectric layer; The second conductive type layer first area and the second conductive type layer second area replace rule each other in the first conduction type drift region arranges, and through conductive polycrystalline silicon and insulated gate dielectric layer interval;
On the cross section of said IGBT device, be coated with insulating medium layer on first interarea of semiconductor substrate, and said insulating medium layer covers on the corresponding conductive polycrystalline silicon; The first conduction type injection region of symmetrical distribution is set in the second conductive type layer first area; The said first conduction type injection region contacts with the corresponding insulation gate dielectric layer; And top, the second conductive type layer first area is provided with the emitter contact hole, and said emitter contact hole connects insulating medium layer and extends on first interarea; Be filled with the emitter metal layer in the emitter contact hole, and said emitter metal layer is covered on the insulating medium layer emitter metal layer and the second conductive type layer first area ohmic contact.
On the cross section of said IGBT device, the second conductive type layer first area has first width, and the second conductive type layer second area has second width, and the second conductive type layer first area and the second conductive type layer second area are same manufacturing layer.
On the cross section of said IGBT device, comprise the first conduction type field cut-off region in the said first conduction type drift region, the said first conduction type field cut-off region is positioned at the bottom of the first conduction type drift region, and near second interarea of semiconductor substrate; The first conductive type impurity concentration of the first conduction type field cut-off region is not less than the first conductive type impurity concentration of the first conduction type drift region.
On the cross section of said IGBT device; In the said first conduction type drift region, below the corresponding first conduction type field cut-off region the second conduction type injection region is set; The second conduction type injection region contacts with the first conduction type field cut-off region, and second conduction type injection region correspondence is second interarea with contacted another surface of the first conduction type field cut-off region; Be coated with the collector electrode metal layer on second interarea of semiconductor substrate, the said collector electrode metal layer and the second conduction type injection region ohmic contact.
On the cross section of said IGBT device, said active area adopts groove cellular structure, and said cellular groove is positioned at second conductive type layer, and the degree of depth stretches in the first conduction type drift region of second conductive type layer below; The insulated gate oxide layer growth also is covered in the inwall and the lower surface of cellular groove, and conductive polycrystalline silicon is filled in growth to be had in the cellular groove of insulated gate oxide layer; Conductive polycrystalline silicon in cellular groove and the cellular groove is separated into the second conductive type layer first area and the second conductive type layer second area with second conductive type layer, and the first conductive type layer injection region in the second conductive type layer first area contacts with corresponding cellular groove one side sidewall; Insulating medium layer covers the notch of cellular groove, and insulated gate oxide layer and conductive polycrystalline silicon in the cellular groove form groove-shaped cellular structure.
On the cross section of said IGBT device, said active area adopts plane cellular structure; Said conductive polycrystalline silicon is positioned on first interarea; Growth has the insulated gate oxide layer between the conductive polycrystalline silicon and first interarea; The second conductive type layer first area, the second conductive type layer second area of said conductive polycrystalline silicon and conductive polycrystalline silicon both sides side-lower partly overlap; And overlap mutually the first conduction type injection region in the second conductive type layer first area that conductive polycrystalline silicon and part overlap; Conductive polycrystalline silicon is covered by the insulating medium layer of top parcel, and the insulated gate oxide layer of first interarea top and conductive polycrystalline silicon constitute plane cellular structure.
Said " first conduction type " and " second conduction type " are among both, and for N type IGBT device, first conduction type refers to the N type, and second conduction type is the P type; For P type IGBT device, the type of first conduction type and the second conduction type indication is just in time opposite with N type IGBT device.
The advantage of the utility model:
1, the utility model is provided with the second conductive type layer second area at said active area; Said second conductive type layer second area top is coated with insulating medium layer; Said insulating medium layer top is coated with the emitter metal layer; Be separated with the first conduction type drift region between between the second conductive type layer second area and the second conductive type layer first area, therefore, the said second conductive type layer second area is the setting (floating) of floating.When the IGBT forward conduction is worked; Injecting into by the second conduction type injection region at the IGBT semiconductor substrate back side, the hole of the first conduction type drift region can accumulate below the second conductive type layer second area; Thereby form conductivity modulation effect in this zone; Greatly reduce this regional resistivity, therefore, obviously improved the conducting saturation voltage drop Vcesat of device.
2, when said IGBT forward conduction; Can form conducting channel in the said second conductive type layer first area; Then can not form conducting channel in the second conductive type layer second area; Therefore, the raceway groove quantity in the more common IGBT device active region of raceway groove quantity in the device active region has obvious minimizing, and the saturation current of device also can obviously reduce; Thereby the short circuit current that has improved device bears tolerance; Strengthened the impact resistance of device, and the conductivity modulation effect that the part that the conducting saturation voltage drop of device increases because raceway groove quantity reduces also can be brought by the holoe carrier increase of second conductive type layer second area below remedies far away, so can't influence the final conducting saturation voltage drop of device.
3, the utility model is provided with the first conduction type field cut-off region below the said first conduction type drift region; When the doping content of the said first conduction type field cut-off region during apparently higher than the first conduction type drift region; And simultaneously said semiconductor substrate is thinned to the thickness of appointment; Said thickness makes device when withstand voltage work, and the depletion region of device can't stop in the first conduction type drift region fully, but can in the said first conduction type field cut-off region, stop and possess certain surplus fully; So; The thickness of the semiconductor substrate of device just can control to the thinnest according to actual reduction process ability, thereby when guaranteeing the device withstand voltage requirement, has further reduced the conducting saturation voltage drop.
In sum; In conjunction with two kinds of methods that reduce the break-over of device saturation voltage drop, guaranteeing that the device withstand voltage ability is constant, increase under the prerequisite of device impact resistance; The conducting saturation voltage drop of device can maximizedly improve; And the related technology manufacturing process of the utility model need not increase any manufacturing cost, and is simple and easy to do, is suitable for large batch of production.
Description of drawings
Fig. 1～Fig. 2 is the cross-sectional view of existing NPT type IGBT, wherein:
Fig. 1 is the profile of groove-shaped IGBT
Fig. 2 is the profile of plane IGBT
Fig. 3～Fig. 4 is the cross-sectional view of the utility model IGBT, wherein:
Fig. 3 is the profile of groove-shaped IGBT
Fig. 4 is the profile of plane IGBT
Fig. 5 is the utility model IGBT schematic top plan view.
Fig. 6 is the profile of A-A among Fig. 5.
Fig. 7 is the profile of B-B among Fig. 5.
Fig. 8-Figure 18 is the utility model IGBT device practical implementation processing step profile, wherein:
Fig. 8 is the profile of the utility model semiconductor substrate.
Fig. 9 is the profile after forming the cellular groove on first interarea of semiconductor substrate.
Figure 10 is the profile behind the filled conductive polysilicon in the cellular groove.
Figure 11 is the profile behind formation P trap layer first area and the P trap layer second area.
Figure 12 is the profile behind the formation N type injection region in P trap layer first area.
Figure 13 is the profile behind deposit insulating medium layer on first interarea.
Figure 14 is the profile after forming the emitter contact hole directly over the P trap layer first area.
Figure 15 is the profile behind the filling emitter metal layer in the emitter contact hole.
Figure 16 is the profile after forming N type field cut-off region below the N type drift region.
Figure 17 is the profile behind the formation P type injection region below the cut-off region of N type field.
Figure 18 is the profile after forming the collector electrode metal layer on second interarea.
Figure 19 is the current trend sketch map of the utility model example I GBT device when forward conduction.
Figure 20 adopts the utility model mechanism and the Vcesat measured value of the IGBT of a 1200V25A that adopts other two kinds of common structures to make to compare.
Figure 21 is the Electric Field Distribution sketch map of the utility model example I GBT device when withstand voltage work.
Description of reference numerals: 1-N type drift region; 2-P trap layer; 3-P type injection region; 4-collector electrode metal layer; 5-emitter metal layer; The 6-insulating medium layer; 7-cellular groove; 8-insulated gate oxide layer; The 9-conductive polycrystalline silicon; The 10-N+ injection region; 11-P trap layer first area; 12-P trap layer second area; 13-emitter contact hole; 14-N type field cut-off region; The 15-active area; 16-terminal protection district; The 17-semiconductor substrate; 18-first interarea; 19-second interarea; The 20-hard mask layer; 21-injects barrier bed; The 22-conducting channel; The 23-electronic current; The 24-hole current; The 25-collector terminal; 26-gate terminal and 27-emitter terminal.
Embodiment
Below in conjunction with concrete accompanying drawing and embodiment the utility model is described further.
Like Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7 and shown in Figure 180: the utility model is an example with N type IGBT, and the structure and the corresponding work principle of the utility model is described.
As shown in Figure 5, on the vertical view of said IGBT device, said device includes source region 15 and around the terminal protection district 16 that is surrounded by source region 15; Said active area 15 comprises the conductive polycrystalline silicon 9 that parallel strip is provided with; Said conductive polycrystalline silicon 9 is separated into P trap layer first area 11 and P trap layer second area 12 with the P trap layer 2 in the active area 15; Said P trap layer first area 11 replaces rule each other with P trap layer second area 12 and arranges; Be provided with N+ injection region 10 in the said P trap layer first area 11; And above P trap layer first area 11, be provided with emitter contact hole 13, said emitter contact hole 13 connects insulating medium layer 6, and extends on first interarea 18 of semiconductor substrate 17 from insulating medium layer 6.
Like Fig. 3 and shown in Figure 6,, adopt the sketch map of groove structure for the active area 15 of IGBT device along on the cross section of A-A among Fig. 5.The N type semiconductor substrate 17 of said IGBT device comprises two interareas, and the upper surface of said semiconductor substrate 17 is first interarea 18, and lower surface is second interarea 19; Include N type drift region 1 between said first interarea 18 and second interarea 19, above said N type drift region 1, be provided with P trap layer 2 and cellular groove 7, said cellular groove 7 is extended by first interarea 18 vertically downward; The degree of depth is deeply to P trap layer 2 below; Said cellular groove 7 is divided into a plurality of P trap layer first area of alternately arranging each other 11 and P trap layer second area 12 with P trap layer 2, and said P trap layer first area 11 has the first width m, and P trap layer second area 12 has the second width n; Usually; The first width m equates that with the second width n P trap layer first area 11 is same manufacturing layer with P trap layer second area 12, and the degree of depth in N type drift region 1 is consistent.
Said cellular groove 7 inner wall surface growth has insulated gate oxide layer 8; Deposit is filled with conductive polycrystalline silicon 9 in the cellular groove 7; Above said P trap layer first area 11, be provided with symmetrical N type injection region 10, said N type injection region 10 contacts with cellular groove 7 lateral walls; Be coated with insulating medium layer 5 on first interarea of P trap layer second area 12 correspondences; Said insulating medium layer 5 covers cellular groove 7 notches simultaneously; The P trap layer first area 11 first corresponding interareas 18 are provided with emitter contact hole 13, and said emitter contact hole 13 is coated with emitter metal layer 5 over against the P trap layer first area 11 of its below above said insulating medium layer 6; Said emitter metal layer 5 is filled in the emitter contact hole 13, and keeps equal potentials with P trap layer first area 11; 1 below, said N type drift region includes N type field cut-off region 14; Said N type field cut-off region 14 is positioned at 1 bottom, N type drift region; And near second interarea 19 of semiconductor substrate 17, the N type impurity concentration of said N type field cut-off region 14 is higher than the N type impurity concentration of N type drift region 1; Be provided with P type injection region 3 below the said N type field cut-off region 14; Said P type injection region 3 corresponding upper surfaces contact with N type field cut-off region 14; Said P type injection region 3 corresponding lower surfaces are second interarea 19; Said second interarea, 19 surface coverage have collector electrode metal layer 4, can form the collector terminal 25 of IGBT device through collector electrode metal layer 4; Simultaneously, can form the emitter terminal 27 of IGBT device, through forming the gate terminal 26 of IGBT device after the conductive polycrystalline silicon parallel connection in the active area 15 through emitter metal layer 5.
As shown in Figure 7, along on the cross section of B-B among Fig. 3, the N type injection region 10 on 11 tops, said P trap layer first area connects into integral body, and the emitter metal layers 5 in its top emitter contact hole 13 are connected with N type injection region 10, and the maintenance equal potentials.
As shown in Figure 4: the sketch map that adopts plane cellular structure for the active area 15 of the utility model IGBT device.When active area 15 adopts planarized structure; Cross section at said IGBT device is up; Said conductive polycrystalline silicon 9 is positioned on first interarea 18; Conductive polycrystalline silicon 9 and 18 growths of first interarea have insulated gate oxide layer 8, and said conductive polycrystalline silicon 9 overlaps with P trap layer first area 11, P trap layer second area 12 parts of conductive polycrystalline silicon 9 both sides side-lowers, and overlap mutually N type injection region 10 in the P trap layer first area 11 of conductive polycrystalline silicon 9 and part overlapping; Conductive polycrystalline silicon 9 is covered by insulating medium layer 6 parcels of top, and the insulated gate oxide layer 8 of first interarea, 18 tops and conductive polycrystalline silicon 9 constitute plane cellular structure.In N type drift region 1, P trap layer first area 11 is isolated through insulated gate oxide layer 8, the conductive polycrystalline silicon 9 of N type drift region 1 and top with P trap layer second area 12.
1 below, said N type drift region includes N type field cut-off region 14; Said N type field cut-off region 14 is positioned at 1 bottom, N type drift region; And near second interarea 19 of semiconductor substrate 17, the N type impurity concentration of said N type field cut-off region 14 is higher than the N type impurity concentration of N type drift region 1; Be provided with P type injection region 3 below the said N type field cut-off region 14; Said P type injection region 3 corresponding upper surfaces contact with N type field cut-off region 14; Said P type injection region 3 corresponding lower surfaces are second interarea 19; Said second interarea, 19 surface coverage have collector electrode metal layer 4, can form the collector terminal 25 of IGBT device through collector electrode metal layer 4; Simultaneously, can form the emitter terminal 27 of IGBT device, through forming the gate terminal 26 of IGBT device after the conductive polycrystalline silicon parallel connection in the active area 15 through emitter metal layer 5.
Like Fig. 8～shown in Figure 180: when the active area 15 of IGBT device adopted the cellular groove structures, above-mentioned IGBT device can form through following processing step:
A, the semiconductor substrate 17 of the N type with two relative interareas is provided, said two interareas comprise first interarea 18 and second interarea 19; First interarea 18 and 19 of second interareas of semiconductor substrate 17 comprise N type drift region 1;
As shown in Figure 8: the material of semiconductor substrate 17 comprises silicon, and the upper surface of semiconductor substrate 17 forms first interarea 18, and the lower surface of semiconductor substrate 17 forms second interarea 19;
B, on above-mentioned first interarea deposit hard mask layer 20; Said hard mask layer 20 can adopt LPTEOS (low-pressure chemical vapor deposition tetraethyl orthosilicate), thermal oxidation silicon dioxide adds chemical vapour deposition (CVD) silicon dioxide or thermal silicon dioxide adds silicon nitride;
C, optionally shelter and etching hard mask layer 20, form the hard mask of etching groove, and etching forms groove on first interarea 18, said groove comprises cellular groove 7;
As shown in Figure 9: show the groove structure in the active area 15 in the utility model, the structure in terminal protection district 16 can be consistent with existing structure;
D, remove the hard mask layer 20 on said first interarea 18, in said trench wall superficial growth insulated gate oxide layer 8, and in said inner wall surface growth has the groove of insulated gate oxide layer 8 deposit conductive polycrystalline silicon 9;
E, etching are removed the conductive polycrystalline silicon 9 on first interarea 18, obtain conductive polycrystalline silicon 9 in the groove;
Shown in figure 10: when deposit conductive polycrystalline silicon 9 in groove, corresponding conductive polycrystalline silicon 9 also can cover on first interarea 18 inside and outside removing and being filled in cellular groove 7, need remove the conductive polycrystalline silicon 9 on first interarea 18;
F, on first interarea 18, the p type impurity ion is injected in autoregistration, and forms P trap layer 2 through the high temperature knot, P trap layer 2 is separated to form P trap layer first area 11 and P trap layer second area 12 through cellular groove 7 and conductive polycrystalline silicon 9; Shown in figure 11;
G, on said first interarea 18, carry out the source region photoetching, and inject the N type foreign ion of high concentration, and obtain being positioned at the N+ injection region 10 of P trap layer first area 11 through the high temperature knot;
Shown in figure 12: for can be in the N+ injection region 10 in the P trap layer first area 11; On first interarea 18 corresponding, be provided with and inject barrier bed 21 with P trap layer second area 12; Can avoid in P trap layer second area 12, forming N+ injection region 10 through injecting barrier bed 21, inject barrier bed 21 and can be photoresist;
H, on above-mentioned first interarea 18, deposit insulating medium layer 6;
Shown in figure 13: said insulating medium layer 6 is covered in first interarea 18 of semiconductor substrate 17, promptly covers the notch and cellular groove 7 two side areas of cellular groove 7 simultaneously; Insulating medium layer 6 is non-doped silicon glass (USG), boron-phosphorosilicate glass (BPSG) or phosphorosilicate glass (PSG), and the material of said semiconductor substrate comprises silicon;
I, optionally shelter and etching insulating medium layer 6, form the emitter contact hole 13 that is positioned at 11 tops, P trap layer first area;
Shown in figure 14: can access emitter contact hole 13 through etching insulating medium layer 6, said emitter contact hole 13 extends on first interarea 18 from the surface of insulating medium layer 6;
J, above said insulating medium layer 6 deposited metal, the metal material that the material of said metal level can be conventional;
K, optionally shelter and etching sheet metal, form emitter metal layer 5, said emitter metal layer 5 is filled in the emitter contact holes 13, and the maintenance equipotential that contacts with P trap layer first area 11, and is shown in figure 15;
L, second interarea 19 of said semiconductor substrate 17 is ground attenuate; The thickness of said grinding attenuate is provided with according to the environment for use of IGBT;
M, to injecting N type foreign ions through second interarea 19 behind the attenuate, form N type field cut-off region 14;
Shown in figure 16: the N type concentration impurity ion that forms N type field cut-off region 14 is not less than the N type concentration impurity ion of N type drift region 1;
N, second interarea 19 is injected the p type impurity ions, and carry out impurity activation, form P type injection region 3 through high annealing; Shown in figure 17;
O, at second interarea, 19 surface deposition metal levels, form collector electrode metal layer 4, said collector electrode metal layer 4 and P type injection region 3 ohmic contact, shown in figure 18.
When the active area 15 of IGBT device adopts planarized structure, can form through following processing step, be specially:
A, the semiconductor substrate 17 of the N type with two relative interareas is provided, said two interareas comprise first interarea 18 and second interarea 19; First interarea 18 and 19 of second interareas of semiconductor substrate 17 comprise N type drift region 1;
B, the insulated gate oxide layer 8 of on said first interarea 18, growing;
C, deposit conductive polycrystalline silicon 9 on first interarea 18 of insulated gate oxide layer 8 is arranged in growth;
D, optionally shelter and etching conductive polysilicon 9;
E, on first interarea 18, be that p type impurity is injected in the masking layer autoregistration with conductive polycrystalline silicon 9, and form P trap layer first area 11 and P trap layer second area 12 through the high temperature knot;
F, on said first interarea 18, carry out the source region photoetching, and inject the N type foreign ion of high concentration, and obtain being positioned at the N+ injection region 10 of P trap layer first area 11 through the high temperature knot;
G, on above-mentioned first interarea 18, deposit insulating medium layer 6;
H, optionally shelter and etching insulating medium layer 6, form the emitter contact hole 13 that is positioned at 11 tops, P trap layer first area;
I, above said insulating medium layer 6 deposited metal;
J, optionally shelter and etching sheet metal, form emitter metal layer 5, said emitter metal layer 5 is filled in the emitter contact holes 13, and the maintenance equipotential that contacts with P trap layer first area 11;
K, second interarea 19 of said semiconductor substrate 17 is ground attenuate;
L, to injecting N type foreign ions through second interarea 19 behind the attenuate, form N type field cut-off region 14;
M, second interarea 19 is injected the p type impurity ions, and carry out impurity activation, form P type injection region 3 through high annealing;
N, at second interarea, 19 surface deposition metal levels, form collector electrode metal layer 4.
Wherein, when active area 15 adopted plane cellular structures, the process conditions of corresponding forming process and the material of employing all can the groove-shaped cellular structures of adopting by reference, no longer detail here.
Shown in figure 19, during use,,, form the gate terminal 26 of IGBT devices through the conductive polycrystalline silicon 9 of parallel connection through the emitter terminal 27 of emitter metal layer 5 formation IGBT device through the collector terminal 25 of collector electrode metal layer 4 formation IGBT device.When said IGBT device forward conduction; The grid conductive polycrystalline silicon that is device applies the grid-emitter voltage Vge that is higher than device cut-in voltage Vth; Simultaneously, collector terminal 25 applies a positive voltage Vce, P type injection region 3 injected hole charge carrier in N type drift region 1 at second interarea, 19 places of said IGBT device; The part of said holoe carrier is passed P trap layer first area 11 until emitter metal layer 5; Thereby form hole current 24, and another part of holoe carrier since P trap layer second area 12 for floating settings, so can't pass through P trap layer second area 12 and below P trap layer second area 12 near zone accumulate and increase; When the holoe carrier when here runs up to concentration considerably beyond the intrinsic carrier concentration of N type drift region 1 here; Conductivity modulation effect promptly occurs, the resistivity of semiconductor substrate 17 obviously reduces because of the holoe carrier of a large amount of accumulation here, thereby has reduced the conducting saturation voltage drop Vcesat of device.Shown in figure 20; Be to adopt the utility model structure and other two kinds of present common structures (the NPT structure is ended structure with the field) to make relatively with the Vcesat measured value behind a 1200V 25A IGBT; The IGBT device of three kinds of structures uses identical semiconductive material substrate and chip area; Wherein the utility model structure is ended the N type drift region that structure has same thickness with the field, and the N type drift region of NPT structure can be found out by curve among the figure than the above two thick about 30um; The Vcesat of the IGBT of employing the utility model structure is obviously low than other Vcesat of two kinds of structures; When current density was 80A/cm2, the utility model structure was low more about 40% than NPT type structure, than the field by structure low about 20%.
Come flow-thru electrode electron current 23 because device can form conducting channel in the P trap layer first area 11 when forward conduction, principle is with the conducting channel 22 of common N type MOSFET, and P trap layer second area 12 then can not form conducting channel; Therefore; The raceway groove quantity of device parallel connection can obviously reduce, thereby reduces the saturation current of device greatly, and the saturation current reduction can help improving the short circuit current tolerance of device; Specifically; When the short circuit current test condition of given device, the short circuit current duration of device can increase, and can improve the impact resistance of device like this.
Shown in figure 21, when said IGBT device withstand voltage was worked, promptly the grid conductive polycrystalline silicon 9 of device kept zero potentials with emitter terminal 27; Simultaneously; Keep a forward high potential Vce on the collector terminal 25, at this moment, the depletion layer of the device meeting overwhelming majority is extending in N type drift 1 district; Direction is pointed to second interarea 19; Electric field strength when the electric field strength coordinate system on right side and left side the utility model IGBT device are worked among Figure 21 is corresponding to the same, and abscissa is represented corresponding electric field strength, and ordinate is corresponding with the position of IGBT device.Because semiconductor substrate is through thinning back side; Therefore remaining N type drift region 1 thickness is not enough to bear fully all electric fields, when depletion layer expands to N type drift region 1 with N type field cut-off region 14, can continue in the cut-off region of N type field, to expand, because N type field cut-off region 14 has higher impurity concentration; Therefore; Electric-force gradient is steepening herein, and ends at fully in the N type field cut-off region 14, reaches to bear the purpose of specifying Vce voltage; Because semiconductor substrate 17 thickness are through attenuate, so the Vcesat of device when forward conduction also can obviously reduce.
P trap layer first area 11 in the utility model is same manufacturing layer with P trap layer second area 12; The existing IGBT manufacturing process of contrast does not increase any processing step; Therefore, the manufacturing cost of device does not increase, can be compatible with existing ripe IGBT manufacturing process; In addition, the second width n of first width m of P trap layer first area 11 and P trap layer second area 12 can be provided with according to the specified design size, thereby the Vcesat of trim and saturation current easily are simple.
Claims (6)
1. IGBT with low conducting saturation voltage drop; On the top plan view of said IGBT device; Comprise the active area and the terminal protection district that are positioned on the semiconductor substrate, said active area is positioned at the central area of semiconductor substrate, and the terminal protection district is around being surrounded by the source region; On the cross section of said IGBT device, said semiconductor substrate has two relative interareas, and said interarea comprises first interarea and second interarea, comprises the first conduction type drift region between first interarea of semiconductor substrate and second interarea; Comprise the conductive polycrystalline silicon that is connected in parallel in the said active area; It is characterized in that:
On the cross section of said IGBT device; In the first corresponding conduction type drift region of active area, second conductive type layer is set; Said second conductive type layer is separated into the some second conductive type layer first areas and the second conductive type layer second area through conductive polycrystalline silicon and insulated gate dielectric layer; The second conductive type layer first area and the second conductive type layer second area replace rule each other in the first conduction type drift region arranges, and through conductive polycrystalline silicon and insulated gate dielectric layer interval;
On the cross section of said IGBT device, be coated with insulating medium layer on first interarea of semiconductor substrate, and said insulating medium layer covers on the corresponding conductive polycrystalline silicon; The first conduction type injection region of symmetrical distribution is set in the second conductive type layer first area; The said first conduction type injection region contacts with the corresponding insulation gate dielectric layer; And top, the second conductive type layer first area is provided with the emitter contact hole, and said emitter contact hole connects insulating medium layer and extends on first interarea; Be filled with the emitter metal layer in the emitter contact hole, and said emitter metal layer is covered on the insulating medium layer emitter metal layer and the second conductive type layer first area ohmic contact.
2. the IGBT with low conducting saturation voltage drop according to claim 1; It is characterized in that: on the cross section of said IGBT device; The second conductive type layer first area has first width; The second conductive type layer second area has second width, and the second conductive type layer first area and the second conductive type layer second area are same manufacturing layer.
3. the IGBT with low conducting saturation voltage drop according to claim 1; It is characterized in that: on the cross section of said IGBT device; Comprise the first conduction type field cut-off region in the said first conduction type drift region; The said first conduction type field cut-off region is positioned at the bottom of the first conduction type drift region, and near second interarea of semiconductor substrate; The first conductive type impurity concentration of the first conduction type field cut-off region is not less than the first conductive type impurity concentration of the first conduction type drift region.
4. the IGBT with low conducting saturation voltage drop according to claim 3; It is characterized in that: on the cross section of said IGBT device; In the said first conduction type drift region, below the corresponding first conduction type field cut-off region the second conduction type injection region is set; The second conduction type injection region contacts with the first conduction type field cut-off region, and second conduction type injection region correspondence is second interarea with contacted another surface of the first conduction type field cut-off region; Be coated with the collector electrode metal layer on second interarea of semiconductor substrate, the said collector electrode metal layer and the second conduction type injection region ohmic contact.
5. the IGBT with low conducting saturation voltage drop according to claim 1; It is characterized in that: on the cross section of said IGBT device; Said active area adopts groove cellular structure; Said cellular groove is positioned at second conductive type layer, and the degree of depth stretches in the first conduction type drift region of second conductive type layer below; The insulated gate oxide layer growth also is covered in the inwall and the lower surface of cellular groove, and conductive polycrystalline silicon is filled in growth to be had in the cellular groove of insulated gate oxide layer; Conductive polycrystalline silicon in cellular groove and the cellular groove is separated into the second conductive type layer first area and the second conductive type layer second area with second conductive type layer, and the first conductive type layer injection region in the second conductive type layer first area contacts with corresponding cellular groove one side sidewall; Insulating medium layer covers the notch of cellular groove, and insulated gate oxide layer and conductive polycrystalline silicon in the cellular groove form groove-shaped cellular structure.
6. the IGBT with low conducting saturation voltage drop according to claim 1 is characterized in that: on the cross section of said IGBT device, said active area adopts plane cellular structure; Said conductive polycrystalline silicon is positioned on first interarea; Growth has the insulated gate oxide layer between the conductive polycrystalline silicon and first interarea; The second conductive type layer first area, the second conductive type layer second area of said conductive polycrystalline silicon and conductive polycrystalline silicon both sides side-lower partly overlap; And overlap mutually the first conduction type injection region in the second conductive type layer first area that conductive polycrystalline silicon and part overlap; Conductive polycrystalline silicon is covered by the insulating medium layer of top parcel, and the insulated gate oxide layer of first interarea top and conductive polycrystalline silicon constitute plane cellular structure.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2015010656A1 (en) * | 2013-07-26 | 2015-01-29 | 无锡华润上华半导体有限公司 | Method for the manufacture of non-punch-through insulated gate bipolar transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2015010656A1 (en) * | 2013-07-26 | 2015-01-29 | 无锡华润上华半导体有限公司 | Method for the manufacture of non-punch-through insulated gate bipolar transistor |
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