CN202405260U - Active matrix display - Google Patents
Active matrix display Download PDFInfo
- Publication number
- CN202405260U CN202405260U CN 201120577247 CN201120577247U CN202405260U CN 202405260 U CN202405260 U CN 202405260U CN 201120577247 CN201120577247 CN 201120577247 CN 201120577247 U CN201120577247 U CN 201120577247U CN 202405260 U CN202405260 U CN 202405260U
- Authority
- CN
- China
- Prior art keywords
- tft
- crystal grain
- mic
- polysilicon membrane
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The utility model provides an active matrix display, which comprises a plurality of thin film transistors, wherein each thin film transistor comprises an active layer, a source, a drain, a gate insulating layer and a gate; the active layer is made of a polycrystalline silicon thin film; parallel conductive strips or parallel conductive wires are arranged in the polycrystalline silicon thin film and connected with a plurality of crystal grains; the source and the drain are arranged on the active layer; each conductive strip or each conductive wire consists of doped lines; and the direction of each of the parallel conductive strips or the parallel conductive wires is perpendicular to that of current.
Description
Technical field
The utility model relates to the polysilicon technology, relates more specifically to a kind of Active Matrix Display.
Background technology
Show the field at the traditional active matrix, TFT normally uses amorphous silicon (a-Si) material to make.This mainly is because its reduction process temperature and low manufacturing cost on the large-area glass base plate.Polysilicon is used for high-resolution LCD (LCD) and active organic electroluminescent display (AMOLED) recently.Polysilicon also has the advantage of integrated circuit on glass substrate.In addition, polysilicon has the possibility of big pixel aperture ratio, has improved optical energy utilization efficiency and has reduced LC and the power consumption of bottom-emission OLED display.As everyone knows; Multi-crystal TFT is more suitable for being used for the driving OLED pixel; Not only because OLED is a current-driven apparatus, a-Si TFT has the long-term reliability problems of driving OLED, and is because the amorphous silicon electron mobility is less; The ratio that needs big W/L is to provide enough OLED pixel driving currents.Therefore, for High Resolution Display, high-quality multi-crystal TFT is absolutely necessary.
In order to realize the suitability for industrialized production of active matrix TFT display panel, need the quality of very high polysilicon membrane.It need satisfy K cryogenic treatment on large-area glass substrate, makes stable manufacturing process, high-performance, the high uniformity of device performance and high reliability cheaply.
The high temperature polysilicon technology can be used for realizing high performance TFT, but it can not be used in the common glass substrates of using in the commercial panel.In this case, must use low temperature polycrystalline silicon (LTPS).Three main LTPS technology are arranged: (1) is at the solid-phase crystallization (SPC) of 600 ℃ of a very long times of annealing down; (2) excimer laser crystallization, annealing (ELC/ELA) or flash annealing; (3) crystallization inducing metal (MIC).ELC can produce optimum efficiency, but is subject to high equipment investment and maintenance cost, and the size of glass substrate also is difficult to further increase.SPC is the most cheap technology, but need be 600 ℃ of annealing just crystallizations in about 24 hours down.The shortcoming of MIC is the heterogeneity of metallic pollution and TFT device.Thereby, also have no a kind of technology can satisfy all above-mentioned low costs and high performance requirement.
The common ground of all polycrystalline silicon film materials is that the size of the crystallization direction of the crystal grain on the film and shape are random distribution in itself.When this polysilicon membrane is used as the active layer of TFT, the electrology characteristic of TFT is subject to the crystal boundary that occurs in the raceway groove.The distribution of crystal grain is at random, makes that the electrology characteristic of TFT of whole base plate is inhomogeneous.The problem that this just electrology characteristic distributes and disperses makes final demonstration defective and the brightness heterogeneous like mura occur.
The utility model content
For overcoming above-mentioned defective; The application proposes a kind of Active Matrix Display; Comprise a plurality of thin-film transistors, wherein each thin-film transistor comprises: active layer is made up of polysilicon membrane; Have parallel conductive strips or conductor wire in this polysilicon membrane, said conductive strips or conductor wire connect a plurality of crystal grain; Source electrode on the active layer and drain electrode; Gate insulator; Grid; Said conductive strips or conductor wire are made up of the lines that mix; The parallel conductive strips or the direction of conductor wire are perpendicular to the sense of current.
Comprise P type thin-film transistor and N type thin-film transistor in a plurality of thin-film transistors that comprise; Wherein conductive strips in the polysilicon membrane of the formation active layer of P type thin-film transistor or conductor wire are made up of the lines of boron-doping, and conductive strips or conductor wire in the polysilicon membrane of the formation active layer of N type thin-film transistor are made up of the lines of mixing phosphorus.
The width of a plurality of conductive strips or conductor wire and spacing and grain size are similar.
Constitute in the polysilicon membrane of active layer, in the lines of doping, the doping peak on the polysilicon membrane thickness direction is positioned at the center of polysilicon membrane thickness.
Use this BG polysilicon layer as active layer, guarantee that current vertical flows through parallel lines TFT design, the influence of crystal boundary can reduce.Threshold voltage, the switch ratio, device mobility, the uniformity of whole base plate, these important characteristics of the reliability of sub-threshold slope and device can use present this technology to be improved.These improvement simultaneously also can be so that cost be lower, and price is more cheap, and high performance LTPS TFT is become a reality.
Description of drawings
Followingly the utility model embodiment is described further with reference to accompanying drawing, wherein:
Fig. 1 a and Fig. 1 b are respectively the sketch map of the low-temperature polysilicon film and the barrier Distribution of correspondence;
Fig. 2 a and Fig. 2 b are respectively the sketch map of the bridged-grain polysilicon membrane and the barrier Distribution of correspondence;
Fig. 3 is for forming the cross sectional representation of BG line structure;
Fig. 4 is the SEM picture of the BG line pattern of 1 μ m for the cycle that forms with PR1075;
Fig. 5 a, 5b and 5c are respectively the cross sectional representation of sample A, sample B and sample C crystallization;
Fig. 6 injects the cross sectional representation behind the formation BG line for all samples through photoresist and ion;
Fig. 7 a, 7b and 7c are the microphoto of TMAH etching macromeritic polysilicon, little grained polysilicon and SR-MILC polysilicon;
Fig. 8 is a BG TFT structure cross sectional representation;
Fig. 9 a is with V
GsAs the transfer characteristic curve of the big crystal grain MIC of the P raceway groove TFT that BG and no BG are arranged of function, Fig. 9 b is with V
GsAs the output current of the big crystal grain MIC of the P raceway groove TFT that BG and no BG are arranged of function than scheming;
Figure 10 a and 10b are at V
Ds=-0.1V and V
DsThe mutual conductance of BG big crystal grain MIC TFT and the big crystal grain MIC of non-BG TFT under the=-5V situation;
Figure 11 a and 11b are respectively the V of the TFT of equally distributed 50 big crystal grain MIC TFTs and 50 the big crystal grain MIC of BG TFTs
ThWith the GIDL performance difference;
Figure 12 a and 12b are respectively with V
GsAs function, the BG structure is arranged and do not have the BG structure the little crystal grain MIC of P type multi-crystal TFT transfer characteristic curve and with V
GsAs function, the BG structure is arranged and do not have the output current ratio of the little crystal grain MIC of the P type multi-crystal TFT of BG structure;
Figure 13 a and 13b are respectively at V
Ds=-0.1V and V
DsThe mutual conductance of BG little crystal grain MIC TFT and the little crystal grain MIC of non-BG TFT during=-5V;
Figure 14 a and 14b are respectively the Vth of the little crystal grain MICTFTs of equally distributed little crystal grain MIC TFTs and BG and the difference of GIDL performance;
Figure 15 a and 15b are respectively with V
GsBe function, have BG and no BG structure P type raceway groove SR-MILCTFTs the transfer characteristic curve and with V
GsBe function, the output current ratio of the P type raceway groove SR-MILCTFTs of BG and no BG structure is arranged;
Figure 16 is the regional microgram of the SR-MILC polysilicon after the etching of TMAH. can see that crystal grain and low angle grain boundary thereof are substantially parallel with the MILC direction, the sense of current of having used the some coil to mark A type and Type B TFTs is parallel and perpendicular to the MILC direction;
Figure 17 is the distinctive logarithmic scale curve of general A type and Type B SR-MILC TFTs, and main difference is the subthreshold value zone;
Figure 18 be with channel length as function, Vth mean value and the standard deviation (S.D.) of extraction A type and Type B TFTs;
Figure 19 is the I-V curve of peculiar linear graduation of the conventional SR-MILC TFT of A and Type B, and can find out has maximum difference in the ON state field;
Figure 20 is when Vds=-0.1V and Vgs=-18V, the extraction resistivity of A type and Type B poly-Si TFTs;
Figure 21 is the A type of BG structure and the Vth of Type B TFTs;
Figure 22 is the A type of BG structure and the resistivity of Type B TFTs.
Embodiment
Generally, polysilicon is made up of two parts, and a kind of is single grained region, and another kind is a crystal boundary.Intragranular conductive characteristic almost is identical, and it is relatively poor to stride the conduction of crystal boundary, and this can cause the loss of whole mobility and the increase of threshold voltage.The active channel of the thin-film transistor of polysilicon membrane (TFT) is made up of such polysilicon membrane usually.Random conductive characteristic with variation is unfavorable for display performance and image quality.Typical polysilicon structure figure is shown in Fig. 1 a, and low-temperature polysilicon film comprises the border of crystal grain and crystal grain.Adjacent intergranule has tangible crystal boundary.Generally, the length of crystal grain is in tens nanometers, between several microns sizes, is considered to a single crystal.The crystal boundary place is distributed with a lot of dislocation usually, storehouse fault and hanging key defect.Because the crystal grain in the different preparation, low-temperature polysilicon film possibly be random distribution or be directional distribution.
There is major defect at crystal boundary, will causes high potential barrier, as shown in Fig. 1 b.The carrier transport of potential barrier (or vertical component of oblique potential barrier) vertical direction can have influence on initial condition and current capacity.The thin-film transistor threshold voltage of this low-temperature polysilicon film preparation, field-effect mobility all is subject to the crystal boundary potential barrier.When the grain boundary of playing the binding effect is applied to TFT, also can under high reverse grid voltage, cause bigger leakage current.
The polysilicon technology of bridged-grain (BG) is the active layer at TFT, connects the technology of crystal grain through using parallel electrically conductive band or line.Form the crossover track of the crystal grain that the electric current of conductive strips or vertical direction flows through, can improve the performance of TFT greatly.These crossover tracks can reduce the influence of crystal grain boundary, as shown in Fig. 2 (b).This structure is defined as the structure of bridged-grain (BG).
Said " bridging " is made up of parallel highly doped lines, and we are referred to as the BG line.The BG line that forms on the polysilicon membrane should be narrow, and is very close to each other.The width of this line and spacing should be with crystal grain big or small similar.Conductor wire should not contact with each other, and should contain whole polysilicon membrane so that with reprocessing.The major function of BG line is to build bridge perpendicular to the flow of current direction at intergranule.Therefore, electric current is mobile along these circuits no longer is a major issue.
The polysilicon membrane sketch map of the bridged-grain structures of Fig. 2 a shown in being.Conductor wire is perpendicular to the flow of current direction.These conductor wires can form with p or n type doped semiconductor dopant ion.Doping can be adjusted, to create conductive channel, usually 10
12/ cm
2To 10
16/ cm
2Scope.The pattern of mixing can be carried out with various methods, like simple photoetching, and laser interference, or nano imprint lithography etc.
Present embodiment provides a kind of formation to have the method for the polysilicon membrane of bridged-grain (BG) line, comprising:
1) at polysilicon membrane surface spin coating one deck PR 1075 photoresists, after the spin coating of PR photoresist, sample is heated to 90 degree and carries out soft roasting; Be 1 minute heating time, and soft roasting purpose is in order to reduce the solvent of photoresist, from～20% to～5%; Discharge the stress induce spin-coated thin film simultaneously, soft roasting after, use ASM PAS5000 step photo-etching machine photoresist to be made public under as 365nm light at wavelength; After 110 ℃ of barbecues 1 minute; Sample is dipped into FHD-530 and carries out development treatment second then, and the photoresist that is emerging under the light is dissolved in the lysate, and the part that does not touch light is to keep intact; Thereby make the BG line graph transfer to (as shown in Figure 3) on the photoresist, the formation cycle is the BG line pattern (its SEM photo is as shown in Figure 4) of 1 μ m;
2) after 120 ℃ of hard baking, sample is sent to and carries out the ion injection in the CF3000.
The step photo-etching machine of ASML 5000 types of NFF (The Nanoelectronics Fabrication Facility nanoelectronic manufacturing works), ratio is 5 to 1, this has guaranteed that minimum feature and minimum interval are 0.5 μ m.Therefore, minimum line cycle limit is at 1 μ m.
Present embodiment generates two steps of BG pattern and ion injection through photoetching, obtained by the single repetition period be the BG line that the DOPOS doped polycrystalline silicon parallel lines of 1 μ m are formed.
In other embodiments, also can after forming the BG line earlier on the amorphous silicon, again recrystallized amorphous silicon be become polysilicon, promptly the BG line can be formed on before or after the crystallization.
This elder generation mixes on amorphous silicon and forms the BG line method of crystallization again, and recrystallized amorphous silicon, the method that on polysilicon, forms the BG line is again compared, and has the following advantages at least with earlier: mix when on amorphous silicon, carrying out the P type, more can promote the crystallization of amorphous silicon during annealing; Because dopant can spread when recrystallized amorphous silicon, utilize this point, the ratio of controlled doping district and non-doped region is better dwindled the probability of the crystal boundary that is present in non-doped region further, reduces short risk simultaneously; Have again because annealing process is after mixing, in the recrystallized amorphous siliconization also electrode dopant activation.
Present embodiment provides a kind of formation to have the method for the polysilicon membrane of bridged-grain (BG) line, comprising:
1) on the Eagel2000 glass substrate, uses the silica (SiO of plasma enhanced chemical vapor deposition (PEVCD) deposition 300nm
2).Use the a-Si of low-pressure chemical vapor deposition (LPCVD) method then 550 ℃ of environment deposit 45 nanometers;
2) hold liquid (HF) lining dipping 1 minute behind the natural oxidizing layer of removing at 1% hydrofluoric acid, put temperature into and be the oxidation environment 15 minutes of 550 degree, make the a-Si surface form one deck SiO
2Nano-oxide layer;
3) sputter one deck slowly-releasing (SR) nickel/silicon oxidation source layer carries out crystallization inducing metal on this nanometer layer; Adopt nickel silicon alloy as target; The nisiloy ratio is: Ni: Si=1: 9; Sputter is in argon gas and 200: 1 mixed environment of oxygen, to carry out, and the sputter DC power supply is 7W, and sputtering time is 90 seconds;
4) at 590 ℃ of N
2Heating is 6 hours under the atmosphere, and till the complete crystallization of a-Si, Fig. 5 a is the schematic cross-section of this crystallization protocol;
5) soak 120 ℃ of mixed solution H
2SO
4+ H
2O
2In 10 minutes, go up residual nickel to remove the surface.Be put into 1% etching acid (HF) then and soaked 1 minute,, deposit the LTO of 100nm again to remove nano coating;
6) use the wavelength described in the embodiment 1 to form the BG pattern as the ASM PAS5000 step photo-etching machine of 365nm, the BG line cycle is 1 micron.
7) 120 ℃ the baking 30 minutes after, for all P channel TFT, at energy and the 2E15/cm of 40KeV
2Dosage uses boron to mix as BG down, for all N type TFT, uses phosphorus to mix as BG, and it is to carry out through two steps that the BG here mixes, and the dosage in each step is 1E15/cm
2, inject energy and be respectively 80KeV and 130KeV, obtain structure as shown in Figure 6;
8) use oxygen plasma at 100 degrees centigrade of following 30 minutes stripping photoresists, remove after the PR photoresist, the LTO of 100nm also uses 777 wet removal at quarter.After this step completion of BG, the entire portion doped polycrystalline silicon film can be called BG-poly-Si, can be used for the TFT active layer.
Utilize slowly-releasing nickel/silicon oxidation source layer to carry out in the process of crystallization inducing metal, slowly-releasing nickel/silicon oxidation source is a supplementary source as nickel in a relatively slow speed.This nickel induces the nickel in source by slowly providing in silicon and the reaction of nisiloy oxide, and this provides a large amount of pure nickel atoms to be very different with the pure nickel source.Therefore, the nickel amount that nickel oxide provides is less than the pure nickel source, and this Soft Release reaction nickel can reduce the content of residual nickel in polysilicon.
The internal structure of the film that the resulting polysilicon membrane of the step 4) of the method that provides in the present embodiment is shown after the room temperature etching by TMAH (TMAH) etching solution is shown in Fig. 7 a; The polysilicon that present embodiment obtains is large-scale grained polysilicon, and high mobility, low cost and stress relief annealed characteristic are arranged.
Embodiment 3
Present embodiment provides a kind of formation to have the method for the polysilicon membrane of bridged-grain (BG) line, comprising:
1) on the Eagel2000 glass substrate, uses the silica (SiO of plasma enhanced chemical vapor deposition (PEVCD) deposition 300nm
2).Use the a-Si of low-pressure chemical vapor deposition (LPCVD) method then 550 ℃ of environment deposit 45 nanometers;
2) hold liquid (HF) lining dipping 1 minute behind the natural oxidizing layer of removing at 1% hydrofluoric acid, immersing temperature is the H of 120 degree
2SO
4+ H
2O
2 Mixed solution 10 minutes makes the a-Si surface form one deck SiO
2Nanometer layer;
3) sputter one deck slowly-releasing (SR) nickel/silicon oxidation source layer carries out crystallization inducing metal on this nanometer layer; Adopt nickel silicon alloy as target; The nisiloy ratio is: Ni: Si=1: 9; Sputter is in argon gas and 200: 1 mixed environment of oxygen, to carry out, and the sputter DC power supply is 7W, and sputtering time is 2 minutes;
4) at 590 ℃ of N
2Heating is 6 hours under the atmosphere, and till the complete crystallization of a-Si, Fig. 5 b is the schematic cross-section of this crystallization protocol;
5) soak 120 ℃ of mixed solution H
2SO
4+ H
2O
2In 10 minutes, go up residual nickel to remove the surface.Be put into 1% etching acid (HF) then and soaked 1 minute,, deposit the LTO (low temperature oxide) of 100nm again to remove nano coating;
6) use the wavelength described in the embodiment 1 to form the BG pattern as the ASM PAS5000 step photo-etching machine of 365nm, the BG line cycle is 1 micron;
7) 120 ℃ the baking 30 minutes after, for all P channel TFT, at energy and the 2E15/cm of 40KeV
2Dosage uses boron to mix as BG down, for all N type TFT, uses phosphorus to mix as BG, and it is to carry out through two steps that the BG here mixes, and the dosage in each step is 1E15/cm
2, inject energy and be respectively 80KeV and 130KeV, obtain structure as shown in Figure 6;
8) use oxygen plasma 30 minutes stripping photoresists under 100 ℃ of temperature, remove after the PR photoresist, the LTO of 100nm also uses 777 wet removal at quarter.After this step completion of BG, the entire portion doped polycrystalline silicon film can be called BG-poly-Si, can be used for the TFT active layer.
The internal structure of the film that the resulting polysilicon membrane of the step 4) of the method that provides in the present embodiment is shown after the room temperature etching by TMAH (TMAH) etching solution is shown in Fig. 7 b; The polysilicon that present embodiment obtains is the polysilicon membrane of little crystal grain (flocculent structure); Less mobility and higher nickel residual quantity are arranged, yet this technology has good uniformity, cost is low; Annealing time is short, wideer advantages such as PROCESS FOR TREATMENT window.
Present embodiment provides a kind of formation to have the method for the polysilicon membrane of bridged-grain (BG) line, comprising:
1) on the Eagel2000 glass substrate, uses the silica (SiO of plasma enhanced chemical vapor deposition (PEVCD) deposition 300nm
2).Use the a-Si of low-pressure chemical vapor deposition (LPCVD) method then 550 ℃ of environment deposit 45 nanometers;
2) flood 1 minute behind the natural oxidizing layer of removing, the low temperature oxide (LTO) of deposition one deck 100 nanometer thickness in 1% hydrofluoric acid appearance liquid (HF) lining;
3) through photoetching and etch process, on the LTO layer, forming width is that line (IL) is induced in 8 microns grooves conducts that are spaced apart 100 μ m, shown in Fig. 5 C, is dipped into the H of 120 degree
2SO
4+ H
2O
2In the mixed solution 10 minutes to remove photoresist; Sputter one deck slowly-releasing (SR) nickel/silicon oxidation source layer carries out crystallization inducing metal; Adopt nickel silicon alloy as target, the nisiloy ratio is: Ni: Si=1: 9, and sputter is in argon gas and 200: 1 mixed environment of oxygen, to carry out; The sputter DC power supply is 7W, and sputtering time is 6 minutes;
4) under 590 ℃, N
2The atmosphere heating was carried out crystallization in 2 hours, and Fig. 5 c is the schematic cross-section of this crystallization protocol;
5) be immersed to 120 the degree H
2SO
4+ H
2O
2 Mixed solution 10 minutes is gone up residual nickel to remove the surface;
6) use the wavelength described in the embodiment 1 to form the BG pattern as the ASM PAS5000 step photo-etching machine of 365nm, the BG line cycle is 1 micron;
7) 120 ℃ the baking 30 minutes after, for all P channel TFT, at energy and the 2E15/cm of 40KeV
2Dosage uses boron to mix as BG down, for all N type TFT, uses phosphorus to mix as BG, and it is to carry out through two steps that the BG here mixes, and the dosage in each step is 1E15/cm
2, inject energy and be respectively 80KeV and 130KeV, obtain structure as shown in Figure 6;
8) use oxygen plasma 30 minutes stripping photoresists under 100 ℃ of temperature, remove after the PR photoresist, the LTO of 100nm also uses 777 wet removal at quarter.After this step completion of BG, the entire portion doped polycrystalline silicon film can be called BG-poly-Si, can be used for the TFT active layer.
The internal structure of the film that the resulting polysilicon membrane of the step 4) of the method that provides in the present embodiment is shown after the room temperature etching by TMAH (TMAH) etching solution is shown in Fig. 7 c; The polysilicon that present embodiment obtains is induced transverse crystallizing (SR-MILC) polysilicon membrane for slowly-releasing nickel; A process window widely is provided, can have prevented the influence of batch processing the changes in process parameters between the polycrystalline SiTFT.
Present embodiment provides a kind of method of manufacturing thin film transistor, comprising:
1) method of utilizing the foregoing description 4 to provide forms the polysilicon membrane with bridged-grain (BG) line;
2) the BG-poly-Si Thinfilm pattern that mixes these parts with AME8110 active-ion-etch machine changes into active island;
3) through dry-etching, photoresist is removed by oxonium ion;
4) remove after the natural oxidizing layer with 1%HF, at 425 ℃ of low temperature oxides (LTO) through LPCVD deposition 100nm as gate insulator;
5) aluminium (or polysilicon of 280nm) of deposition 300nm and be patterned to gate electrode, it is 4 * 10 that the source-drain electrode of P type and N type TFT is carried out dosage respectively
15/ cm
2Boron and phosphorus doping;
6) the LTO separator of deposition one deck 500nm and activating dopant simultaneously;
7) etching contact hole, the contact wire and the patterning of the aluminium of sputter one deck 700nm-1% silicon form BG-poly-TFT then, and its cross sectional representation is as shown in Figure 8.
In other embodiments, above-mentioned steps 1) also replaceable one-tenth utilizes method or the additive method that the foregoing description 5 or embodiment 6 provide to form the polysilicon membrane with bridged-grain (BG) line.For hereinafter is described conveniently; The thin-film transistor called after sample A that the polysilicon membrane that will be formed by embodiment 4 (big crystal grain) is processed; The thin-film transistor called after sample B that will process by the polysilicon membrane (little crystal grain) that embodiment 5 forms, the thin-film transistor called after sample C (SR-MILC-TFT) that will process by the polysilicon membrane that embodiment 6 forms.
For the opposite sex that has according to the performance of the thin-film transistor of the utility model is described, the measurement of respectively TFT of 3 kinds of BG multi-crystal TFTs and no BG being carried out electrology characteristic with HP4156 analyzing parameters of semiconductor appearance is to carry out the performance comparison.V
Ds=-0.1V and V
Ds=-5V is through the V of TFT field-effect mobility (μ FE)
GsFunction measure transfer characteristic curve.Threshold voltage (Vth) is defined as works as V
DsDuring=-5V, make I
d=W/L * 10
-7The V of A
GVoltage.Field-effect mobility (μ FE) is at low drain voltage (V
DsDuring=-0.1V), its equation of n th order n:
Wherein W and L are effective channel width and length, g
mBe mutual conductance, C
OxBe the gate insulator layer capacitance of unit are, V
DsBe the voltage between drain electrode and the source electrode.The field-effect mobility of report is the maximum that records.
A: sample A (the big crystal grain MIC of BG TFTs)
Fig. 9 (a) is for working as V
Ds=-0.1V and V
DsDuring=-5V, V
GsThe transfer characteristic curve of the TFT of function.The electrical parameter of big crystal grain BG MIC TFT and the electrical parameter of non-BG are as shown in table 1.The subthreshold value amplitude of oscillation (S) of the large-scale crystal grain MIC of BG TFT is 0.78V/dec, but not that BG is 1.02V/dec.Threshold voltage (the V that the BG structure is arranged in addition,
Th) reduced 3.2V, up to-6.6V.Another significantly improves is that grid are induced drain leakage (GIDL).The leakage current of BG TFT is 6.13pA/ μ m, and this is that normal big crystal grain MIC TFT is at V
Gs=10V and V
DsDuring=-5V about 1/2000.From top contrast, after we can see Application of B G technology, most TFT parameter significantly improved.
What Fig. 9 (b) showed is with V
GsAs function, the big crystal grain MIC of BG TFT schemes with the output current ratio of non-BG structure TFT.We can find, work as V
GsAnd V
DsWhen changing, the current ratio (γ) between BG TFT and the non-BGTFT also can change.Work as V
DsDuring=-0.1V, as shown in Figure 9 in zone 1, γ is approximately～0.5, and it is half the to this means that leakage current has reduced.In the subthreshold value in the 2nd district zone, γ sharply increases, and maximum be～70, and this is about 20 times in the 3rd regional γ value.Work as V
Ds=-5V, big crystal grain MIC TFT has shown that unique leakage current and grid induce drain leakage (GIDL) in 1 zone, simultaneously, the GIDL of the big crystal grain MIC of BG TFT obviously is suppressed to～and 10
-10A and minimum current also descend 11 times.Shown in Fig. 9 (b), γ significantly drops to～and 10
-4Increase that it should be noted that the multi-crystal TFT OFF leakage current mainly contains 2 reasons.One of reason is in the drain region, owing to applying the high electric field that grid and drain voltage cause.Leakage current is along with V
DsIncrease and significantly increase; Second former in the grain boundary defect concentration near the drain region.For BG-TFT, also be because these two reasons in the minimizing of the leakage current in first district, because the effect that the BG structure is built bridge makes the minimizing of grain boundary defects, and make the minimizing of electric field at a series of serial shallow junctions of the active channel of BG-TFT.Polarity in the boron-doping of BG line and TFT source and leakage is consistent.Generally, non-doping MIC polysilicon membrane shows slight n polarity.Therefore, in the 1st zone, work as V
GsCompare V
ThHour, be n-polarity and doped region presents p+ polarity at the MIC polysilicon that does not have to mix, this just means has the TFT of BG structure active channel a series of pn knots that become.This also is why GIDL and minimum current all descend greatly.
In the 2nd district, sub-threshold region, the BG-line plays bridging action in the vertical direction of crystal grain to the flow of current direction, and the crystal boundary potential barrier is minimized by the BG structure, and meanwhile, because the doping of BG line, defect state and border heterogeneity are able to fill up or terminate.Therefore, the TFT threshold voltage that the BG structure not only arranged than the TFT that does not have the BG structure little～3V, simultaneously, have the subthreshold value amplitude of oscillation (S) of the TFT of BG structure also to reduce to 0.78V/decade from 1.02V/decade.
In zone 3, the increase of opening electric current is approximately relevant with 2 factors of BG structure.This is because there is the TFT of BG line can be counted as into a series of jitty TFTs.Therefore, the TFT of BG has the benefit of the short channel TFT of no hot carrier's effect, increasing ON state current, reduces the threshold voltage and the sub-threshold slope amplitude of oscillation etc.
Table 1 has the electrical parameter of the big crystal grain MIC of the P type TFT of BG structure and non-BG structure
Figure 10 (a) and (b) shown in be respectively at V
Ds=-0.1V and V
DsUnder the=-5V situation, the mutual conductance of BG big crystal grain MIC TFT and the big crystal grain MIC of non-BG TFT.
Figure 11 (a) and (b) shown in be the difference on the P type channel TFT performance, that shown is general big crystal grain MIC TFT and the V of the big crystal grain MIC of BG TFT
THAnd GIDL.DATA REASONING is evenly distributed on the TFT that surpasses on 4 inches the glass wafer from 50.Clearly, have the TFT of BG structure more much lower than the GIDL value of general big crystal grain MIC TFT, the otherness of GIDL also is greatly enhanced.Simultaneously, compare with normal big crystal grain MIC TFT, the big crystal grain MIC of BG TFT also shows littler V
ThChange and absolute V
ThValue.
B: sample B (the little crystal grain MIC of BG TFT)
Shown in Figure 12 (a) is to work as V
Ds=-0.1V and V
DsDuring=-5V, the BG structure is arranged and do not have the transfer characteristic curve of little crystal grain (or flocculent structure) the MIC multi-crystal TFT of BG structure.Shown in Figure 12 (b) is with V
GsAs function, the BG structure is arranged and do not have the output current of the little crystal grain MIC multi-crystal TFT of BG structure to scheme than (γ).Table 2 has been listed the electrical parameter of BG structure and the little crystal grain MIC of non-BG structure multi-crystal TFT.The subthreshold value amplitude of oscillation (S) of BG structure TFT and non-BG structure TFT is respectively 0.8V/dec and 1.15V/dec.Threshold voltage (the V that the TFT of BG structure is arranged in addition,
Th) absolute value is to have reduced 4.5V, drops to 6.8V.In the 2nd zone, shown in Figure 12 (b), V is worked as in the subthreshold value zone
Ds=-0.1V and V
DsDuring=-5V, γ significantly increases, and reach peak～2 * 10
4With～4 * 10
3, this than the γ in the 3rd district value big hundreds of or thousands of doubly.
Another is significantly improved to be the leakage current in 1 zone, shown in Figure 12 (a).Work as V
Gs=10V and V
Ds=-5V the time, the leakage current of the little crystal grain MIC of BG TFT is 14.6pA/um, this be normal little crystal grain MIC TFT about 1/50.Shown in Figure 12 (a), work as V
Ds=-5V, in 1 zone, little crystal grain MIC TFT has tangible leakage current and GIDL, and the GIDL of the little crystal grain MIC of BG TFT obviously is suppressed to～10
-10A and minimum current have also reduced 3.1 times.Shown in Figure 13 (b), γ is showing decline～2 * 10
-2From top contrast, after we can see Application of B G technology, most TFT parameter significantly improved.
Table 2 has the electrical parameter of the little crystal grain MIC of the P type TFT of BG structure and non-BG structure
Figure 13 (a) and (b) shown in be respectively at V
Ds=-0.1V and V
DsUnder the=-5V situation, the mutual conductance of BG little crystal grain MIC TFT and the little crystal grain P of non-BG type MIC TFT.
Figure 14 (a) and (b) shown in be the difference on the P type channel TFT performance, that shown is general little crystal grain MIC TFT and the V of the little crystal grain MIC of BG TFT
ThAnd GIDL.DATA REASONING is evenly distributed on the TFT that surpasses on 4 inches the glass wafer from 96.Clearly, have the TFT of BG structure more much lower than the GIDL value of normal little crystal grain MIC TFT, the otherness of GIDL also is greatly enhanced.Simultaneously, compare with general little crystal grain MIC TFT, the little crystal grain MIC of BG TFT also shows littler V
ThChange.Table 3 has shown the MIC of big crystal grain, the big crystal grain MIC of BG, the V of 4 kinds of TFT such as the little crystal grain MIC of granule MIC and BG
ThUniformity data with GIDL.From comparison, we can find that the uniformity of the bigger crystal grain MIC of little crystal grain MIC TFT TFT is better, also finds same effect between BG big crystal grain MIC TFT and the little crystal grain MIC of the BG TFT.Because it is more that the absolute value of GIDL reduces, BG TFT shows littler GIDL difference.Should be noted that the TFT of little crystal grain MIC demonstrates the littler V of TFT than the little crystal grain MIC of BG
ThStandard deviation.This is because the inhomogeneities of BG line will still need bigger improvement in future.
The big crystal grain of table 3BG and non-BG structure and the uniformity of little crystal grain MIC TFT are relatively
C: sample C (BG SR-MILC TFT)
Shown in Figure 15 (a) is to work as V
Ds=-0.1V and V
DsDuring=-5V, the BG structure is arranged and do not have the transfer characteristic curve of the SR-MILC multi-crystal TFT of BG structure.Shown in Figure 15 (b) is with V
GsAs function, the BG structure is arranged and do not have the output current of the P raceway groove SR-MILC TFT of BG structure to scheme than (γ).Table 4 has been listed the electrical parameter of BG structure and non-BG structure SR-MILC TFT.The subthreshold value amplitude of oscillation (S) of BG structure TFT and non-BG structure SR-MILC TFT is respectively 0.95V/dec and 1.34V/dec.Threshold voltage (the V that the TFT of BG structure is arranged in addition,
Th) absolute value is to have reduced 4.1V, drops to 5.9V.In the 2nd zone, shown in Figure 15 (b), subthreshold value zone, γ significantly increases, and reach peak～100, this is than big 20 times in the γ in the 3rd district value.
The leakage current that another is significantly improved when being the TFT reverse bias is shown in Figure 12 (a).Work as V
Gs=10V and V
Ds=-5V the time, the leakage current of BG SR-MILC TFT is 7.26pA/um, this be general SR-MILC TFT about 1/32.Shown in Figure 15 (a), work as V
Ds=-5V, in 1 zone, SR-MILC TFT has tangible leakage current and GIDL, and the GIDL of BG SR-MILC TFT obviously is suppressed to～2 * 10
-10A and minimum current have also reduced 3 times.Shown in Figure 15 (b), γ is showing decline～3 * 10
-2
Table 4 has the P type SR-MILC multi-crystal TFT electrical parameter of BG structure and non-BG structure
D: anisotropy SR-MILC multi-crystal TFT and homogeneity BG multi-crystal TFT
Present embodiment provides a kind of SR-MILC TFT, and Figure 16 is the regional microgram of the SR-MILC TFT after the etching of TMAH.In the present embodiment, the width of inducing line is 8 microns, and two adjacent, and to induce the distance between the line be 100 microns.The metal inducement side crystallization results from the low angle grain boundary GBS of longated grain and associated, and the low angle grain boundary mainly is along the MILC direction, shown in Figure 16 dotted line circle.Angle between low angle GBS and the horizontal MILC direction is usually less than 30 °.These are orderly relatively different with the LPCVD polysilicon with those SPC with anisotropic microstructure, and nucleation and even grained growth cause isotropic microstructure and electric property at random for they.Adopt traditional LTPS TFT technology to make the TFT of two types P-passage.All TFT have 10 microns identical active channel width (W), with the different channel length (L) that does not wait from 1 micron to 20 microns.In addition, all TFT active channels are positioned at good MILC zone, and the edge that this means each TFT active channel is at least from inducing line and two to induce 7 microns on LLGB line in the middle of the line.A type TFT electric current is parallel to the MILC crystallization direction, and the current vertical of Type B TFT is in the MILC crystallization direction.In addition, the BG line is applied to two kinds of thin-film transistors of A type and Type B perpendicular to the BG structure of the sense of current, to reduce the anisotropy influence of this SR-MILC polysilicon membrane.BG polysilicon membrane as this zebra stripes is repeated to form by intrinsic polysilicon lines of 0.5 μ m parallel to each other and 0.5 μ m boron-doping polysilicon lines.
Figure 17 is that regular SR-MILC multi-crystal TFT is at V
DsTypical logarithmic scale transfer curve during=-5V, wherein, A type TFT electric current is parallel to the MILC crystallization direction, and the current vertical of Type B TFT is in the MILC crystallization direction.Here, the width of TFT and length are respectively 10 μ m and 14 μ m.Except shown in figure 17, overseas with the sub-threshold region that the some circle is represented, all basically TFT show identical transfer curve.For the anisotropy performance of the SR-MILC polycrystalline SiTFT further inquired into, make and carefully measure and studied the TFT of more eurypalynous A type and Type B, the L size from 1 micron to 20 μ m.TFT threshold voltage (V
Th) be defined as and work as V
DsDuring=-0.1V, make I
d=W/L * 10
-9The V of A
GVoltage.In order to give prominence to difference, for A type and Type B TFT, V in the subthreshold value zone
ThExtract and be that function is presented at Figure 18 with L.
Shown in figure 18, as L during less than 2 μ m, A type and Type B TFT show essentially identical V
THValue and standard deviation (SD).In sub-threshold region, I
dBe that main dissufion current and charge carrier are along the high electric guiding path that is provided by good crystal region.The mean breadth of the good crystal grain of elongation of SR-MILC is about 3～5 microns, as shown in Figure 16.As L during less than 2um, for the TFT of A type and Type B, dissufion current is main still a crystal grain the inside to leaking from the source.Therefore, all TFT have shown identical threshold voltage and identical S.D.'s.Along with the increase of passage length, the TFT of A type will show less relatively V than the TFT of Type B
ThThis be because Type B TFT when passage length during greater than 4 μ m, the low angle grain boundary will probably can be dropped on the active channel, its direction is vertical with the sense of current.Low angle grain boundary in the Type B TFT will be an obstacle for dissufion current, makes the V of category-B TFT
ThBig than category-A TFT.
In sub-threshold region, the electrical conductive behavior of polycrystalline SiTFT mainly is to be controlled by thermionic emission.As low angle grain boundary (GB
S) crossbearer when electric current, compare with the situation in the grain boundary, for thermionic emission, the GB crystal boundary can look like a higher potential barrier.When TFT is opened, the conduction behavior mainly is by defective and/or GB scatter control.Figure 19 has shown the I-V curve of typical linear scale of the conventional SR-MILC TFT of A and Type B.Difference between A type and the Type B membrane transistor is to iris out with point.At V
Gs=-18V and V
DsThe aisle resistance rate of the multi-crystal TFT during=-0.1V is extracted and is compared to Figure 20.
The resistivity of the A type TFT passage that the sense of current is parallel with the MILC direction is denoted as ρ
pThe sense of current is denoted as ρ perpendicular to the Type B TFT aisle resistance rate of MILC direction
tAs shown in Figure 20, when L less less than 2 μ m, ρ
pAnd ρ
tBasically be identical, this can be used in the essentially identical V in subthreshold value zone
ThThe reason of value is explained.As L during greater than 4 μ m, ρ
pBecome and compare ρ
tLess.For ρ
tSituation, electric current flows through vertical low angle grain boundary and excites along the continuous charge carrier that conduction orientation is crossed a series of horizontal crystal boundaries is essential.Therefore, electric current is by those low angles GB in the TFT active channel
SLimit.For ρ
pSituation, the sense of current is to be parallel to germination.FOR ALL WE KNOW, the angle between low angle grain boundary and the MILC direction is usually less than 30 degree.Under the situation of W/L＜1/2, in passage area low angle GB might appear
SWith the reduction electricalresistivity
pTherefore, flow of current will be followed the pattern of complications, thereby avoid the low angle GB that in cross conduction, runs into
SYet the low angle grain boundary number of category-A device lacks than category-B type TFT crystal boundary number usually.Therefore, this also is SR-MILC polycrystalline SiTFT ρ
pLess reason.Certainly, the anisotropic conductive characteristic of SR-MILC polysilicon membrane will cause the TFT of lack of homogeneity.Figure 21 and Figure 22 show the V of extraction
ThWith the A type of BG structure and the resistivity of Type B TFT.The BG line cycle is 1 micron.As L during less than 4 μ m, the BG structure is not obviously improved.For L during greater than 4 μ m, different with Figure 18 and category-A, category-B TFT shown in Figure 20, the BG structure is arranged, the difference of A type and Type B TFT can be reduced, and shows better uniformity.This is because the low angle grain boundary between the long little die region of two folders in the TFT passage is doped BG structure-steel framing spanning mistake.Therefore, use the BG structure, the effect of anisotropy of SR-MILC polysilicon membrane can be eliminated effectively.
Although the utility model is made specific descriptions with reference to the above embodiments; But for the person of ordinary skill of the art; Above embodiment is only in order to the technical scheme of describing the utility model but not the present technique method is limited; The utility model can extend to other modification, variation, application and embodiment on using, and therefore thinks that all such modifications, variation, application, embodiment are in the spirit and teachings of the utility model.
Claims (4)
1. an Active Matrix Display comprises a plurality of thin-film transistors, and wherein each thin-film transistor comprises:
Active layer is made up of polysilicon membrane, has parallel conductive strips or conductor wire in this polysilicon membrane, and said conductive strips or conductor wire connect a plurality of crystal grain;
Source electrode on the active layer and drain electrode;
Gate insulator;
Grid;
It is characterized in that said conductive strips or conductor wire are made up of the lines that mix; The parallel conductive strips or the direction of conductor wire are perpendicular to the sense of current.
2. Active Matrix Display according to claim 1; It is characterized in that; Comprise P type thin-film transistor and N type thin-film transistor in a plurality of thin-film transistors that comprise; Wherein conductive strips in the polysilicon membrane of the formation active layer of P type thin-film transistor or conductor wire are made up of the lines of boron-doping, and conductive strips or conductor wire in the polysilicon membrane of the formation active layer of N type thin-film transistor are made up of the lines of mixing phosphorus.
3. Active Matrix Display according to claim 1 is characterized in that the width of a plurality of conductive strips or conductor wire and spacing and grain size are similar.
4. Active Matrix Display according to claim 1 is characterized in that, constitutes in the polysilicon membrane of active layer, and in the lines of doping, the doping peak on the polysilicon membrane thickness direction is positioned at the center of polysilicon membrane thickness.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120577247 CN202405260U (en) | 2011-08-23 | 2011-12-31 | Active matrix display |
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110243267 | 2011-08-23 | ||
| CN201110243267.X | 2011-08-23 | ||
| CN201110256340.7 | 2011-09-01 | ||
| CN201110256340 | 2011-09-01 | ||
| CN 201120577247 CN202405260U (en) | 2011-08-23 | 2011-12-31 | Active matrix display |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202405260U true CN202405260U (en) | 2012-08-29 |
Family
ID=46702891
Family Applications (17)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011103519844A Pending CN102956499A (en) | 2011-08-23 | 2011-11-09 | Preparation method of polysilicon film |
| CN201110351983XA Pending CN102956678A (en) | 2011-08-23 | 2011-11-09 | Polysilicon film |
| CN 201120440884 Expired - Fee Related CN202405261U (en) | 2011-08-23 | 2011-11-09 | Mask MIC TFT film |
| CN2011103520076A Pending CN102956500A (en) | 2011-08-23 | 2011-11-09 | Preparation method of polysilicon thin-film transistor |
| CN2011103519859A Pending CN102956710A (en) | 2011-08-23 | 2011-11-09 | Mask metal induced crystallized polycrystalline silicon thin-film transistor |
| CN201110461881.3A Pending CN103762175A (en) | 2011-08-23 | 2011-12-31 | Preparation method for polysilicon thin film with bridged crystal-grain structure |
| CN201110461884.7A Pending CN103779391A (en) | 2011-08-23 | 2011-12-31 | Polycrystalline silicon thin film with bridging grain structure and preparation method thereof |
| CN201110461863.5A Pending CN103762172A (en) | 2011-08-23 | 2011-12-31 | Preparation method of polysilicon thin film with bridged-grain structure |
| CN201110461873.9A Pending CN103779209A (en) | 2011-08-23 | 2011-12-31 | Method for preparing polycrystalline silicon thin-film transistor |
| CN201110461864.XA Pending CN103762173A (en) | 2011-08-23 | 2011-12-31 | Method for preparing polysilicon thin film |
| CN201110461875.8A Pending CN103779420A (en) | 2011-08-23 | 2011-12-31 | Polycrystalline silicon thin-film transistor with bridging grain structure |
| CN201110461883.2A Pending CN103762176A (en) | 2011-08-23 | 2011-12-31 | Preparation method for polysilicon thin film with bridged crystal-grain structure |
| CN201110461865.4A Pending CN103762174A (en) | 2011-08-23 | 2011-12-31 | Preparation method for thin-film transistor |
| CN 201120577247 Expired - Fee Related CN202405260U (en) | 2011-08-23 | 2011-12-31 | Active matrix display |
| CN2012100512458A Pending CN102956549A (en) | 2011-08-23 | 2012-03-01 | Manufacturing method of active matrix backing plate of field sequential color liquid crystal display |
| CN2012100512443A Pending CN102956648A (en) | 2011-08-23 | 2012-03-01 | Active matrix rear panel with liquid crystal display |
| CN2012100513018A Pending CN102955307A (en) | 2011-08-23 | 2012-03-01 | Field sequential color liquid crystal display based on polycrystalline silicon thin film transistor |
Family Applications Before (13)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011103519844A Pending CN102956499A (en) | 2011-08-23 | 2011-11-09 | Preparation method of polysilicon film |
| CN201110351983XA Pending CN102956678A (en) | 2011-08-23 | 2011-11-09 | Polysilicon film |
| CN 201120440884 Expired - Fee Related CN202405261U (en) | 2011-08-23 | 2011-11-09 | Mask MIC TFT film |
| CN2011103520076A Pending CN102956500A (en) | 2011-08-23 | 2011-11-09 | Preparation method of polysilicon thin-film transistor |
| CN2011103519859A Pending CN102956710A (en) | 2011-08-23 | 2011-11-09 | Mask metal induced crystallized polycrystalline silicon thin-film transistor |
| CN201110461881.3A Pending CN103762175A (en) | 2011-08-23 | 2011-12-31 | Preparation method for polysilicon thin film with bridged crystal-grain structure |
| CN201110461884.7A Pending CN103779391A (en) | 2011-08-23 | 2011-12-31 | Polycrystalline silicon thin film with bridging grain structure and preparation method thereof |
| CN201110461863.5A Pending CN103762172A (en) | 2011-08-23 | 2011-12-31 | Preparation method of polysilicon thin film with bridged-grain structure |
| CN201110461873.9A Pending CN103779209A (en) | 2011-08-23 | 2011-12-31 | Method for preparing polycrystalline silicon thin-film transistor |
| CN201110461864.XA Pending CN103762173A (en) | 2011-08-23 | 2011-12-31 | Method for preparing polysilicon thin film |
| CN201110461875.8A Pending CN103779420A (en) | 2011-08-23 | 2011-12-31 | Polycrystalline silicon thin-film transistor with bridging grain structure |
| CN201110461883.2A Pending CN103762176A (en) | 2011-08-23 | 2011-12-31 | Preparation method for polysilicon thin film with bridged crystal-grain structure |
| CN201110461865.4A Pending CN103762174A (en) | 2011-08-23 | 2011-12-31 | Preparation method for thin-film transistor |
Family Applications After (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012100512458A Pending CN102956549A (en) | 2011-08-23 | 2012-03-01 | Manufacturing method of active matrix backing plate of field sequential color liquid crystal display |
| CN2012100512443A Pending CN102956648A (en) | 2011-08-23 | 2012-03-01 | Active matrix rear panel with liquid crystal display |
| CN2012100513018A Pending CN102955307A (en) | 2011-08-23 | 2012-03-01 | Field sequential color liquid crystal display based on polycrystalline silicon thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (17) | CN102956499A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104241395A (en) * | 2014-09-10 | 2014-12-24 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and displaying device |
| CN106601873A (en) * | 2016-12-16 | 2017-04-26 | 中利腾晖光伏科技有限公司 | CZTS film applied spin coating apparatus and method for preparing CZTS battery |
| CN106876479A (en) * | 2017-04-19 | 2017-06-20 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte and preparation method thereof, display panel |
| US9793361B2 (en) | 2014-09-10 | 2017-10-17 | Boe Technology Group Co., Ltd. | Thin film transistor, array substrate and display device |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103151388B (en) * | 2013-03-05 | 2015-11-11 | 京东方科技集团股份有限公司 | A kind of polycrystalline SiTFT and preparation method thereof, array base palte |
| CN103235439B (en) * | 2013-04-08 | 2015-08-12 | 北京京东方光电科技有限公司 | A kind of to box substrate and preparation method, touch-screen, display device |
| CN104282546A (en) * | 2013-07-08 | 2015-01-14 | 上海和辉光电有限公司 | Method for improving homogeneity of polycrystalline silicon layer |
| CN103700688B (en) * | 2013-12-23 | 2016-03-30 | 京东方科技集团股份有限公司 | Color membrane substrates and preparation method thereof, display unit |
| CN103700698B (en) | 2013-12-30 | 2016-06-15 | 北京京东方光电科技有限公司 | The preparation method of a kind of thin film transistor, thin film transistor and display panel |
| CN105514023B (en) * | 2014-09-22 | 2018-07-24 | 上海和辉光电有限公司 | A kind of contact hole interface processing method |
| CN104505340B (en) * | 2014-11-28 | 2017-12-26 | 信利（惠州）智能显示有限公司 | A kind of preparation method of low-temperature polysilicon film |
| CN106033707A (en) * | 2015-03-10 | 2016-10-19 | 上海和辉光电有限公司 | Preparation method for polysilicon film |
| CN105575974B (en) * | 2015-12-14 | 2018-08-14 | 深圳市华星光电技术有限公司 | The production method of low temperature polycrystalline silicon TFT backplate |
| CN106298802B (en) * | 2016-08-16 | 2019-05-07 | 武汉华星光电技术有限公司 | A kind of LTPS array substrate and manufacturing method, display panel |
| CN106328506B (en) * | 2016-08-31 | 2020-04-10 | 上海华力微电子有限公司 | Method for reducing photoresist stripping risk of ion implantation layer |
| WO2018126358A1 (en) * | 2017-01-04 | 2018-07-12 | 曾世宪 | Pixel unit structure and manufacturing method thereof |
| CN109742028B (en) * | 2018-12-25 | 2021-04-02 | 惠科股份有限公司 | Manufacturing method of thin film transistor, thin film transistor and display panel |
| DE102019100312A1 (en) * | 2019-01-08 | 2020-07-09 | Parcan NanoTech Co. Ltd. | Controlled ion implantation substrate and method of making a controlled ion implantation substrate |
| CN112736087B (en) * | 2019-10-10 | 2024-03-05 | 京东方科技集团股份有限公司 | Manufacturing method of array substrate, array substrate and display panel |
| CN110660869A (en) * | 2019-10-27 | 2020-01-07 | 南京飞芯电子科技有限公司 | Method for forming enhancement mode field effect transistor |
| CN112563197B (en) * | 2020-11-24 | 2022-03-22 | 惠科股份有限公司 | Active switch, manufacturing method thereof and display panel |
Family Cites Families (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5783047A (en) * | 1980-11-10 | 1982-05-24 | Matsushita Electric Ind Co Ltd | Polycrystalline semiconductor resistor |
| TW520072U (en) * | 1991-07-08 | 2003-02-01 | Samsung Electronics Co Ltd | A semiconductor device having a multi-layer metal contact |
| JPH06104438A (en) * | 1992-09-22 | 1994-04-15 | Casio Comput Co Ltd | Film transistor |
| JPH08139335A (en) * | 1994-11-14 | 1996-05-31 | Casio Comput Co Ltd | Method of manufacturing thin film transistor |
| US6108058A (en) * | 1997-04-30 | 2000-08-22 | Tohoku Techno-Brains Corporation | Field sequential Pi cell LCD with compensator |
| JPH11354800A (en) * | 1998-06-04 | 1999-12-24 | Hitachi Ltd | Thin-film transistor, its forming method, and liquid crystal display device |
| JP4436469B2 (en) * | 1998-09-30 | 2010-03-24 | 三洋電機株式会社 | Semiconductor device |
| JP2000133807A (en) * | 1998-10-22 | 2000-05-12 | Seiko Epson Corp | Polycrystalline silicon thin-film transistor |
| JP2000208771A (en) * | 1999-01-11 | 2000-07-28 | Hitachi Ltd | Semiconductor device, liquid cystal display device, and their manufacturing |
| TWI243432B (en) * | 1999-10-29 | 2005-11-11 | Hitachi Ltd | Semiconductor device, method of making the same and liquid crystal display device |
| JP3873811B2 (en) * | 2002-05-15 | 2007-01-31 | 日本電気株式会社 | Manufacturing method of semiconductor device |
| KR100930362B1 (en) * | 2002-11-04 | 2009-12-08 | 엘지디스플레이 주식회사 | Polycrystalline Silicon Film Formation Method And Manufacturing Method Of Thin Film Transistor Including The Same |
| KR100577795B1 (en) * | 2003-12-30 | 2006-05-11 | 비오이 하이디스 테크놀로지 주식회사 | Method for forming polycrystalline silicon film |
| TWI266427B (en) * | 2004-06-01 | 2006-11-11 | Yamanashi Tlo Co Ltd | Field-effect transistor and method of manufacturing same |
| TWI241027B (en) * | 2004-09-30 | 2005-10-01 | Ind Tech Res Inst | Method of preparing electronic device |
| US8088676B2 (en) * | 2005-04-28 | 2012-01-03 | The Hong Kong University Of Science And Technology | Metal-induced crystallization of amorphous silicon, polycrystalline silicon thin films produced thereby and thin film transistors produced therefrom |
| US8013957B2 (en) * | 2005-05-21 | 2011-09-06 | The Hong Kong University Of Science And Technology | Transflective liquid crystal device and method of manufacturing the same |
| US7790580B2 (en) * | 2006-03-13 | 2010-09-07 | Hong Kong University Of Science And Technology | Metal-induced crystallization of amorphous silicon in thin film transistors |
| KR101426982B1 (en) * | 2007-06-22 | 2014-08-06 | 더 홍콩 유니버시티 오브 사이언스 앤드 테크놀러지 | Polycrystalline silicon thin film transistors with bridged-grain structures |
| JP5295529B2 (en) * | 2007-08-13 | 2013-09-18 | 株式会社ジャパンディスプレイ | Semiconductor device |
| CN101834211A (en) * | 2010-02-09 | 2010-09-15 | 广东中显科技有限公司 | Polycrystalline silicon thin film based on metal induction |
| CN101834138A (en) * | 2010-02-09 | 2010-09-15 | 广东中显科技有限公司 | Method for preparing transistor device of crystallized thin film |
| CN101814438A (en) * | 2010-05-17 | 2010-08-25 | 广东中显科技有限公司 | Preparation method of thin film transistor based on induced longitudinal crystallization polycrystalline silicon |
| CN101853784B (en) * | 2010-05-17 | 2012-07-04 | 广东中显科技有限公司 | Method for transversely inducing and crystallizing low-temperature polycrystalline silicon film |
| CN101819999A (en) * | 2010-05-17 | 2010-09-01 | 广东中显科技有限公司 | Multilayer film structure for transverse induced crystallization of low-temperature poly-silicon film |
| CN102129962A (en) * | 2010-10-28 | 2011-07-20 | 广东中显科技有限公司 | Controllable method for manufacturing polysilicon thin film through metal induction |
| CN102082098A (en) * | 2010-12-15 | 2011-06-01 | 四川虹视显示技术有限公司 | Method for producing low-temperature polysilicon thin-film transistor |
-
2011
- 2011-11-09 CN CN2011103519844A patent/CN102956499A/en active Pending
- 2011-11-09 CN CN201110351983XA patent/CN102956678A/en active Pending
- 2011-11-09 CN CN 201120440884 patent/CN202405261U/en not_active Expired - Fee Related
- 2011-11-09 CN CN2011103520076A patent/CN102956500A/en active Pending
- 2011-11-09 CN CN2011103519859A patent/CN102956710A/en active Pending
- 2011-12-31 CN CN201110461881.3A patent/CN103762175A/en active Pending
- 2011-12-31 CN CN201110461884.7A patent/CN103779391A/en active Pending
- 2011-12-31 CN CN201110461863.5A patent/CN103762172A/en active Pending
- 2011-12-31 CN CN201110461873.9A patent/CN103779209A/en active Pending
- 2011-12-31 CN CN201110461864.XA patent/CN103762173A/en active Pending
- 2011-12-31 CN CN201110461875.8A patent/CN103779420A/en active Pending
- 2011-12-31 CN CN201110461883.2A patent/CN103762176A/en active Pending
- 2011-12-31 CN CN201110461865.4A patent/CN103762174A/en active Pending
- 2011-12-31 CN CN 201120577247 patent/CN202405260U/en not_active Expired - Fee Related
-
2012
- 2012-03-01 CN CN2012100512458A patent/CN102956549A/en active Pending
- 2012-03-01 CN CN2012100512443A patent/CN102956648A/en active Pending
- 2012-03-01 CN CN2012100513018A patent/CN102955307A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104241395A (en) * | 2014-09-10 | 2014-12-24 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and displaying device |
| WO2016037435A1 (en) * | 2014-09-10 | 2016-03-17 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and display device |
| CN104241395B (en) * | 2014-09-10 | 2017-02-15 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and displaying device |
| US9793361B2 (en) | 2014-09-10 | 2017-10-17 | Boe Technology Group Co., Ltd. | Thin film transistor, array substrate and display device |
| CN106601873A (en) * | 2016-12-16 | 2017-04-26 | 中利腾晖光伏科技有限公司 | CZTS film applied spin coating apparatus and method for preparing CZTS battery |
| CN106876479A (en) * | 2017-04-19 | 2017-06-20 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte and preparation method thereof, display panel |
| WO2018192217A1 (en) * | 2017-04-19 | 2018-10-25 | 京东方科技集团股份有限公司 | Thin-film transistor and preparation method therefor, array substrate and preparation method therefor, and display panel |
| CN106876479B (en) * | 2017-04-19 | 2020-03-06 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method thereof, array substrate and preparation method thereof, and display panel |
| US11296235B2 (en) | 2017-04-19 | 2022-04-05 | Boe Technology Group Co., Ltd. | Thin film transistor having a wire grid on a channel region and manufacturing method thereof, array substrate and manufacturing method thereof, and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103762175A (en) | 2014-04-30 |
| CN103762176A (en) | 2014-04-30 |
| CN103779209A (en) | 2014-05-07 |
| CN102956549A (en) | 2013-03-06 |
| CN103762174A (en) | 2014-04-30 |
| CN102956499A (en) | 2013-03-06 |
| CN102956678A (en) | 2013-03-06 |
| CN103762172A (en) | 2014-04-30 |
| CN102956648A (en) | 2013-03-06 |
| CN103779420A (en) | 2014-05-07 |
| CN102956500A (en) | 2013-03-06 |
| CN102956710A (en) | 2013-03-06 |
| CN103762173A (en) | 2014-04-30 |
| CN202405261U (en) | 2012-08-29 |
| CN102955307A (en) | 2013-03-06 |
| CN103779391A (en) | 2014-05-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN202405260U (en) | Active matrix display | |
| KR101426982B1 (en) | Polycrystalline silicon thin film transistors with bridged-grain structures | |
| CN100355044C (en) | Semiconductor thin film, Semiconductor device and mfg. method thereof | |
| CN107507841A (en) | Array base palte and preparation method thereof, display device | |
| EP2736077A1 (en) | Array substrate and method for fabricating array substrate, and display device | |
| CN104282696B (en) | A kind of array substrate and preparation method thereof, display device | |
| CN107482066A (en) | Thin film transistor (TFT) and preparation method thereof, array base palte and display device | |
| CN105304500A (en) | Manufacture method of N-type TFT (Thin Film Transistor) | |
| CN104681624A (en) | Monocrystalline silicon substrate TFT device | |
| CN107818986A (en) | Semiconductor device and its manufacture method and display device and its manufacture method | |
| CN106328592A (en) | Thin film transistor and manufacturing method, the array substrate and display device | |
| CN104241299A (en) | Oxide semiconductor TFT substrate manufacturing method and oxide semiconductor TFT substrate structure | |
| CN106298645B (en) | A kind of preparation method of TFT substrate | |
| CN104465509B (en) | A kind of OLED display device array base palte and preparation method thereof | |
| CN105551967B (en) | The production method of N-type TFT | |
| CN107342297A (en) | Thin-film transistor array base-plate and preparation method thereof, display device | |
| CN207503977U (en) | array substrate, display panel and display device | |
| CN204130536U (en) | A kind of array base palte and display unit | |
| CN106057677B (en) | The production method of low-temperature polysilicon film transistor | |
| CN104599973A (en) | Preparation method of low-temperature polycrystalline silicon thin film transistor | |
| CN104934444A (en) | Coplane oxide semiconductor TFT substrate composition and manufacturing method thereof | |
| CN103258855A (en) | Polycrystalline silicon thin film transistor based on solid-phase crystallization technology and manufacturing method thereof | |
| CN205069643U (en) | Membrane transistor, array substrate and display device | |
| CN103123902A (en) | Semiconductor layer structure, polysilicon thin film transistor, manufacturing method and display device | |
| CN108933146A (en) | A kind of array substrate and preparation method thereof, liquid crystal display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120829 Termination date: 20121231 |