CN202405260U - Active matrix display - Google Patents

Abstract

The utility model provides an active matrix display, which comprises a plurality of thin film transistors, wherein each thin film transistor comprises an active layer, a source, a drain, a gate insulating layer and a gate; the active layer is made of a polycrystalline silicon thin film; parallel conductive strips or parallel conductive wires are arranged in the polycrystalline silicon thin film and connected with a plurality of crystal grains; the source and the drain are arranged on the active layer; each conductive strip or each conductive wire consists of doped lines; and the direction of each of the parallel conductive strips or the parallel conductive wires is perpendicular to that of current.

Description

An active matrix display

technical field

The utility model relates to polysilicon technology, in particular to an active matrix display.

Background technique

In the field of traditional active matrix display, TFT is usually made of amorphous silicon (a-Si) material. This is mainly due to its low processing temperature and low manufacturing cost on large-area glass substrates. More recently polysilicon is used in high resolution liquid crystal displays (LCDs) and active organic electroluminescent displays (AMOLEDs). Polysilicon also has the advantage of integrating circuits on glass substrates. In addition, polysilicon has the possibility of a larger pixel aperture ratio, improving light energy utilization efficiency and reducing power consumption in LC and bottom-emitting OLED displays. It is well known that polysilicon TFTs are more suitable for driving OLED pixels, not only because OLEDs are current-driven devices, and a-Si TFTs have long-term reliability issues in driving OLEDs, but also because amorphous silicon has a smaller electron mobility and requires a large W/ L ratio to provide sufficient OLED pixel drive current. Therefore, for high-definition displays, high-quality polysilicon TFTs are essential.

In order to realize the industrial production of active matrix TFT display panels, a very high quality polysilicon film is required. It needs to meet the requirements of low-temperature processing on a large-area glass substrate, low-cost manufacturing, stable manufacturing process, high performance, high uniformity and high reliability of device performance.

High-temperature polysilicon technology can be used to realize high-performance TFTs, but it cannot be applied to common glass substrates used in commercial panels. In this case, low temperature polysilicon (LTPS) must be used. There are three main LTPS techniques: (1) solid-phase crystallization (SPC) annealed at 600 °C for a long period of time; (2) excimer laser crystallization, annealing (ELC/ELA) or rapid thermal annealing; (3) metal Induced Crystallization (MIC). ELC can produce the best results, but is limited by high equipment investment and maintenance costs, and it is difficult to further increase the size of the glass substrate. SPC is the cheapest technique, but requires about 24 hours of annealing at 600°C to crystallize. The disadvantages of MIC are metal contamination and non-uniformity of TFT devices. Thus, there is no single technology that can satisfy all the above-mentioned low-cost and high-performance requirements.

Common to all polysilicon thin film materials is that the size and shape of the crystallographic directions of the grains on the film are randomly distributed in nature. When such a polysilicon thin film is used as an active layer of a TFT, the electrical characteristics of the TFT are limited by the grain boundaries present in the channel. The distribution of crystal grains is random, making the electrical characteristics of the TFTs across the substrate non-uniform. It is this discrete distribution of electrical characteristics that causes defects such as mura and non-uniform brightness in the final display.

Utility model content

In order to overcome the above defects, the present application proposes an active matrix display comprising a plurality of thin film transistors, wherein each thin film transistor comprises: an active layer made of a polysilicon film with parallel conductive strips or conductive lines in the polysilicon film, The conductive strips or conductive lines connect a plurality of crystal grains; the source and drain electrodes on the active layer; the gate insulating layer; the gate; the conductive strips or conductive lines are composed of doped lines; parallel conductive strips Or the direction of the conductive line is perpendicular to the direction of current flow.

The plurality of thin film transistors included include P-type thin film transistors and N-type thin film transistors, wherein the conductive strips or conductive lines in the polysilicon film that constitutes the active layer of the P-type thin film transistors are composed of boron-doped lines, and the N-type thin film transistors The conductive bands or lines in the polysilicon thin film constituting the active layer consist of lines doped with phosphorous.

The width and spacing of the plurality of conductive strips or lines is similar to the grain size.

In the polysilicon film constituting the active layer, in the doped lines, the doping peak in the thickness direction of the polysilicon film is located at the center of the polysilicon film thickness.

Using this BG polysilicon layer as the active layer ensures that the current flows vertically through the parallel-line TFT design, and the influence of grain boundaries can be reduced. Important properties such as threshold voltage, switching ratio, device mobility, uniformity across the substrate, subthreshold slope, and device reliability can all be improved using this technology today. These improvements can also make the cost lower and the price lower, making high-performance LTPS TFT a reality.

Description of drawings

The utility model embodiment is described further below with reference to accompanying drawing, wherein:

Figure 1a and Figure 1b are schematic diagrams of low-temperature polysilicon thin films and corresponding potential barrier distributions, respectively;

Figure 2a and Figure 2b are schematic diagrams of the bridge grain polysilicon film and the corresponding potential barrier distribution;

3 is a schematic cross-sectional view of forming a BG line structure;

Figure 4 is a SEM picture of a BG line pattern with a period of 1 μm formed by PR1075;

Figures 5a, 5b and 5c are schematic cross-sectional views of sample A, sample B and sample C crystallization, respectively;

Figure 6 is a schematic cross-sectional view of all samples after forming BG lines through photoresist and ion implantation;

Figures 7a, 7b and 7c are photomicrographs of large-grain polysilicon, small-grain polysilicon and SR-MILC polysilicon etched by TMAH;

Figure 8 is a schematic cross-sectional view of the BG TFT structure;

Figure _9a shows the transfer characteristic curves of P-channel large-grain MIC TFTs with and without BG as a function of V _gs , and Figure 9b shows the transfer characteristics of P-channel large-grain MIC TFTs with and without BG as a function of V gs TFT output current ratio diagram;

Figures 10a and 10b show the transconductance of BG large-grain MIC TFT and non-BG large-grain MIC TFT under the conditions of V _ds =-0.1V and V _ds =-5V;

Figures 11a and 11b show the V _th and GIDL performance differences of TFTs of uniformly distributed 50 large-grain MIC TFTs and 50 BG large-grain MIC TFTs, respectively;

Figures 12a and _12b are the transfer characteristic curves of P-type small-grain MIC polysilicon TFTs with and without BG structure as a function of V gs, and with and without BG structure as a function of V _gs , respectively. The output current ratio of P-type small-grain MIC polysilicon TFT;

Figures 13a and 13b show the transconductance of BG small-grain MIC TFT and non-BG small-grain MIC TFT at V _ds =-0.1V and V _ds =-5V, respectively;

Figures 14a and 14b show the differences in Vth and GIDL performance of uniformly distributed small-grain MIC TFTs and BG small-grain MICTFTs, respectively;

Figures 15a and 15b show the transfer characteristic curves of P-channel SR-MILCTFTs with and without BG structure as a function of _Vgs , and the P-channel SR with and without BG structure as a function of _Vgs , respectively. - output current ratio of MILCTFTs;

Figure 16 is the regional microscopic view of SR-MILC polysilicon after TMAH etching. It can be seen that the crystal grains and their low-angle grain boundaries are basically parallel to the MILC direction, and the current directions of A-type and B-type TFTs have been marked with dot coils. and perpendicular to the MILC direction;

Figure 17 shows the characteristic logarithmic ratio curves of general A-type and B-type SR-MILC TFTs, the main difference lies in the subthreshold region;

Figure 18 is the average value and standard deviation (S.D.) of Vth extracted from Type A and Type B TFTs as a function of channel length;

Figure 19 is the I-V curve of the characteristic linear scale of the conventional SR-MILC TFT of type A and B, and it can be seen that there is the largest difference in the open state;

Figure 20 is when Vds=-0.1V and Vgs=-18V, the extraction resistivity of type A and type B poly-Si TFTs;

Figure 21 is the Vth of A-type and B-type TFTs of BG structure;

Fig. 22 is the resistivity of A-type and B-type TFTs of BG structure.

Detailed ways

Typically, polysilicon consists of two parts, a single grain region and a grain boundary. The conduction characteristics within the grains are almost the same, while the conduction across grain boundaries is poor, which leads to a loss of overall mobility and an increase in threshold voltage. The active channel of a thin film transistor (TFT) of polysilicon film usually consists of such a polysilicon film. Random and varying conductivity characteristics are detrimental to display performance and picture quality. A typical polysilicon structure diagram is shown in Figure 1a. The low-temperature polysilicon film includes grains and grain boundaries. There are obvious grain boundaries between adjacent grains. Usually, the length of the grain is between tens of nanometers and several micrometers in size, and it is considered as a single crystal. Grain boundaries are usually distributed with many dislocations, stacking failures and dangling bond defects. Due to different preparation methods, the grains in the low-temperature polysilicon film may be randomly distributed or directional.

The presence of severe defects at grain boundaries will cause high potential barriers, as shown in Fig. 1b. The carrier transport in the vertical direction of the barrier (or the vertical component of the sloped barrier) will affect the initial state and current carrying capacity. The threshold voltage and field effect mobility of thin film transistors prepared by the low-temperature polysilicon film are limited by the grain boundary barrier. When the grain boundary that acts as a connection is applied to a TFT, it will also cause a large leakage current under a high back gate voltage.

Bridging grain (BG) polysilicon technology is a technology that connects the grains by using parallel conductive strips or lines in the active layer of the TFT. Forming conductive bands or crossing lines of crystal grains through which current flows in a vertical direction can greatly improve the performance of TFTs. These crossing lines can reduce the effect of crystal grain boundaries, as shown in Fig. 2(b). This structure is defined as the bridge grain (BG) structure.

The "bridge" is composed of parallel highly doped lines, which we call BG lines. The BG lines formed on the polysilicon film should be narrow and very close to each other. The line width and spacing should be similar to the grain size. Conductive lines should not touch each other and should cover the entire polysilicon film for later processing. The main function of the BG wire is to bridge between the grains perpendicular to the direction of current flow. Therefore, the flow of current along these lines is no longer a significant issue.

FIG. 2a is a schematic diagram of a polysilicon thin film with a bridging grain structure shown. Conductive wires are perpendicular to the direction of current flow. These conductive lines can be formed with p- or n-type doped semiconductor dopant ions. The amount of doping can be adjusted to create conductive channels, typically in the range of 10 ¹² /cm ² to 10 ¹⁶ /cm ² . Doping patterns can be performed by various methods, such as simple photolithography, laser interference, or nanoimprint lithography.

Example 1

This embodiment provides a method for forming a polysilicon film with bridging grain (BG) lines, including:

1) A layer of PR 1075 photoresist is spin-coated on the surface of the polysilicon film. After the PR photoresist is spin-coated, the sample is heated to 90 degrees for soft baking. The heating time is 1 minute. The purpose of soft baking is to reduce the amount of photoresist. Solvent, from ~20% to ~5%, release the stress that induces the spin-coated film at the same time, after soft baking, use ASM PAS5000 stepper photolithography machine to expose the photoresist under the light with a wavelength of 365nm, and bake at 110°C After 1 minute, the sample was soaked in FHD-5 for 30 seconds for developing treatment. The photoresist exposed to the light was dissolved in the solution, and the part that was not exposed to the light remained as it was, so that the BG line pattern was transferred to the light. On the resist (as shown in Figure 3), a BG line pattern with a period of 1 μm is formed (the SEM photo of which is shown in Figure 4);

2) After hard baking at 120°C, the samples were sent to CF3000 for ion implantation.

The ASML 5000 stepper of NFF (The Nanoelectronics Fabrication Facility) has a ratio of 5 to 1, which ensures a minimum line width and a minimum spacing of 0.5 μm. Therefore, the lowest line period is limited to 1 μm.

In this embodiment, BG lines composed of doped polysilicon parallel lines with a single repetition period of 1 μm are obtained through two steps of generating BG patterns by photolithography and ion implantation.

In other embodiments, the BG lines may also be formed on the amorphous silicon first and then the amorphous silicon is crystallized into polysilicon, that is, the BG lines may be formed before or after the crystallization.

Compared with the method of first crystallizing amorphous silicon and then forming BG lines on polysilicon, this method of doping amorphous silicon to form BG lines and recrystallization has at least the following advantages: P-type doping can promote the crystallization of amorphous silicon during annealing; since the dopant substance will diffuse during the crystallization of amorphous silicon, this can be used to better control the ratio of the doped region to the non-doped region, Further reduce the probability of the grain boundary existing in the non-doped region, and at the same time reduce the risk of short circuit; moreover, since the annealing process is after doping, the dopant is also activated while crystallizing the amorphous silicon.

Example 2

This embodiment provides a method for forming a polysilicon film with bridging grain (BG) lines, including:

1) On an Eagel2000 glass substrate, 300 nm of silicon oxide (SiO ₂ ) was deposited using plasma enhanced chemical vapor deposition (PEVCD). Then use low-pressure chemical vapor deposition (LPCVD) to deposit 45 nanometers of a-Si at 550 ° C;

2) After immersing in 1% hydrofluoric acid solution (HF) for 1 minute to remove the natural oxide layer, put it into an oxidizing environment with a temperature of 550 degrees for 15 minutes to form a layer of SiO ₂ nano-oxidation on the surface of a-Si layer;

3) Sputter a layer of slow-release (SR) nickel/silicon oxide source layer on the nano-layer for metal-induced crystallization, using nickel-silicon alloy as the target material, the ratio of nickel to silicon is: Ni:Si=1:9, sputtering It is carried out in a mixed environment of argon and oxygen at a ratio of 200:1, the sputtering DC power supply is 7W, and the sputtering time is 90 seconds;

4) Heating at 590°C for 6 hours under _N2 atmosphere until a-Si is completely crystallized. Figure 5a is a schematic cross-sectional view of the crystallization scheme;

5) Soak in the mixed solution H ₂ SO ₄ +H ₂ O ₂ at 120° C. for 10 minutes to remove residual nickel on the surface. Then soak in 1% hydrofluoric acid (HF) for 1 minute to remove the nano-coating, and then deposit 100nm of LTO;

6) Use the ASM PAS5000 stepper photolithography machine with a wavelength of 365nm described in Example 1 to form a BG pattern, and the BG line period is 1 micron.

7) After baking at 120°C for 30 minutes, use boron as BG doping at 40KeV energy and 2E15/ ^cm2 dose for all P-channel TFTs, and phosphorus as BG doping for all N-type TFTs , the BG doping here is carried out through two steps, the dose in each step is 1E15/cm ² , the implantation energy is 80KeV and 130KeV respectively, and the structure shown in Figure 6 is obtained;

8) Use oxygen plasma to strip the photoresist at 100 degrees Celsius for 30 minutes. After removing the PR photoresist, 100nm of LTO is also removed using 777 wet etching. After the BG step is completed, the entire partially doped polysilicon film can be called BG-poly-Si, which can be used for the TFT active layer.

During metal-induced crystallization using the slow-release nickel/silicon oxide source layer, the slow-release nickel/silicon oxide source serves only as a supplementary source of nickel at a relatively slow rate. The nickel in this nickel-inducing source is slowly provided by the reaction of silicon and nickel-silicon oxide, which is very different from the pure nickel source that provides a large number of pure nickel atoms. Therefore, the amount of nickel provided by nickel oxide is less than that of pure nickel source, and this slow release of nickel in polysilicon will reduce the residual nickel content.

The internal structure of the film shown in Figure 7a after the polysilicon film obtained in step 4) of the method provided in this embodiment is etched by tetramethylammonium hydroxide (TMAH) etching solution at room temperature is shown in Figure 7a. Polysilicon is large-grain polysilicon characterized by high mobility, low cost, and low-temperature annealing.

Example 3

This embodiment provides a method for forming a polysilicon film with bridging grain (BG) lines, including:

1) On an Eagel2000 glass substrate, 300 nm of silicon oxide (SiO ₂ ) was deposited using plasma enhanced chemical vapor deposition (PEVCD). Then use low-pressure chemical vapor deposition (LPCVD) to deposit 45 nanometers of a-Si at 550 ° C;

2) Immerse in 1% hydrofluoric acid solution (HF) for 1 minute to remove the natural oxide layer, then immerse in a mixed solution of H ₂ SO ₄ +H ₂ O ₂ at a temperature of 120 degrees for 10 minutes to make a-Si A layer of _SiO2 nanometer layer is formed on the surface;

3) Sputter a layer of slow-release (SR) nickel/silicon oxide source layer on the nano-layer for metal-induced crystallization, using nickel-silicon alloy as the target material, the ratio of nickel to silicon is: Ni:Si=1:9, sputtering It is carried out in a mixed environment of argon and oxygen at a ratio of 200:1, the sputtering DC power supply is 7W, and the sputtering time is 2 minutes;

4) Heating at 590°C for 6 hours under _N2 atmosphere until the a-Si is completely crystallized. Figure 5b is a schematic cross-sectional view of the crystallization scheme;

5) Soak in the mixed solution H ₂ SO ₄ +H ₂ O ₂ at 120° C. for 10 minutes to remove residual nickel on the surface. Then soak in 1% hydrofluoric acid (HF) for 1 minute to remove the nano-coating, and then deposit 100nm of LTO (low temperature oxide);

6) Use the ASM PAS5000 stepping photolithography machine with a wavelength of 365nm described in Example 1 to form a BG pattern, and the BG line period is 1 micron;

7) After baking at 120°C for 30 minutes, use boron as BG doping at 40KeV energy and 2E15/ ^cm2 dose for all P-channel TFTs, and phosphorus as BG doping for all N-type TFTs , the BG doping here is carried out through two steps, the dose in each step is 1E15/cm ² , the implantation energy is 80KeV and 130KeV respectively, and the structure shown in Figure 6 is obtained;

8) Use oxygen plasma to strip the photoresist at a temperature of 100° C. for 30 minutes. After removing the PR photoresist, 100 nm of LTO is also removed using 777 wet etching. After the BG step is completed, the entire partially doped polysilicon film can be called BG-poly-Si, which can be used for the TFT active layer.

The internal structure of the film shown in Figure 7b after the polysilicon film obtained in step 4) of the method provided in this embodiment is etched by tetramethylammonium hydroxide (TMAH) etching solution at room temperature is shown in Figure 7b. Polysilicon is a polysilicon film with small crystal grains (flocculent structure), which has a small mobility and a high residual nickel content. However, this technology has good uniformity, low cost, short annealing time, and a wider process window. Etc.

Example 4

This embodiment provides a method for forming a polysilicon film with bridging grain (BG) lines, including:

1) On an Eagel2000 glass substrate, 300 nm of silicon oxide (SiO ₂ ) was deposited using plasma enhanced chemical vapor deposition (PEVCD). Then use low-pressure chemical vapor deposition (LPCVD) to deposit 45 nanometers of a-Si at 550 ° C;

2) After dipping in 1% hydrofluoric acid solution (HF) for 1 minute to remove the natural oxide layer, deposit a layer of low-temperature oxide (LTO) with a thickness of 100 nanometers;

3) Through photolithography and etching processes, grooves with a width of 8 microns and an interval of 100 μm are formed on the LTO layer as induction lines (IL), as shown in Figure 5C, soaked in H ₂ SO ₄ +H ₂ O at 120 degrees ₂ In the mixed solution for 10 minutes to remove the photoresist, sputter a layer of slow-release (SR) nickel/silicon oxide source layer for metal-induced crystallization, using nickel-silicon alloy as the target material, the ratio of nickel to silicon is: Ni:Si=1 :9, the sputtering is carried out in a mixed environment of argon and oxygen in a ratio of 200:1, the sputtering DC power supply is 7W, and the sputtering time is 6 minutes;

4) Crystallization was carried out by heating at 590° C. in N _atmosphere for 2 hours, and Figure 5c is a schematic cross-sectional view of the crystallization scheme;

5) Immerse in a mixed solution of H ₂ SO ₄ +H ₂ O ₂ at 120 degrees for 10 minutes to remove residual nickel on the surface;

6) Use the ASM PAS5000 stepping photolithography machine with a wavelength of 365nm described in Example 1 to form a BG pattern, and the BG line period is 1 micron;

7) After baking at 120°C for 30 minutes, use boron as BG doping at 40KeV energy and 2E15/ ^cm2 dose for all P-channel TFTs, and phosphorus as BG doping for all N-type TFTs , the BG doping here is carried out through two steps, the dose in each step is 1E15/cm ² , the implantation energy is 80KeV and 130KeV respectively, and the structure shown in Figure 6 is obtained;

8) Use oxygen plasma to strip the photoresist at a temperature of 100° C. for 30 minutes. After removing the PR photoresist, 100 nm of LTO is also removed using 777 wet etching. After the BG step is completed, the entire partially doped polysilicon film can be called BG-poly-Si, which can be used for the TFT active layer.

The internal structure of the polysilicon film obtained in step 4) of the method provided in this embodiment is shown in Figure 7c after being etched by tetramethylammonium hydroxide (TMAH) etching solution at room temperature. Polysilicon provides a wider process window for slow-release nickel-induced lateral crystallization (SR-MILC) polysilicon thin films, which prevents batch processing from affecting process parameter variations between polysilicon TFTs.

Example 5

This embodiment provides a method for manufacturing a thin film transistor, including:

1) Forming a polysilicon film with bridging grain (BG) lines by the method provided in the above embodiment 4;

2) Pattern these partially doped BG-poly-Si films into active islands with an AME8110 reactive ion etcher;

3) After dry etching, the photoresist is removed by oxygen ions;

4) After removing the natural oxide layer with 1% HF, deposit a 100nm low-temperature oxide (LTO) as a gate insulating layer by LPCVD at 425° C.;

5) Deposit 300nm aluminum (or 280nm polysilicon) and pattern it into a gate electrode, doping the source and drain electrodes of P-type and N-type TFTs with boron and phosphorus at a dose of 4×10 ¹⁵ /cm ² respectively;

6) Depositing a 500nm LTO isolation layer and simultaneously activating the dopant;

7) Etching the contact hole, and then sputtering a layer of 700nm aluminum-1% silicon contact wire and patterning to form a BG-poly-TFT, the cross-sectional schematic diagram of which is shown in FIG. 8 .

In other embodiments, the above step 1) can also be replaced by using the method provided in the above embodiment 5 or embodiment 6 or other methods to form a polysilicon film with bridging grain (BG) lines. For the convenience of the following description, the thin film transistor made of the polysilicon film (large grain) formed in Example 4 is named Sample A, and the thin film transistor made of the polysilicon film (small grain) formed in Example 5 is named Sample B , the thin film transistor made of the polysilicon thin film formed in Example 6 was named Sample C (SR-MILC-TFT).

In order to illustrate the heterogeneity of the performance of the thin film transistor according to the utility model, the electrical characteristics of three kinds of BG polysilicon TFTs and TFTs without BG were measured by HP4156 semiconductor parameter analyzer for performance comparison. V _ds = -0.1 V and V _ds = -5 V, transfer characteristic curves were measured as a function of V _gs of TFT field effect mobility (μFE). The threshold voltage (Vth) is defined as the V _G voltage such that I _d =W/L×10 ^-7 A when V _ds =-5V. Field effect mobility (μFE) at low drain voltage (V _ds ＝-0.1V), the following equation:

${\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; FE</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; LG</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}}{{\mathrm{<span\; class="notranslate">\; WC</span>}}_{\mathrm{<span\; class="notranslate">\; ox</span>}}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; ds</span>}}}$

Where W and L are the effective channel width and length, _gm is the transconductance, _Cox is the gate insulating layer capacitance per unit area, and _Vds is the voltage between the drain and source. The reported field-effect mobilities are the maximum values measured.

A: Sample A (BG large grain MIC TFTs)

FIG. 9( a ) is the transfer characteristic curve of TFT as a function of V _gs when V _ds =-0.1V and V _ds =-5V. The electrical parameters of large-grain BG MIC TFT and those of non-BG are shown in Table 1. The subthreshold swing (S) of the BG large-grain MIC TFT is 0.78V/dec, while that of the non-BG is 1.02V/dec. In addition, the threshold voltage (V _th ) decreased by 3.2V to -6.6V with the BG structure. Another obvious improvement is Gate Induced Drain Leakage (GIDL). The leakage current of the BG TFT is 6.13pA/μm, which is about 1/2000 of that of a normal large-grain MIC TFT at V _gs =10V and V _ds =-5V. From the above comparison, we can see that most of the TFT parameters have been significantly improved after applying BG technology.

Figure 9(b) shows the output current ratio of BG large-grain MIC TFT and non-BG structure TFT with V _gs as a function. We can find that when _Vgs and _Vds are changed, the current ratio (γ) between BG TFT and non-BGTFT is also changed. When V _ds = -0.1V, in region 1, as shown in Fig. 9, γ is about ~0.5, which means that the leakage current is reduced by half. In the subthreshold region of zone 2, gamma increases dramatically, with a maximum value of ~70, which is about 20 times the value of gamma in zone 3. When V _ds = -5V, the large-grain MIC TFT in region 1 exhibited unique leakage current and gate-induced drain leakage (GIDL), meanwhile, the GIDL of the BG large-grain MIC TFT was significantly suppressed to ~10 ^-10 A and The minimum current is also dropped by a factor of 11. As shown in Figure 9(b), γ dropped significantly to ~10 ^-4 . It is worth noting that there are two main reasons for the increase in off-state leakage current of polysilicon TFTs. One of the reasons is the high electric field in the drain region due to the applied gate and drain voltages. Leakage current increases significantly with increasing V _ds ; the second reason is the grain boundary defect density near the drain region. For BG-TFT, the reduction of the leakage current in the first region is also due to these two reasons, because the bridging effect of the BG structure makes the reduction of grain boundary defects, and a series of shallow series of active channels in the BG-TFT The junction results in a reduction of the electric field. Boron doping on the BG line is consistent with the polarity of the source and drain of the TFT. Typically, undoped MIC polysilicon films show slight n-polarity. Therefore, in the first region, when V _gs is smaller than V _th , the undoped MIC polysilicon is n-polar and the doped region shows p+ polarity, which means that the TFT active channel with BG structure becomes A series of pn junctions. This is also why both GIDL and minimum current are greatly reduced.

In the second zone, the sub-threshold zone, the BG-line bridges the flow direction of the current in the vertical direction of the grain, so that the grain boundary barrier can be reduced by the BG structure. At the same time, due to the doping of the BG line , defect states and boundary inhomogeneities are filled or terminated. Therefore, not only the threshold voltage of the TFT with the BG structure is ~3V lower than that of the TFT without the BG structure, but also the subthreshold swing (S) of the TFT with the BG structure is also reduced from 1.02V/decade to 0.78V/decade.

In region 3, the increase of on current is related to 2 factors of BG structure. This is because, a TFT with a BG line can be regarded as a series of short-channel TFTs. Therefore, BG's TFT has the benefits of a short-channel TFT without hot carrier effects, increasing the on-state current, reducing the threshold voltage and sub-threshold slope swing, etc.

Table 1 Electrical parameters of P-type large grain MIC TFT with BG structure and non-BG structure

Figure 10(a) and (b) show the transconductance of BG large-grain MIC TFT and non-BG large-grain MIC TFT under the conditions of V _ds =-0.1V and V _ds =-5V respectively.

Figure 11(a) and (b) show the difference in the performance of P-channel TFTs, and show the V _TH and GIDL of a general large-grain MIC TFT and a BG large-grain MIC TFT. Data measurements are taken from 50 TFTs evenly spaced over a 4-inch glass wafer. Obviously, the GIDL value of TFT with BG structure is much lower than that of general large-grain MIC TFT, and the difference of GIDL is also greatly improved. At the same time, compared with normal large-grain MIC TFT, BG large-grain MIC TFT also exhibits smaller V _th variation and absolute V _th value.

B: Sample B (BG small grain MIC TFT)

Fig. 12(a) shows the transfer characteristic curves of small grain (or floc structure) MIC polysilicon TFTs with and without BG structure when V _ds =-0.1V and V _ds =-5V. Figure 12(b) shows the output current ratio (γ) plots of small-grain MIC polysilicon TFTs with and without BG structure, with V _gs as a function. Table 2 lists the electrical parameters of small-grain MIC polysilicon TFTs with BG structure and non-BG structure. The subthreshold swing (S) of BG structure TFT and non-BG structure TFT is 0.8V/dec and 1.15V/dec, respectively. In addition, the absolute value of the threshold voltage (V _th ) of the TFT with the BG structure is reduced by 4.5V to 6.8V. In the second region, as shown in Fig. 12(b), the subthreshold region, when V _ds = -0.1V and V _ds = -5V, γ increases significantly and reaches the highest value of ~2×10 ⁴ and ~4 ×10 ³ , which is hundreds or thousands of times larger than the gamma value in region 3.

Another obvious improvement is the leakage current in the 1 region, as shown in Fig. 12(a). When V _gs =10V and V _ds =-5V, the leakage current of the BG small grain MIC TFT is 14.6pA/um, which is about 1/50 of the normal small grain MIC TFT. As shown in Fig. 12(a), when V _ds = -5V, in region 1, the small-grain MIC TFT has obvious leakage current and GIDL, while the GIDL of the BG small-grain MIC TFT is obviously suppressed to ~10 ^-10 A and minimum current are also reduced by a factor of 3.1. As shown in Figure 13(b), γ dropped significantly by ~2×10 ⁻² . From the above comparison, we can see that most of the TFT parameters have been significantly improved after applying BG technology.

Table 2 Electrical parameters of P-type small grain MIC TFT with BG structure and non-BG structure

Figure 13(a) and (b) show the transconductance of BG small-grain MIC TFT and non-BG small-grain P-type MIC TFT under the conditions of V _ds =-0.1V and V _ds =-5V respectively.

Figure 14(a) and (b) show the difference in performance of P-channel TFTs, showing the V _th and GIDL of a general small-grain MIC TFT and a BG small-grain MIC TFT. Data measurements were taken from 96 TFTs evenly spaced over a 4-inch glass wafer. Obviously, the GIDL value of the TFT with BG structure is much lower than that of the normal small-grain MIC TFT, and the difference of GIDL is also greatly improved. Meanwhile, the BG small-grain MIC TFT also exhibits smaller V _th variation compared with the general small-grain MIC TFT. Table 3 shows the uniformity data of V _th and GIDL of 4 kinds of TFTs including MIC of large grain, BG large grain MIC, small grain MIC and BG small grain MIC. From the comparison, we can find that the uniformity of the small-grain MIC TFT is better than that of the large-grain MIC TFT, and the same effect is also found between the BG large-grain MIC TFT and the BG small-grain MIC TFT. BG TFTs exhibited smaller differences in GIDL due to greater reduction in absolute value of GIDL. It should be noted that the TFTs of small-grain MICs showed a smaller standard deviation of _Vth than the TFTs of BG small-grain MICs. This is because the inhomogeneity of the BG line still needs a large improvement in the future.

Table 3 Uniformity comparison of large-grain and small-grain MIC TFTs with BG and non-BG structures

C: Sample C (BG SR-MILC TFT)

Fig. 15(a) shows the transfer characteristic curves of SR-MILC polysilicon TFTs with and without BG structure when V _ds =-0.1V and V _ds =-5V. Figure 15(b) shows the output current ratio (γ) plots of P-channel SR-MILC TFTs with and without BG structure as a function of V _gs . Table 4 lists the electrical parameters of BG structure and non-BG structure SR-MILC TFT. The subthreshold swing (S) of BG structure TFT and non-BG structure SR-MILC TFT is 0.95V/dec and 1.34V/dec, respectively. In addition, the absolute value of the threshold voltage (V _th ) of the TFT with the BG structure is reduced by 4.1V to 5.9V. In region 2, as shown in Fig. 15(b), the subthreshold region, γ increases significantly and reaches a maximum value of ~100, which is 20 times greater than the value of γ in region 3.

Another obvious improvement is the leakage current when the TFT is reverse biased, as shown in Figure 12(a). When V _gs =10V and V _ds =-5V, the leakage current of BG SR-MILC TFT is 7.26pA/um, which is about 1/32 of that of general SR-MILC TFT. As shown in Figure 15(a), when V _ds = -5V, in region 1, SR-MILC TFT has obvious leakage current and GIDL, while the GIDL of BG SR-MILC TFT is obviously suppressed to ~2×10 ^-10 A and minimum current are also reduced by a factor of 3. As shown in Figure 15(b), γ dropped significantly by ~3×10 ⁻² .

Table 4 Electrical parameters of P-type SR-MILC polysilicon TFT with BG structure and non-BG structure

Example 8

D: Anisotropic SR-MILC polysilicon TFT and uniform BG polysilicon TFT

This embodiment provides an SR-MILC TFT, and FIG. 16 is a regional microscopic view of the etched SR-MILC TFT of TMAH. In this embodiment, the width of the induction line is 8 microns, and the distance between two adjacent induction lines is 100 microns. Metal-induced lateral crystallization occurs from elongated grains and associated low-angle grain boundaries GBS, which are mainly along the MILC direction, as shown by the dotted circle in Fig. 16. The angle between the low-angle GBS and the horizontal MILC direction is usually less than 30°. This relatively ordered and anisotropic microstructure differs from those of SPC and LPCVD polysilicon, whose random nucleation and uniform grain growth lead to isotropic microstructure and electrical properties. Two types of P-channel TFTs are fabricated using the traditional LTPS TFT process. All TFTs have the same active channel width (W) of 10 microns, and different channel lengths (L) ranging from 1 micron to 20 microns. In addition, all TFT active channels are located in the excellent MILC region, which means that the edge of each TFT active channel is at least 7 μm away from the induction line and the LLGB line in the middle of the two induction lines. The current of type A TFT is parallel to the crystallization direction of MILC, and the current of type B TFT is perpendicular to the crystallization direction of MILC. In addition, the BG structure in which the BG line is perpendicular to the current direction is applied to two types of thin film transistors of type A and type B to reduce the anisotropic effect of this SR-MILC polysilicon film. This zebra-like BG polysilicon film is composed of repeated parallel 0.5μm polysilicon lines and 0.5μm boron-doped polysilicon lines.

Figure 17 is a typical logarithmic ratio transfer curve of a normal SR-MILC polysilicon TFT at V _ds = -5V, where the current of the A-type TFT is parallel to the MILC crystallographic direction, and the B-type TFT current is perpendicular to the MILC crystallographic direction. Here, the width and length of the TFT are 10 μm and 14 μm, respectively. Except for the subthreshold region indicated by the dotted circles as shown in Figure 17, essentially all TFTs show the same transfer curves. In order to further explore the anisotropic performance of SR-MILC polysilicon thin film transistors, more types of A-type and B-type TFTs were fabricated, carefully measured and studied, and the L size ranged from 1 micron to 20 μm. TFT threshold voltage (V _th ) is defined as V _G voltage such that I _d =W/L×10 ^-9 A when V _ds =-0.1V. To highlight the difference in the subthreshold region, V _th is extracted as a function of L for Type A and Type B TFTs and shown in Figure 18.

As shown in Fig. 18, when L is less than 2 μm, both Type A and Type B TFTs exhibit substantially the same V _TH value and standard deviation (SD). In the subthreshold region, _Id is the dominant diffusion current and carriers along the high-conductance path provided by the well-crystallized region. The average width of the elongated grains of SR-MILC is about 3-5 microns, as shown in FIG. 16 . When L is less than 2um, for A-type and B-type TFTs, the diffusion current from source to drain is mainly in one grain. Therefore, all TFTs showed the same threshold voltage and the same SD. As the channel length increases, the Type A TFT exhibits a relatively smaller V _th than the Type B TFT. This is because when the channel length of B-type TFT is greater than 4 μm, the low-angle grain boundary will likely fall on the active channel, and its direction is perpendicular to the current direction. The low-angle grain boundaries in the B-type TFT will be an obstacle to the diffusion current, making the _Vth of the B-type TFT larger than that of the A-type TFT.

In the subthreshold region, the conduction behavior of polysilicon TFTs is mainly controlled by thermionic emission. When the low-angle grain boundary (GB _S ) traverses the current flow, the GB grain boundary acts like a higher potential barrier to thermionic emission than is the case within the grain boundary. When the TFT is turned on, the conduction behavior is mainly controlled by defects and/or GB scattering. Figure 19 shows typical linear scale IV curves for conventional SR-MILC TFTs of type A and B. The difference between Type A and Type B TFTs is circled with dotted circles. The channel resistivity of the polysilicon TFT at V _gs =-18V and V _ds =-0.1V has been extracted and compared to FIG. 20 .

The resistivity of the A-type TFT channel with the current direction parallel to the MILC direction is denoted as ρ _p . The B-type TFT channel resistivity with the current direction perpendicular to the MILC direction is denoted as ρ _t . As shown in Fig. 20, when L is smaller than 2 μm, _ρp and _ρt are substantially the same, which can be explained by the substantially same _Vth value in the subthreshold region. When L is larger than 4 μm, ρ _p becomes smaller than ρ _t . For the ρ _case , current flow through vertical low-angle grain boundaries and continuous carrier excitation across a series of lateral grain boundaries along the conduction direction are required. Therefore, the current is limited by those low-angle _GBs in the active channel of the TFT. For the case of ρ _p , the current direction is parallel to the long grains. As we know, the angle between low-angle grain boundaries and MILC directions is usually less than 30 degrees. In the case of W/L<1/2, low angle GB _S and lower resistivity ρ _p may appear in the channel region. Therefore, the flow of current will follow a meandering pattern, avoiding the low angle _GBs encountered in lateral conduction. However, Type A devices generally have fewer low-angle grain boundaries than Type B TFTs. Therefore, this is also the reason why ρ _p of the SR-MILC polysilicon thin film transistor is small. Of course, the anisotropic conductive properties of SR-MILC polysilicon films will result in TFTs with poor uniformity. Figure 21 and Figure 22 show the extracted _Vth and resistivity of A-type and B-type TFTs of BG structure. The BG line period is 1 micron. When L is smaller than 4 μm, the BG structure is not significantly improved. When L is greater than 4 μm, unlike the A-type and B-type TFTs shown in Figure 18 and Figure 20, it has a BG structure, and the difference between the A-type and B-type TFTs will be reduced, showing better uniformity. This is because the low-angle grain boundary between the two pinched small grain regions in the TFT channel is bridged by the doped BG structure. Therefore, using the BG structure, the anisotropy effect of the SR-MILC polysilicon film can be effectively eliminated.

Although the utility model has been specifically described with reference to the above-mentioned embodiments, for those of ordinary skill in the art, the above embodiments are only used to describe the technical solutions of the present utility model rather than to limit the technical method. The application can extend to other modifications, changes, applications, and embodiments, and all such modifications, changes, applications, and embodiments are therefore considered to be within the spirit and teaching scope of the present invention.

Claims (4)

1. An active matrix display comprising a plurality of thin film transistors, wherein each thin film transistor comprises: The active layer is composed of a polysilicon film, and the polysilicon film has parallel conductive strips or conductive lines, and the conductive strips or conductive lines connect a plurality of crystal grains; source and drain on the active layer; gate insulating layer; grid; It is characterized in that the conductive strips or conductive lines are composed of doped lines; the direction of the parallel conductive strips or conductive lines is perpendicular to the current direction. 2. The active matrix display according to claim 1, wherein the plurality of thin film transistors included include P-type thin film transistors and N-type thin film transistors, wherein the polysilicon thin film forming the active layer of the P-type thin film transistors The conductive strips or conductive lines of the N-type thin film transistor are composed of boron-doped lines, and the conductive strips or conductive lines in the polysilicon film constituting the active layer of the N-type thin film transistor are composed of phosphorous-doped lines. 3. The active matrix display of claim 1, wherein the width and pitch of the plurality of conductive strips or conductive lines is similar to the grain size. 4. The active matrix display according to claim 1, wherein in the polysilicon film constituting the active layer, in the doped lines, the doping peak in the thickness direction of the polysilicon film is located at the center of the polysilicon film thickness.

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