CN102955307A - Field sequential color liquid crystal display based on polycrystalline silicon thin film transistor - Google Patents

Field sequential color liquid crystal display based on polycrystalline silicon thin film transistor Download PDF

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CN102955307A
CN102955307A CN2012100513018A CN201210051301A CN102955307A CN 102955307 A CN102955307 A CN 102955307A CN 2012100513018 A CN2012100513018 A CN 2012100513018A CN 201210051301 A CN201210051301 A CN 201210051301A CN 102955307 A CN102955307 A CN 102955307A
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active matrix
layer
liquid crystal
tft
crystal display
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赵淑云
郭海成
王文
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GUANGDONG ZHONGXIAN TECHNOLOGY Co Ltd
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GUANGDONG ZHONGXIAN TECHNOLOGY Co Ltd
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Abstract

The invention provides an active matrix rear panel for a field sequential color liquid crystal display. The active matrix rear panel comprises a substrate, a polycrystalline silicon thin film transistor on the substrate, a scanning line and a data line, wherein a channel width/length ratio of the thin film transistor is at least 0.06. The invention also provides a manufacturing method of the active matrix rear panel for the field sequential color liquid crystal display.

Description

Field-sequential color liquid crystal display based on polycrystalline SiTFT
Technical field
The present invention relates to a kind of field-sequential color liquid crystal display, relate in particular to a kind of field-sequential color liquid crystal display based on polycrystalline SiTFT.
Background technology
For high-resolution flat-panel monitor, thin film transistor (TFT) is necessary.Liquid crystal display is the main flow in all flat panel displays.The TFT-LCD technology has wide application, from mobile phone, this class small consumer products of digital camera to giant displays such as desktop computer displays and televisors.TFTLCD has the industrial foundation of huge maturation.For LCD display, pocket particularly, the high-luminous-efficiency low energy consumption becomes research emphasis.For high-contrast, high resolving power, Gao Sezhen, move into the picture clearly high-resolution display field sequential color (FSC) technology be splendid selection.This display based on DLP and LCoS is coming into the market of success.
Based on the LCD of colour film (CF) technology, need the red, green and blue sub-pixels shown in Fig. 1 (a).In this structure, high light efficiency and Gao Sezhen can not coexist.Gao Sezhen needs thick color film usually, and its light transmission efficiency is relatively poor.Even sacrificing look true, still relatively poor based on the display light transmission efficiency of color film (CF).Even in the situation that best, still only less than 10% backlight can the utilization.Therefore, based on the RGB sub-pixel structure, under existing process conditions, be difficult to improve resolution.
Field sequential color LCD utilizes pulse color LED backlight and liquid crystal cells at each pixel simultaneously, reappears redly, green and blue on each time series, and need not the micro color film.Dot structure is shown in Fig. 1 (b).This method shows so can realize high brightness because there be not the backlight of colour film absorption.The pixel quantity of field sequential color displays only has with 1/3rd of CF display.Therefore, field sequential color LCD has than with the higher aperture opening ratio of color filter display (AR) and use same technology it can realize being higher than 3 times resolution in same resolution.
Therefore FSC-LCD is an important green environmental protection technique.The major issue of FSC-LCD is that look separates.Separate in order to solve look, need the frame rate of Cai Genggao, for example replace original 60HZ with 90HZ.
Summary of the invention
Therefore for realizing FSC, the LCD pattern is indispensable together with the swift electron addressing based on the TFT panel fast.Therefore the invention provides a kind of field-sequential color liquid crystal display (FSC-LCD) that adopts the multi-crystal TFT of high mobility, it adopts multi-crystal TFT at the enterprising row data of TFT substrate rapid loading.
The invention provides a kind of active matrix backboard of field-sequential color liquid crystal display, comprising: substrate; Polycrystalline SiTFT on the substrate, the raceway groove width/length ratio of this thin film transistor (TFT) is at least 0.06; Sweep trace; Data line.
In active matrix backboard of the present invention, Pixel Dimensions is 200 * 200 μ m, and the width of sweep trace and data line is 12 μ m, and the minimum interval of the figure between the same layer is 5 μ m, and the minimum interval between different figures is 2 μ m.
In active matrix backboard of the present invention, wherein the raceway groove width/length ratio of polycrystalline SiTFT is at least 0.5.
In active matrix backboard of the present invention, wherein polycrystalline SiTFT has two separated grids, and the raceway groove width/length ratio of thin film transistor (TFT) is 24 μ m/5 μ m * 2.
In active matrix backboard of the present invention, also comprise pixel capacitance, pixel capacitance by and the data line of sweep trace different layers between electric capacity, sweep trace and LC thereon between electric capacity, the electric capacity between the addressing thin film transistor (TFT) form.
In active matrix backboard of the present invention, wherein the thickness of insulating material is 0.6 μ m between data line and sweep trace, and the thickness of lc unit is 5 μ m.
In active matrix backboard of the present invention, wherein said liquid crystal display is the QVGA liquid crystal display, VGA liquid crystal display, XGA liquid crystal display or SXGA liquid crystal display.
In active matrix backboard of the present invention, wherein the active layer of polycrystalline SiTFT is continuous band-shaped regional polysilicon membrane.
In active matrix backboard of the present invention, the active layer of wherein said polycrystalline SiTFT is standby by mask metal-induced crystallization legal system, and the method comprises:
With plasma activated chemical vapour deposition silicon dioxide on glass substrate, again with the low-pressure chemical vapor deposition amorphous silicon membrane;
Form the nanometer titanium dioxide silicon layer on the amorphous silicon membrane surface, form by photoetching process and induce linear window, inducing the line place to form thin chemical oxide layer;
The nisiloy oxide of sputter one deck 7-14 dust on silicon dioxide layer and chemical oxide layer, high annealing is with the whole crystallization of amorphous silicon.
According to another aspect of the invention, also provide a kind of method of making the active matrix backboard, comprising: deposition of amorphous silicon films on substrate; Form the nanometer titanium dioxide silicon layer on the amorphous silicon membrane surface, form by photoetching process and induce linear window, inducing the line place to form thin chemical oxide layer; The nisiloy oxide of sputter one deck 7-14 dust on silicon dioxide layer and chemical oxide layer, high annealing form polysilicon layer with the whole crystallization of amorphous silicon; As active layer, make polycrystalline SiTFT with this polysilicon layer; Form data line and sweep trace.
Description of drawings
Embodiments of the present invention is further illustrated referring to accompanying drawing, wherein:
The band colored filter LCD (a) that Fig. 1 is traditional and field sequential color LCD (b) cross-sectional view; Traditional band colored filter LCD (c) and field sequential color LCD (d) pixel map;
Fig. 2 shows QVGA with the drive principle of LCD (a) and the field sequential color LCD (b) of color filter;
Fig. 3 is the project organization synoptic diagram of 5 μ m techniques;
Fig. 4 be a-Si:H TFT and P-Si TFT in 5 μ m and 10 μ m preparation technologies, the aperture opening ratio corresponding according to respective scan line quantity (AR);
The power function of Fig. 5 impressed voltage and LC electric capacity;
Fig. 6 is the time response of LC when charging;
Fig. 7 is the reaction time of LC in keep-process;
Fig. 8 is the structure of FSC-LCD. image element circuit;
Fig. 9 is the electric capacity relevant with sweep trace on a pixel;
Figure 10 is the electric capacity relevant with data line on the pixel;
Figure 11 is the 3 inches active driving backboard of QVGA TFT layouts;
Figure 12 is the structural representation by the polysilicon membrane of MMIC method preparation;
Figure 13 is content and the distribution of nickel in the CZD that measures of Tof-SIMS and the MILC gained polysilicon;
Figure 14 is the manufacturing process of FSC-LCD active array;
The optical microscope photograph (b) of 3 inches QVGA active arrays of Figure 15 (a) panel is the enlarged photograph of a pixel region.
Embodiment
Describe the present invention below in conjunction with drawings and Examples.The principle of work of FSC LCD is to show red, green and blue (RGB) subframe in the displaying time order.If frame rate is enough fast, people's eyes will be integrated the realistic colour that visual field and observer it will be appreciated that image.The RGB LED-backlit lamp of the realization of RGB subframe by independently being controlled.By the GTG of control subframe, can realize full-color demonstration, its color saturation is better than color filter (CF) escope usually.
Under identical frame rate, minute frame rate of FSC-LCD is three times of traditional CF LCD.Yet, to separate for reducing look, higher subframe speed will be used.Fig. 2 (b) has showed the drives structure principle of FSC-LCD.For the QVGA display of a 90HZ frame speed, the duration of a frame is about 11.1ms.So the duration of a subframe only is 3.7ms.The fast-response time of supposing LCD is that the minimum start-up period of 1.7ms and LED accounts for 30%, leaves the time of data loading for and only has 1ms, shown in Fig. 2 (b).For the color filter film LCD with equal resolution, identical frame rate and data load, and liquid crystal drive and LED illumination can occur in same time, shown in Fig. 2 (a).This load time that just means FSC-LCD under equal resolution only is 1/10th of CF LCD.Therefore the rapid data loading is the major issue of FSC-LCD, and this just means that field-effect mobility is～1cm 2The non-crystalline silicon tft of/Vs can not satisfy the use needs.Multi-crystal TFT with high field-effect mobility becomes the key of FSC-LCD.
The design of TFT pixel
What lower surface analysis is at AM FSC-LCD to the requirement of pixel TFT.V DFor being added in the voltage on the data line, the voltage level on the pixel approximately is described as following equation as the function of time (t):
V write＝V D(1-e -t/τon)；τ on＝R onC s..................(1)
V hold＝V De -t/τoff； τ on＝R offC s..................(2)
R OnAnd R OffThe channel resistance of TFT when being respectively TFT " opening " and "Off" state.V WriteAnd V HoldRefer to that respectively pixel electrode is at the voltage of charging process and maintenance process.
When image was write to LC, it needed
V signal > 0.99 V D ⇒ T writing > 4.6 τ on - - - ( 3 )
When image was in hold mode, it needed
V signal > 0.95 V D &DoubleRightArrow; T holdign < &tau; off / 19.5 - - - ( 4 )
So , &tau; on < T writing / 4.6 &DoubleRightArrow; R on < T writing / 4.6 C s - - - ( 5 )
&tau; off > 19.5 T holding &DoubleRightArrow; R off > 19.5 T holding / C s - - - ( 6 )
V SignalThe image voltage on the pixel electrode, T WritingThe time of writing image, T HoldingBe the time of keeping image, in display standard, this is a typical frame period.In present design, Cs was～1.0pF during AMCS-LCD showed.As mentioned before, the limit time of each subframe only has 3.7ms.Be 3.7ms, R so hold time OffShould for:
R off＞19.5T holding/C s＝7.2×10 10Ω
Under identical frame rate, the driven speed of color sequence LCD is 3 times of traditional LC D.The time of writing only has about 1ms, so with respect to traditional LCD, it needs less R OnFor addressing TFT, the wire zone of its work, leakage current (I d) pass:
I d = &mu; FE &epsiv; 0 &epsiv; t ox &times; W L ( V gs - V T ) &times; V D - - - ( 7 )
&DoubleRightArrow; R on = V D I d = t ox L &mu; FE &epsiv; 0 &epsiv;W ( V gs - V T ) - - - ( 8 )
The μ here FERefer to the mobility of field effect, ε 0ε is the dielectric constant of grid oxic horizon, and W and L are respectively width and the length of TFT, V GsVoltage and the V that is applied between gate-source TIt is threshold voltage.In conjunction with equation (5), the ratio (W/L) of the wide length of TFT can be expressed as:
W L > 4.6 &times; C s t ox &mu; FE &epsiv; 0 &epsiv; ( V gs - V T ) &times; T writing - - - ( 9 )
Here our hypothesis is in ON state, the V of TFT Gs15V, and C s=1.0pF.The parameter of typical a-Si:HTFT and multi-crystal TFT is listed in table 1, and long (L) ratio of the raceway groove of TFT wide (W) can be showed by equation (9), lists in the table 1.For the QVGA demonstration of 90Hz frame rate, the time of writing of each pixel is 4 μ s.The W/L ratio of a-Si:H TFT requires to be at least 14.Simultaneously, the requirement of the W/L ratio of multi-crystal TFT only is 0.06.That means under the technique of 5 μ m, and the TFT channel width of a-Si:H TFT is 70 μ m, and multi-crystal TFT only is 0.3 μ m.With regard to higher resolution shows, write time shorten, so the requirement of the W/L ratio of TFT is larger.Be shown as example with regard to SXGA, only there is 0.9 μ s the restriction time of writing.The channel width of a-Si:H TFT requires at least 300 μ m, and this is impossible for the technique of 5 μ m fully.Yet compared to a-Si:H TFT, it only needs～1.5 μ m to use the multi-crystal TFT technology, compares with a-Si:H TFT, and multi-crystal TFT is because therefore its higher field-effect mobility can reach higher aperture opening ratio (AR).
Table 1 multi-crystal TFT and a-Si:HTFT canonical parameter
Figure BSA00000677562700064
In the present embodiment, in order to make calculating simplicity, make design rule as follows: Pixel Dimensions is fixed as 200 * 200 μ m, and sweep trace and data line width are 12 μ m, the minimum interval of the figure between the same layer is 5 μ m, and the minimum interval between different figures is 2 μ m.Usually, in LCD showed, the grid length of TFT was 5 μ m or 10 μ m, according to these technological parameter exemplary distribution of pixel, wherein image element circuit only has a TFT, based on table 2 listed a-Si:H TFT and the W/L ratio of multi-crystal TFT under different resolution.It is reported, photoetching technique can't provide than feature technology (2 λ=5 μ m) and also want little live width or length, that is to say, the L of TFT and W can not be less than 2 λ.For example, L=5 μ m, the W of TFT must also just mean W/L necessarily greater than 1 greater than 5 μ m, if W=10 μ is m, the W of TFT must greater than 5 μ m, just mean that also W/L is necessarily more than or equal to 0.5.So, at table 2, for all multi-crystal TFTs, calculating respectively L and be 5 μ m to 10 μ m, W/L is 0.5 to 1 aperture opening ratio (AR).
Fig. 3 is the project organization synoptic diagram of 5 μ m techniques.
Simultaneously, for FSC-LCD, memory capacitance can be the grid capacitance of TFT.Based on our calculating, can additionally increase memory capacitance, these will partly be explained below.So a need is considered the size of addressing TFT in aperture opening ratio is derived.Fig. 4 has shown respectively a-Si:H TFT and P-Si TFT at 5 μ m and 10 μ m grid widths, according to the corresponding aperture opening ratio (AR) of respective scan line quantity.A-Si:HTFT, pixel aperture ratio (AR) diminishes along with the increase of sweep trace.Multi-crystal TFT, the aperture opening ratio of pixel (AR) almost maintains 77%-78%.Therefore, multi-crystal TFT is mathematical can reach high resolving power and high aperture (AR) demonstration.
The breadth length ratio rate of table 2 addressing TFT
Figure BSA00000677562700071
Figure BSA00000677562700081
The design of electric capacity
Electric capacity provides by formula C=ε A/d.In the formula, A and d are respectively area and the thickness of capacitor dielectric material.For LC, its electric capacity is more complicated, and also its this characteristic makes it very useful just, and that is that specific inductive capacity is anisotropic exactly, and namely it depends on the direction of electric field.Fig. 5 has showed the electric capacity of LC and the power function of impressed voltage.For eurymeric LC, C //＞C ⊥, LC will be parallel to direction of an electric field under high voltage.Here we suppose, C ⊥=0.31pF, C //=1.0pF, V On=10VandR On=0.1M Ω.
Usually, C is considered to a constant, is defined as Charging process can be described by following formula
Figure BSA00000677562700083
V DFor being added in the virtual voltage on the data line.V is the voltage on the LC.Straight line among Fig. 6 is the time response of voltage on LC.Finish V Signal＞0.99V DWrite time be about 0.4 μ s.
In order to describe more accurately this process, the variation of C all is not taken into account under the same electric field.As shown in Figure 5, suppose V ∈ (0, V On),, and
Figure BSA00000677562700084
So charging process can be with the following mode that represents more accurately V D - V R on = dQ dt = d ( C &perp; + C / / - C &perp; V on &times; V ) &times; V dt Also can be write as
Figure BSA00000677562700086
Solid dot among Fig. 6 (C-variable) lines have been showed voltage on the LC and the relation in reaction time.Realize V Signal＞0.99V DWrite time only need 0.7 μ s.
For keep-process, also done identical emulation.If C is considered as constant, keep-process can be done following description
V R off = - C / / + C &perp; 2 &times; dV dt - - - ( 12 )
If C is considered as variable, keep-process can be done following description
V R off = - C &perp; &times; dV dt - 2 C / / - C &perp; V on &times; V &times; dV dt - - - ( 13 )
Use the equation of above-mentioned (12) and (13), image voltage time as shown in Figure 7 corresponding.Keep this process need V Signal＞0.95V DSo be respectively 4ms and 6ms for the said circumstances maximum retention time.The electric capacity that this means LC is enough large for the QVGA FSC-LCD of 90HZ refreshing frequency.In our design, do not need more extra storage electric capacity in the FSC-LCD image element circuit.
An image element circuit zone only has a TFT, as shown in Figure 8.According to one embodiment of present invention, wherein the W/L of TFT is 24 μ m/5 μ m * 2, and this result of calculation from 5 μ m/5 μ m is different.Two separated grids are used for reducing the leakage current of CZD multi-crystal TFT.Under the dot structure basis of carrying in front, under the prerequisite that does not reduce display panel pixel aperture opening ratio 1%, larger W/L design can increase ON state current and reduce the write time for each pixel.
The design of sweep trace
As shown in Figure 9, pixel capacitance (C Slu) by and the data line of sweep trace different layers between electric capacity (C Sdu), the electric capacity (C between sweep trace and LC thereon SLCu), the electric capacity (C between addressing TFT Gateu) form.Take the QVGA FSC-LCD of 90HZ as example.
In the present embodiment, a pixel is of a size of 200 μ m * 200 μ m, and the width of sweep trace and data line is 12 μ m.Gate blocks layer oxide thickness (d) is 0.12 μ m.The thickness of insulating material (d ') is 0.6 μ m between data line and sweep trace, and (d ") is 5 μ m to the thickness of lc unit.
C sdu = &epsiv; 0 &epsiv; ox S d = &epsiv; 0 &times; 4 &times; 12 &mu;m &times; 12 &mu;m 0.6 &mu;m = 8.5 &times; 10 - 3 pF
C gateu = &epsiv; 0 &epsiv; ox S &prime; d &prime; = &epsiv; 0 &times; 4 &times; 10 &mu;m &times; 5 &mu;m 0.12 &mu;m = 1.5 &times; 10 - 2 pF
C sLCu = &epsiv; 0 &epsiv; LC S &prime; &prime; d &prime; &prime; = &epsiv; 0 &times; 12.7 &times; 188 &mu;m &times; 12 &mu;m 5 &mu;m = 5.1 &times; 10 - 2 pF
The total capacitance relevant with sweep trace is on the pixel:
C ssu＝C sdu+C gateu+C sdu＝7.45×10 -2pF
Noted earlier such as us, for FSC-AMLCD, suppose that resolution is QVGA (240 * 320), refreshing frequency is 90Hz.
T writing = 4.0 &mu;s , &tau; on < T writing 4.6 = 0.87 &mu;s
Usually, select time is less than pixel write time T WritingTen minutes one.
&tau; ons < 11 10 &tau; on &DoubleRightArrow; &tau; ons < 0.087 &mu;s
Total capacitance is: C Ss=320 * 7.45 * 10 -2=23.84pF
R SL < &tau; ons C ss = 0.087 &mu;s 23.84 pF = 3.8 K&Omega;
Utilize similarly and derive, listed to needs such as the table 3 of sweep trace for high resolution display.
The FSC-LCDs of table 3 different resolution comprises square resistance to the requirement of sweep trace, and RC postpones and with the true resistance of the data line of following fabrication
Figure BSA00000677562700104
The design of data line
In the present embodiment, Pixel Dimensions is 200 μ m * 200 micron, and the live width of data line and sweep trace is 12 μ m.The minimum interval of identical layer is 5 μ m, and the minimum interval of different layers is 2 μ m.
As shown in figure 10, the electric capacity (C on pixel Dlu) by at the sweep trace between different layers and the electric capacity (C between data line Dsu) and at the LC on the data line and the electric capacity (C between data line DLCu) form.In this design, insulation thickness between data line and sweep trace (d ') is 0.6 μ m, and lc unit thickness is 5 μ m.Take QVGAFSC-LCD as example,
C dsu = &epsiv; 0 &epsiv; ox S d &prime; = &epsiv; 0 &times; 4 &times; 12 &mu;m &times; 12 &mu;m 0.6 &mu;m = 8.5 &times; 10 - 3 pF
C dLCu = &epsiv; 0 &epsiv; LC S &prime; &prime; d &prime; &prime; = &epsiv; 0 &times; 12.7 &times; 188 &mu;m &times; 12 &mu;m 5 &mu;m = 5.1 &times; 10 - 2 pF
C dlu＝C dsu+C dLCu＝5.99×10 -2pF
In the formula, ε 0Be permittivity of vacuum.ε OxAnd ε LCBe respectively the relative dielectric constant of insulation course and lc unit.For the QVGA display, the total capacitance relevant with data line is:
C ds＝240×5.99×10 -2＝14.4pF
τ Ond=R Dl* C dL, the load time of data-driven addressing TFT is 1/10th of the pixel write time usually.As mentioned above, the RC of image element circuit postpones (τ On) be about 0.87 μ s, so τ Ond≤ 0.087 μ s.The resistance of data line is roughly
Figure BSA00000677562700113
Based on theorems, can derive the FSC-LCD of different resolution to the demand of data line, and list table 4 in.
So, for QVGA FSC-LCD, the largest block resistance R of data line MAXBe 1.5 Ω/.In this design, we select the aluminium of 700 nanometer thickness as the data line material.The square resistance of the aluminium data line of 700 nanometers is 0.1 Ω/, satisfies the demands fully.But for high resolving power SXGA (1024 * 1280) for example, τ OndNeed to reduce to 0.02 μ s.For long data line C DlCan be increased to 64.1pF.It needs whole data line resistance to be no more than 25.6K Ω.This means the square resistance R of the maximum of data line MAX0.02 Ω/.Aluminium can not satisfy above demand.So, need the lower material of example resistivity as copper.
The FSC-LCDs of table 4 different resolution comprises square resistance to the demand of data line, and RC postpones and with the true resistance of the data line of following fabrication
Figure BSA00000677562700121
Final design
Based on above calculating, the present embodiment design is also made one 3 inches QVGA type FSC-LCD.The advantage of FSC-LCD is not need extra memory capacitance.So it is the addressing TFT of 24 μ m/2 * 5 μ m that the image element circuit on pixel only has a W/L.The aluminium that adopts 200 nanometers in the present embodiment is as sweep trace, and the square resistance on the straight line is 0.176 Ω.The LTO that deposits 50 nanometers is as gate insulator and deposit the oxide of 600 nanometers by PECVD as the sept of data line and sweep trace.Should be understood that oxide thickness is estimated as 120 nanometers, it often is mentioned in list of references.For the present embodiment, deposit the LTO of 50 nanometers, reduce the threshold voltage of TFT.As mentioned above, the W/L in our design is 2.4, is far longer than 0.06 calculated value.So thin-films Oxygen compound thickness can not have influence on the writing speed of TFT.For the image control process, the thin-films Oxygen compound can provide larger electric capacity this will be conducive to the voltage keep-process.The width of data line and sweep trace is fixed as 12 μ m.Figure 11 is 3 inches active driving substrate layout of QVGA TFT.
The making of active matrix backboard
At first utilize mask metal-induced crystallization method (MMIC) to prepare continuous band-shaped zone (CZD) polysilicon membrane: on the glass substrate that preparation process starts from covering with the silicon dioxide of plasma activated chemical vapour deposition 300nm, this glass substrate can be hawk 2000 glass substrate.Again with the method for the low-pressure chemical vapor deposition amorphous silicon at 550 ℃ of deposit 45nm.Samples of amorphous silicon is immersed the natural oxidizing layer that removed the surface in the solution that contains 1% hydrofluorite in 1 minute.Subsequently, the nanometer titanium dioxide silicon layer that 4nm is thick is formed at amorphous silicon surfaces.By the window of inducing of 1 micron of photoetching process formation, photoresist is removed under 120 ℃ of conditions by the mixed solution of sulfuric acid and hydrogen peroxide.Meanwhile, a very thin chemical oxide layer is formed at induces the line place, and approximately 1-2nm is thick.The nisiloy oxide of sputter one deck 10 dusts is on this body structure surface.Figure 12 is the schematic diagram of MMIC structure.The whole crystallization of amorphous silicon after 590 ℃ of lower annealing several hours obtain the CZD polysilicon membrane.
Among other embodiment of the present invention, the thickness of above-mentioned nanometer titanium dioxide silicon layer can also be 3 nanometers, 4 nanometers, 5 nanometers or 6 nanometers.
Among other embodiment of the present invention, induce the width of window can also be the 1-3 micron.
Among other embodiment of the present invention, the nisiloy oxide thickness is respectively a thickness between 7 dusts, 10 dusts, 14 dusts or this three.
Induce line can obtain the identical CZD metal induced crystallization poly-crystalline Si film of width film by setting in advance at nano silicon oxide cover layer.After the crystallization, the All Ranges of polysilicon layer can be as the active layer of high performance thin film transistor (TFTs), can overcome that the contraction of glass substrate causes to the version problem of misalignment.All transverse crystallization zones have accurate equal length and width, thus crystallization process can be controlled accurately and also at 590 ℃ of lower annealing times less than 1 hour.
In order relatively to use after CZD method and metal induced longitudinal crystallization method (MILC) crystallization residual nickel concentration in the polysilicon membrane, content and the distribution of using Tof-SIMS to measure nickel in CZD and MILC gained polysilicon.Nickel content in the CZD film is than lack 2 orders of magnitude (Figure 13 (a)) in the MILC film.Figure 13 (b) and shown respectively that (c) 2 dimensions (2D) of in CZD and MILC gained polysilicon membrane residual nickel distribute.In 2 dimension figure, mark nickel and/or nickel silicide with bright spot.(Figure 13 (b), the bright post of both sides are MIC zones to MILC polysilicon membrane in 2 dimension images, and middle dim lines are 2 crystal boundaries that the head-on collision of MILC zone forms.This nickel content that shows the crystal boundary that clashes is relatively higher, and the MIC zone is then very high.
(Figure 13 (c)) is similar to the MIC zone in the MILC film in the 2D of CZD polysilicon membrane image, in the nucleation areal distribution more nickel.But transverse metal is induced in the thin-film technique, and the content of nickel residual metal is more a lot of than nickeliferous ratio height of measuring one's own ability in nucleation zone and the transverse crystallization zone of wanting in the CZD polysilicon membrane in the polysilicon membrane in MIC and MILC zone.This means that not having the zone in the CZD polysilicon is the nickel that contains high concentration.Whole polysilicon membrane can be made the active layer of TFT.The nickel concentration that this means the CZD polysilicon membrane is lower, and homogeneity is higher.
In above-mentioned manufacture process, obtain after the CZD polysilicon membrane, prepare typical top grid TFTS with the CZD polysilicon membrane.The CZD polysilicon membrane becomes active silicon island with Freckle etching liquid wet etching, by the heavy method (LPCVD) of low pressure chemical gas phase at the low temperature oxide (LTO) of 425 ℃ of deposit 50 nanometer thickness as gate insulator.Form gate electrode, with boron with 4 * 10 15/ cm 2Metering Implantation source electrode and drain electrode.Oxide with the method for LPCVD deposition 500nm is opened the electrode contact hole as insulation course and in grid, source electrode and drain region.Subsequently, the aluminium photoetching that contains 1%Si of sputter 700 nanometer thickness forms electrode.420 ℃ of lower sintering 30 minutes to be to form good Ohmic contact in the forming gas of hydrogen and nitrogen, simultaneously dopant activation.
Then by stripping technology composition pixel electrode tin tin indium oxide (ITO) film.At last, the black matrix of definition is to reduce the reflex of aluminium electrode.So far panel is carried out the preparation that LCD integrates.Figure 14 is its synoptic diagram.Figure 15 (a) has showed the optical microscope photograph of 3 inches QVGA active array panels, and Figure 15 (b) is the enlarged photograph of a pixel region.
LCD integrates
The active array base plate of finishing is used to make a LCD.As previously described, must be very fast for the LCD pattern that requires of FSC.Transient mode based on the optics rebounce is used.The FSC that this pattern once was used to passive matrix shows.It is fixed against namely transient effect of optics bounce-back.Therefore it has overcome the harsh requirement that is used for willing LCD pattern.The principle of work details of LCD is former did explanation.
In fact, it is pointed out 3.7ms is only arranged a sub-frame time (sub-frame frequency is 90 * 3Hz), and this is difficult to realize turned to by a LC collating sequence one-period conversion of another LC collating sequence.Yet transient state generation speed is very fast.When being 5 μ m, gap of liquid crystal cell can obtain all GTGs in the 1.8ms.Driving voltage is very little, less than 4V.Since FSC, LED lights the time very short (1ms) and it does not need the LC sequence under stable state yet.A momentary status is perfectly worked.
It should be noted that at last, above embodiment is only in order to describe technical scheme of the present invention rather than the present technique method is limited, the present invention can extend to other modification, variation, application and embodiment on using, and therefore thinks that all such modifications, variation, application, embodiment are in spirit of the present invention and teachings.

Claims (10)

1. the active matrix backboard of a field-sequential color liquid crystal display comprises:
Substrate;
Polycrystalline SiTFT on the substrate, the raceway groove width/length ratio of this thin film transistor (TFT) is at least 0.06;
Sweep trace;
Data line.
2. active matrix backboard according to claim 1, wherein Pixel Dimensions is 200 * 200 μ m, and the width of sweep trace and data line is 12 μ m, and the minimum interval of the figure between the same layer is 5 μ m, and the minimum interval between different figures is 2 μ m.
3. active matrix backboard according to claim 1, wherein the raceway groove width/length ratio of polycrystalline SiTFT is at least 0.5.
4. active matrix backboard according to claim 1, wherein polycrystalline SiTFT has two separated grids, and the raceway groove width/length ratio of thin film transistor (TFT) is 24 μ m/5 μ m * 2.
5. active matrix backboard according to claim 1 also comprises pixel capacitance, pixel capacitance by and the data line of sweep trace different layers between electric capacity, sweep trace and LC thereon between electric capacity, the electric capacity between the addressing thin film transistor (TFT) form.
6. active matrix backboard according to claim 5, wherein the thickness of insulating material is 0.6 μ m between data line and sweep trace, the thickness of lc unit is 5 μ m.
7. active matrix backboard according to claim 1, wherein said liquid crystal display is the QVGA liquid crystal display, VGA liquid crystal display, XGA liquid crystal display or SXGA liquid crystal display.
8. active matrix backboard according to claim 1, wherein the active layer of polycrystalline SiTFT is continuous band-shaped regional polysilicon membrane.
9. active matrix backboard according to claim 8, the active layer of wherein said polycrystalline SiTFT is standby by mask metal-induced crystallization legal system, and the method comprises:
With plasma activated chemical vapour deposition silicon dioxide on glass substrate, again with the low-pressure chemical vapor deposition amorphous silicon membrane;
Form the nanometer titanium dioxide silicon layer on the amorphous silicon membrane surface, form by photoetching process and induce linear window, inducing the line place to form thin chemical oxide layer;
The nisiloy oxide of sputter one deck 7-14 dust on silicon dioxide layer and chemical oxide layer, high annealing is with the whole crystallization of amorphous silicon.
10. method of making active matrix backboard according to claim 1 comprises:
Deposition of amorphous silicon films on substrate;
Form the nanometer titanium dioxide silicon layer on the amorphous silicon membrane surface, form by photoetching process and induce linear window, inducing the line place to form thin chemical oxide layer;
The nisiloy oxide of sputter one deck 7-14 dust on silicon dioxide layer and chemical oxide layer, high annealing form polysilicon layer with the whole crystallization of amorphous silicon;
As active layer, make polycrystalline SiTFT with this polysilicon layer;
Form data line and sweep trace.
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Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103151388B (en) * 2013-03-05 2015-11-11 京东方科技集团股份有限公司 A kind of polycrystalline SiTFT and preparation method thereof, array base palte
CN103235439B (en) * 2013-04-08 2015-08-12 北京京东方光电科技有限公司 A kind of to box substrate and preparation method, touch-screen, display device
CN104282546A (en) * 2013-07-08 2015-01-14 上海和辉光电有限公司 Method for improving homogeneity of polycrystalline silicon layer
CN103700688B (en) * 2013-12-23 2016-03-30 京东方科技集团股份有限公司 Color membrane substrates and preparation method thereof, display unit
CN103700698B (en) 2013-12-30 2016-06-15 北京京东方光电科技有限公司 The preparation method of a kind of thin film transistor, thin film transistor and display panel
US9793361B2 (en) 2014-09-10 2017-10-17 Boe Technology Group Co., Ltd. Thin film transistor, array substrate and display device
CN104241395B (en) * 2014-09-10 2017-02-15 京东方科技集团股份有限公司 Thin film transistor, array substrate and displaying device
CN105514023B (en) * 2014-09-22 2018-07-24 上海和辉光电有限公司 A kind of contact hole interface processing method
CN104505340B (en) * 2014-11-28 2017-12-26 信利（惠州）智能显示有限公司 A kind of preparation method of low-temperature polysilicon film
CN106033707A (en) * 2015-03-10 2016-10-19 上海和辉光电有限公司 Preparation method for polysilicon film
CN105575974B (en) * 2015-12-14 2018-08-14 深圳市华星光电技术有限公司 The production method of low temperature polycrystalline silicon TFT backplate
CN106298802B (en) * 2016-08-16 2019-05-07 武汉华星光电技术有限公司 A kind of LTPS array substrate and manufacturing method, display panel
CN106328506B (en) * 2016-08-31 2020-04-10 上海华力微电子有限公司 Method for reducing photoresist stripping risk of ion implantation layer
CN106601873B (en) * 2016-12-16 2018-06-29 苏州腾晖光伏技术有限公司 A kind of spin coating device for CZTS films and the method for preparing CZTS batteries
JP7032434B2 (en) * 2017-01-04 2022-03-08 曾 世憲 Display device
CN106876479B (en) 2017-04-19 2020-03-06 京东方科技集团股份有限公司 Thin film transistor and preparation method thereof, array substrate and preparation method thereof, and display panel
CN109742028B (en) * 2018-12-25 2021-04-02 惠科股份有限公司 Manufacturing method of thin film transistor, thin film transistor and display panel
DE102019100312A1 (en) * 2019-01-08 2020-07-09 Parcan NanoTech Co. Ltd. Controlled ion implantation substrate and method of making a controlled ion implantation substrate
CN112736087B (en) * 2019-10-10 2024-03-05 京东方科技集团股份有限公司 Manufacturing method of array substrate, array substrate and display panel
CN110660869A (en) * 2019-10-27 2020-01-07 南京飞芯电子科技有限公司 Method for forming enhancement mode field effect transistor
CN112563197B (en) * 2020-11-24 2022-03-22 惠科股份有限公司 Active switch, manufacturing method thereof and display panel

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1197933A (en) * 1997-04-30 1998-11-04 内田龙男 Liquid crystal display
US20030164501A1 (en) * 1999-01-11 2003-09-04 Kenkichi Suzuki Semiconductor device including a TFT having large-grain polycrystalline active layer, LCD employing the same and method of fabricating them
CN101086962A (en) * 2006-03-13 2007-12-12 香港科技大学 Metal-induced crystallization of amorphous silicon
CN101369605A (en) * 2007-08-13 2009-02-18 株式会社日立显示器 Display device
CN102129962A (en) * 2010-10-28 2011-07-20 广东中显科技有限公司 Controllable method for manufacturing polysilicon thin film through metal induction

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5783047A (en) * 1980-11-10 1982-05-24 Matsushita Electric Ind Co Ltd Polycrystalline semiconductor resistor
TW520072U (en) * 1991-07-08 2003-02-01 Samsung Electronics Co Ltd A semiconductor device having a multi-layer metal contact
JPH06104438A (en) * 1992-09-22 1994-04-15 Casio Comput Co Ltd Film transistor
JPH08139335A (en) * 1994-11-14 1996-05-31 Casio Comput Co Ltd Method of manufacturing thin film transistor
JPH11354800A (en) * 1998-06-04 1999-12-24 Hitachi Ltd Thin-film transistor, its forming method, and liquid crystal display device
JP4436469B2 (en) * 1998-09-30 2010-03-24 三洋電機株式会社 Semiconductor device
JP2000133807A (en) * 1998-10-22 2000-05-12 Seiko Epson Corp Polycrystalline silicon thin-film transistor
TWI243432B (en) * 1999-10-29 2005-11-11 Hitachi Ltd Semiconductor device, method of making the same and liquid crystal display device
JP3873811B2 (en) * 2002-05-15 2007-01-31 日本電気株式会社 Manufacturing method of semiconductor device
KR100930362B1 (en) * 2002-11-04 2009-12-08 엘지디스플레이 주식회사 Polycrystalline Silicon Film Formation Method And Manufacturing Method Of Thin Film Transistor Including The Same
KR100577795B1 (en) * 2003-12-30 2006-05-11 비오이 하이디스 테크놀로지 주식회사 Method for forming polycrystalline silicon film
TWI266427B (en) * 2004-06-01 2006-11-11 Yamanashi Tlo Co Ltd Field-effect transistor and method of manufacturing same
TWI241027B (en) * 2004-09-30 2005-10-01 Ind Tech Res Inst Method of preparing electronic device
US8088676B2 (en) * 2005-04-28 2012-01-03 The Hong Kong University Of Science And Technology Metal-induced crystallization of amorphous silicon, polycrystalline silicon thin films produced thereby and thin film transistors produced therefrom
US8013957B2 (en) * 2005-05-21 2011-09-06 The Hong Kong University Of Science And Technology Transflective liquid crystal device and method of manufacturing the same
US8426865B2 (en) * 2007-06-22 2013-04-23 The Hong Kong University Of Science And Technology Polycrystalline silicon thin film transistors with bridged-grain structures
CN101834138A (en) * 2010-02-09 2010-09-15 广东中显科技有限公司 Method for preparing transistor device of crystallized thin film
CN101834211A (en) * 2010-02-09 2010-09-15 广东中显科技有限公司 Polycrystalline silicon thin film based on metal induction
CN101814438A (en) * 2010-05-17 2010-08-25 广东中显科技有限公司 Preparation method of thin film transistor based on induced longitudinal crystallization polycrystalline silicon
CN101819999A (en) * 2010-05-17 2010-09-01 广东中显科技有限公司 Multilayer film structure for transverse induced crystallization of low-temperature poly-silicon film
CN101853784B (en) * 2010-05-17 2012-07-04 广东中显科技有限公司 Method for transversely inducing and crystallizing low-temperature polycrystalline silicon film
CN102082098A (en) * 2010-12-15 2011-06-01 四川虹视显示技术有限公司 Method for producing low-temperature polysilicon thin-film transistor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1197933A (en) * 1997-04-30 1998-11-04 内田龙男 Liquid crystal display
US20030164501A1 (en) * 1999-01-11 2003-09-04 Kenkichi Suzuki Semiconductor device including a TFT having large-grain polycrystalline active layer, LCD employing the same and method of fabricating them
CN101086962A (en) * 2006-03-13 2007-12-12 香港科技大学 Metal-induced crystallization of amorphous silicon
CN101369605A (en) * 2007-08-13 2009-02-18 株式会社日立显示器 Display device
CN102129962A (en) * 2010-10-28 2011-07-20 广东中显科技有限公司 Controllable method for manufacturing polysilicon thin film through metal induction

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