CN102129962A - Controllable method for manufacturing polysilicon thin film through metal induction - Google Patents
Controllable method for manufacturing polysilicon thin film through metal induction Download PDFInfo
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- CN102129962A CN102129962A CN 201010529564 CN201010529564A CN102129962A CN 102129962 A CN102129962 A CN 102129962A CN 201010529564 CN201010529564 CN 201010529564 CN 201010529564 A CN201010529564 A CN 201010529564A CN 102129962 A CN102129962 A CN 102129962A
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Abstract
The invention provides a controllable method for manufacturing a polysilicon thin film through metal induction. The method comprises the following steps: 1) providing an insulating substrate and forming a barrier layer and an amorphous silicon layer on the insulating substrate in sequence; 2) forming a buffer layer on the amorphous silicon layer, photoetching a groove on the buffer layer and ensuring certain distance to exist between the bottom of the groove and the upper surface of the amorphous silicon layer; 3) depositing a metal induction layer on the photoetched buffer layer; 4) carrying out annealing in the protective gas and crystallization; and 5) removing the buffer layer and the metal induction layer. By adopting the method, the polysilicon thin film with big and uniform grains and regular grain boundary can be manufactured, and meanwhile, the metals do not directly contact with the silicon layer, thus avoiding the pollution caused by the residual metals.
Description
Technical field
The present invention relates to a kind of manufacture method of low-temperature polysilicon film, particularly a kind of improved metal inducement that utilizes makes the amorphous silicon crystallization, thereby obtains the manufacture method of high-quality polysilicon.
Background technology
Along with high-tech development, video product, particularly digitlization video signal or device for image have become product common in the general daily life.In these digitlization video signals or the device for image, display is the element that is even more important.In order to improve the performance of display, usually adopt TFT to form pixel drive circuit and peripheral driving circuit thereof, these TFT adopt polysilicon membrane as its active layer mostly, and drive circuit and display element are produced on the transparent glass substrate with low cost together, this all requires the better performances of polysilicon membrane, and requires to make under cryogenic conditions.
The technology that quasi-molecule laser annealing and metal inducement prepare polysilicon is two kinds of conventional methods of preparation polysilicon membrane in the present industry.Compare with the method for quasi-molecule laser annealing, the metal inducement technology can obtain the mobility height, the polysilicon membrane that has an even surface, and manufacture craft and equipment are also comparatively simple.But this method also exists some problems at present, and after for example crystallization was finished, near the metal residual the induction port was overweight.In order to address this problem, the common employing of people at present will induce metal level to do very thinly, or after annealing in process, adopt PSG to absorb, or adopt from the control of composite materials such as slowly-releasing and induce the methods such as diffusion of metal at amorphous silicon material, but these methods all can't thoroughly be avoided can leaving metal residual near induction port, also can't realize the regulation and control to the crystallization zone simultaneously.
Summary of the invention
Therefore, the objective of the invention is to overcome the defective of above-mentioned prior art, a kind of regulatable metal inducement method for manufacturing polycrystalline silicon thin film is provided, when keeping traditional horizontal inductive technology advantage of metal, also can avoid effectively, and then improve the electrical property of polysilicon layer in the overweight problem of the metal residual of induction port.
The objective of the invention is to be achieved through the following technical solutions:
According to the present invention, a kind of manufacture method of regulatable metal inducement polysilicon membrane is provided, comprising:
Step 1): dielectric substrate is provided, on described dielectric substrate, forms barrier layer and amorphous silicon layer successively;
Step 2): on described amorphous silicon layer, form resilient coating, and on this resilient coating, make groove by lithography, make to have certain distance between the upper surface of the bottom of described groove and described amorphous silicon layer;
Step 3): on through the resilient coating after the described photoetching, deposit the layer of metal inducing layer;
Step 4): the crystallization of in protective gas, annealing;
Step 5): remove resilient coating and metal induction layer.
In said method, the distance after the described photoetching between the bottom portion of groove of resilient coating and the amorphous silicon layer upper surface is 10nm to 100nm.
In said method, the distance after the described photoetching between the bottom portion of groove of resilient coating and the amorphous silicon layer upper surface is 30nm.
In said method, the described resilient coating of stating is made by silica or silicon nitride, and thickness is more than the 100nm.
In said method, described groove is the groove that a plurality of areas equate.
In said method, each area of described groove is at 400 μ m
2More than.
In said method, each area of described groove is at 400 μ m
2To 3600 μ m
2Between.
In said method, described groove is square, circle or polygon.
In said method, the thickness of described metal induction layer is a few nanometer to tens nanometers.
Compared with prior art, the invention has the advantages that:
1. reduced the kish after crystallization is finished;
2. method is simple, Modulatory character is high.
Description of drawings
It is following that embodiments of the present invention is further illustrated with reference to accompanying drawing, wherein:
Figure 1A to Fig. 1 E is the schematic cross-section that forms layer polysilicon film according to each step of the inventive method;
Fig. 2 is the local schematic top plan view of the polysilicon membrane that obtains through the inventive method;
Fig. 3 A to Fig. 3 C is the design sketch of the formed layer polysilicon film of induction port of employing different area.
Embodiment
According to the present invention, a kind of preparation method of regulatable metal inducement polysilicon membrane is provided, this method may further comprise the steps:
At first, shown in Figure 1A, adopting insulating material, deposition one deck barrier layer 11 on the dielectric substrate of making as glass or quartz etc. 10 is used to stop the diffusion to the upper strata of moisture on the substrate or other foreign body; Deposition one deck amorphous silicon membrane layer 12 on barrier layer 11, amorphous silicon membrane 12 adopts the physical deposition method growth that deposits (PECVD) or low-pressure chemical vapor deposition (LPCVD) such as plasma enhanced chemical mutually; Then regrowth one deck is induced metal buffer layer 13A on amorphous silicon membrane 12, and this induces the material of metal buffer layer can be silica or silicon nitride, and its thickness is generally more than 100 nanometers;
Second step, shown in Figure 1B, 13A carries out photoetching to this metal inducement resilient coating, make groove 15 (or being called induction port) by lithography, and make that having certain distance 16 between the bottom of induction port 15 after the photoetching and amorphous silicon layer 12 upper surfaces (sees Fig. 1 D, hereinafter referred to as " buffer distance "), the metal inducement resilient coating after the photoetching is denoted as 13B;
In the 3rd step, shown in Fig. 1 C, at the surface coverage layer of metal inducing layer 14 of resilient coating 13B, this induces metal level 14 can adopt metal Ni, and Au, Cu, Al, Pd, Co or Ag, these metals can adopt method preparations such as sputter, thermal evaporation and electron beam evaporation;
In the 4th step, annealing (as 400 degrees centigrade to 800 degrees centigrade) adopts protective gas (as nitrogen) that sample is protected in the annealing process under cryogenic conditions, and the time of annealing was generally 1 to 10 hour; Film after the annealed processing is shown in Fig. 1 D, and the metal of inducing in the metal induction layer 14 is diffused in the amorphous silicon layer 12 by buffer distance 16, forms seed region 17 below induction port 15; Wherein the area of this seed region 17 is 15 more bigger than induction port, shape is similar, but still can think that seed region 17 areas are substantially equal to the induction port area; Carrying out along with crystallization, shown in Fig. 1 E, 18 beginning crystallizations around beyond the seed region 17, the size in crystallization field 18 is that the area by seed region 17 decides, the distribution of crystal boundary also is clocklike (because the growth of polysilicon is to be radiation growth around the middle mind-set with seed region 17, so overall slightly circular (see figure 2) of crystallization meeting, as for seed region 17, because the crystal grain number and the position that form in it can not be controlled, so the crystal boundary direction that forms in the seed region 17 is irregular);
The 5th step, treat that crystallization is finished after, adopt the method for dry method or wet etching will induce metal level 14 and resilient coating 13B to remove separately or together, guarantee that simultaneously polysilicon layer and dielectric substrate are not damaged in the etching process, thereby make polysilicon membrane.
Fig. 2 is the partial top view of the polysilicon membrane that obtains through the inventive method.Seed region 17 among the figure is a square, and seed region 17 is other shape in fact, also is fine as circle, polygon etc.Crystallization field 18 is that the center forms along direction 21 growths with seed region 17.Because the growth of crystal is be center radiation growth with seed region 17, so just formed many directive crystal boundaries in 18 the insides, crystallization field, just hangs down angle grain circle 22.Low angle grain circle 22 is the crystal boundary of the crystal grain generation of crystallization field 18 inner different qualities.Angle of elevation grain circle 23 is the crystal boundary line in crystallization field 18, just with other seed region be the polysilicon at center intersect or with the crossing boundary line of uncrystallized amorphous silicon also.So the crystal grain in the crystallization field 18 has big or small homogeneous, the characteristics of the crystal boundary regularity of distribution.
Example 1:
Step 1): at first on plate glass substrate 10, adopt the PECVD method to deposit 200 nanometer LTO (low temperature oxide) and do barrier layer 11, adopting the PECVD deposit thickness on barrier layer 11 is the amorphous silicon layer 12 of 60nm, underlayer temperature is 200 degree during deposition, and base vacuum is 2 * 10
-4Pa, chamber pressure 80pa, then deposition one layer thickness is the SiN of 300 nanometers on amorphous silicon layer 12
XLayer is as metal buffer layer 13A, and the growth of this layer film utilizes PECVD at SiH equally
4And NH
3Down growth of mixed atmosphere, underlayer temperature remains on 270 degree, chamber pressure is 30pa;
Step 2): above-mentioned metal inducement resilient coating 13A is carried out photoetching, and making a plurality of areas by lithography is the induction port 15 of 10 μ m * 10 μ m, makes that the buffer distance 16 between the upper surface of the bottom of induction port 15 after the photoetching and amorphous silicon layer 12 is 5 nanometers;
Step 3): the gained sample is put into magnetic control platform growth one deck induce metal 14, the thickness of this layer is 5 nanometers, uses metal Ni as inducing metal, and underlayer temperature is 130 degree during growth, and base vacuum is 2 * 10
-4Pa, chamber pressure is 0.1pa during sputter;
Step 4): utilize quick anneal oven to anneal 4 hours down, pass to nitrogen therebetween as protective gas at 520 ℃;
Step 5): annealing erodes remaining metal Ni with watery hydrochloric acid after finishing, and last using plasma etching technics is at CF
4Carve metal buffer layer 13B under the atmosphere, polysilicon layer that stays and substrate use for element manufacturing.
Prepare example 2～6 according to the method described above, concrete experiment condition and result are referring to table 1.
Table 1
Fig. 3 A to Fig. 3 C shows the design sketch of layer polysilicon film of the corresponding different induction port sizes of example 1～6.With reference to Fig. 3 A, when the area of induction port 31 is 100 μ m
2, do not form the crystallization field substantially; When the area of induction port 32 is 400 μ m
2, can see that crystallization field 39 begins to form.With reference to Fig. 3 B～Fig. 3 C, the area that can see crystallization field 39 is to increase along with the increase of induction port.Because the metal of inducing at induction port place does not directly contact with the amorphous silicon layer surface in the present invention, but is diffused into amorphous silicon surfaces by buffer distance 16, so just can control the area of seed region 17 by the design of induction port area and buffering distance 16.From the effect of diffusion, the area of induction port is big more, and the area of seed region 17 is also big more.Because the crystallization of polysilicon is from seed region 17, the area of seed region 17 will have influence on the crystallization radius of polysilicon afterwards again.Should be appreciated that, the big young pathbreaker of buffer distance 16 has influence on and induces metal layer thickness (or concentration) and buffer time, buffer distance 16 is big more, mean bigger (can reach nanoscale) of inducing metal layer thickness (or concentration) to do so that bigger thickness, but also correspondingly increased buffer time, so those skilled in the art should suitably select buffer distance according to above-mentioned triangular relation.In addition, as required, described induction port can be set to one or more, and the size of each induction port can be the same or different.
Should be appreciated that, in the present invention, just can realize the object of the invention as long as between the upper surface of bottom portion of groove and amorphous silicon layer, have certain distance, and buffer distance 16 is being preferred between the 10nm to 100nm approximately, if this is because less than 10nm, buffering effect is limited, if greater than 100nm, then will increase the time of induction port catalytic metal by resilient coating.Certainly, should be appreciated that to those skilled in the art, can determine suitable buffer distance 16 according to the thickness of metal induction layer.In other embodiments of the invention, the thickness of metal induction layer 14 preferably in several nanometers to tens nanometers; Described annealing temperature can be at 400 ℃ to 800 ℃, and the time can be at 1 to 10 hour.
Compare with other the method for minimizing induction port kish, more simple on the method technology of the present invention, owing to avoided inducing metal level to contact with the direct of semiconductor layer, so can reduce better crystallization finish after kish to the pollution of semiconductor layer, reduce influence to device (as TFT).
Although the present invention is made specific descriptions with reference to the above embodiments, but for the person of ordinary skill of the art, should be appreciated that and to make amendment based on content disclosed by the invention within spirit of the present invention and the scope or improve not breaking away from, these modifications and improving all within spirit of the present invention and scope.
Claims (10)
1. the manufacture method of a regulatable metal inducement polysilicon membrane comprises:
Step 1): dielectric substrate is provided, on described dielectric substrate, forms barrier layer and amorphous silicon layer successively;
Step 2): on described amorphous silicon layer, form resilient coating, and on this resilient coating, make groove by lithography, make to have certain distance between the upper surface of the bottom of described groove and described amorphous silicon layer;
Step 3): on through the resilient coating after the described photoetching, deposit the layer of metal inducing layer;
Step 4): the crystallization of in protective gas, annealing;
Step 5): remove resilient coating and metal induction layer.
2. a kind of regulatable metal inducement method for manufacturing polycrystalline silicon thin film according to claim 1 is characterized in that the distance after the described photoetching between the bottom portion of groove of resilient coating and the amorphous silicon layer upper surface is 10nm to 100nm.
3. a kind of regulatable metal inducement method for manufacturing polycrystalline silicon thin film according to claim 2 is characterized in that the distance after the described photoetching between the bottom portion of groove of resilient coating and the amorphous silicon layer upper surface is 30nm.
4. a kind of regulatable metal inducement method for manufacturing polycrystalline silicon thin film according to claim 1 is characterized in that the described resilient coating of stating is made by silica or silicon nitride, and thickness is more than the 100nm.
5. a kind of regulatable metal inducement method for manufacturing polycrystalline silicon thin film according to claim 1 is characterized in that, described groove is the groove that a plurality of areas equate.
6. a kind of regulatable metal inducement method for manufacturing polycrystalline silicon thin film according to claim 5 is characterized in that each area of described groove is at 400 μ m
2More than.
7. a kind of regulatable metal inducement method for manufacturing polycrystalline silicon thin film according to claim 6 is characterized in that each area of described groove is at 400 μ m
2To 3600 μ m
2Between.
8. a kind of regulatable metal inducement method for manufacturing polycrystalline silicon thin film according to claim 7 is characterized in that, described groove is square, circle or polygon.
9. a kind of regulatable metal inducement method for manufacturing polycrystalline silicon thin film according to claim 1 is characterized in that the thickness of described metal induction layer is a few nanometer to tens nanometers.
10. according to each described a kind of regulatable metal inducement method for manufacturing polycrystalline silicon thin film in the claim 1 to 9; it is characterized in that; the temperature of described annealing crystallization is 400 degrees centigrade to 800 degrees centigrade, and the time is 1 to 10 hour, and the employing protective gas is a nitrogen.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102955307A (en) * | 2011-08-23 | 2013-03-06 | 广东中显科技有限公司 | Field sequential color liquid crystal display based on polycrystalline silicon thin film transistor |
| CN112563196A (en) * | 2020-11-24 | 2021-03-26 | 惠科股份有限公司 | Manufacturing method of active switch and display panel |
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|---|---|---|---|---|
| CN1316770A (en) * | 2001-03-15 | 2001-10-10 | 东南大学 | Process for preparing polysilicon film |
| KR20040040762A (en) * | 2002-11-08 | 2004-05-13 | 진 장 | Method of phase transition of amorphous material using a cap layer |
| US20050019995A1 (en) * | 2003-07-24 | 2005-01-27 | Mao-Yi Chang | [method of fabricating polysilicon film] |
| CN1595613A (en) * | 2004-06-30 | 2005-03-16 | 吉林大学 | A method for making metal induced polysilicon film having diffuse layer above metal |
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2010
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1316770A (en) * | 2001-03-15 | 2001-10-10 | 东南大学 | Process for preparing polysilicon film |
| KR20040040762A (en) * | 2002-11-08 | 2004-05-13 | 진 장 | Method of phase transition of amorphous material using a cap layer |
| US20050019995A1 (en) * | 2003-07-24 | 2005-01-27 | Mao-Yi Chang | [method of fabricating polysilicon film] |
| CN1595613A (en) * | 2004-06-30 | 2005-03-16 | 吉林大学 | A method for making metal induced polysilicon film having diffuse layer above metal |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102955307A (en) * | 2011-08-23 | 2013-03-06 | 广东中显科技有限公司 | Field sequential color liquid crystal display based on polycrystalline silicon thin film transistor |
| CN102956710A (en) * | 2011-08-23 | 2013-03-06 | 广东中显科技有限公司 | Mask metal induced crystallized polycrystalline silicon thin-film transistor |
| CN112563196A (en) * | 2020-11-24 | 2021-03-26 | 惠科股份有限公司 | Manufacturing method of active switch and display panel |
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Application publication date: 20110720 |