CN202306376U - Reference current source circuit - Google Patents
Reference current source circuit Download PDFInfo
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- CN202306376U CN202306376U CN2011204275611U CN201120427561U CN202306376U CN 202306376 U CN202306376 U CN 202306376U CN 2011204275611 U CN2011204275611 U CN 2011204275611U CN 201120427561 U CN201120427561 U CN 201120427561U CN 202306376 U CN202306376 U CN 202306376U
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Abstract
The utility model provides a reference current source circuit, which comprises a reference voltage generation module, a voltage buffer, an equivalent resistor, a filtering capacitor, a current mirror module and a reference current output terminal. The voltage buffer comprises an operational amplifier and first a field effect transistor. The current mirror module comprises a second field effect transistor and a third field effect transistor. The equivalent resistor comprises an oscillator, a fourth field effect transistor, a fifth field effect transistor, and a capacitor connected with the fourth field effect transistor and the fifth field effect transistor. The oscillator generates a clock signal with the frequency of the clock signal related to a charging and discharging capacitor arranged in the oscillator so as to control the charging and the discharging of the internal capacitance of the equivalent resistor. The reference current output terminal outputs a reference current related to the ratio of the above capacitor to the charging and discharging capacitor. The reference current source circuit is simple in structure and reduces the cost of chips.
Description
Technical field
The utility model relates to a kind of reference current source circuit, refers to a kind of reference current source circuit that need not plug-in resistance especially.
Background technology
See also Fig. 1; Fig. 1 is existing reference current source circuit structure; Existing reference current source circuit all produces through resistance R 31, and its reference current value equals the resistance of the reference voltage level Vref of reference voltage end divided by resistance R 31, so the absolute value of reference current value and resistance is relevant.Because in semiconductor technology; The absolute value of resistance has positive and negative 10% deviation, so when the high-precision reference current source of needs, resistance or plug-in; Alignment mechanism through back end test is revised resistance value, yet these two kinds of methods have all increased the cost of chip.
Can know that by above analysis existing reference current terminal circuit needs plug-in resistance to produce high-precision reference current source usually, thereby has increased the cost of chip.
Summary of the invention
In view of above content, be necessary to provide a kind of reference current source circuit that need not plug-in resistance.
A kind of reference current source circuit; Said reference current source circuit comprises the reference current output terminal that current mirror module and that filter capacitor, that equivalent resistance, that voltage buffer, that a reference voltage generation module, links to each other with said reference voltage generation module links to each other with said voltage buffer links to each other with said voltage buffer links to each other with said voltage buffer links to each other with said current mirror module; Said voltage buffer comprises first FET that an operational amplifier and links to each other with said operational amplifier; Said current mirror module comprises the 3rd FET that one second FET and links to each other with said second FET; Said equivalent resistance comprises the electric capacity that the 5th FET and that the 4th FET, that an oscillator, links to each other with said oscillator links to each other with said oscillator links to each other with said the 4th FET and said the 5th FET; Said oscillator produces the relevant clock signal of a charge and discharge capacitance in a frequency and the said oscillator and controls discharging and recharging of electric capacity in the said equivalent resistance, and said reference current output terminal is exported a reference current relevant with the ratio of said electric capacity and said charge and discharge capacitance.
Preferably; Said reference voltage generation module links to each other with a normal phase input end of said operational amplifier; One inverting input of said operational amplifier links to each other with the source class of the source class of said first FET, said the 4th FET and an end of said filter capacitor, and an output terminal of said operational amplifier links to each other with the grid of said first FET.
Preferably; The grid of the drain electrode of said first FET, said second FET links to each other with the grid of drain electrode with said the 3rd FET; The drain electrode of said the 3rd FET links to each other with said reference current output terminal, and the source class of said second FET is connected a power end jointly with the source class of said the 3rd FET.
Preferably; The grid of said the 4th FET is connected said oscillator jointly with the grid of said the 5th FET; The drain electrode of said the 4th FET links to each other with the drain electrode of said the 5th FET and an end of said electric capacity, the common earth terminal that connects of the other end of the source class of said the 5th FET, the other end of said electric capacity and said filter capacitor.
Preferably, said oscillator also comprises the 14 FET that the 13 FET, that the 12 FET, that the 11 FET, that the tenth FET, that the 9th FET, that the 8th FET, that the 7th FET, that one the 6th FET, links to each other with said the 6th FET links to each other with said the 6th FET and said the 7th FET links to each other with said the 8th FET links to each other with said the 9th FET links to each other with said the 9th FET and said the tenth FET links to each other with said the 11 FET links to each other with said the 6th FET links to each other with said the 13 FET.
Preferably, said oscillator comprises that also first resistance, one that the 21 FET, that the 20 FET, that the 19 FET, that the 18 FET, that the 17 FET, that the 16 FET, that 1 the 15 FET, links to each other with said the 9th FET links to each other with said the 16 FET links to each other with said the 12 FET links to each other with said the 18 FET links to each other with said the 11 FET links to each other with said the 20 FET links to each other with said the 13 FET is connected in the rest-set flip-flop that second comparer and that first comparer, that the 3rd resistance, one that second resistance, one between said the 8th FET and said the 15 FET links to each other with said the 16 FET links to each other with said second resistance links to each other with said first comparer links to each other with several first comparers and said second comparer.
Relative prior art, the reference current of the utility model reference current source circuit output is only relevant with capacitance ratio, need not produce reference current by plug-in resistance, and is simple in structure, and reduced the cost of chip.
Description of drawings
Fig. 1 is the circuit diagram of existing reference current source circuit.
Fig. 2 is the system chart of the utility model reference current source circuit preferred embodiments.
Fig. 3 is the circuit diagram of the utility model reference current source circuit preferred embodiments.
Fig. 4 is the circuit diagram of oscillator in the utility model reference current source circuit preferred embodiments.
Embodiment
See also Fig. 2 and Fig. 3, the utility model reference current source circuit preferred embodiments comprises the reference current output terminal Iout that current mirror module and that filter capacitor C1, that equivalent resistance, that voltage buffer, that a reference voltage generation module VREF, links to each other with this reference voltage generation module VREF links to each other with this voltage buffer links to each other with this voltage buffer links to each other with this voltage buffer links to each other with this current mirror module.Wherein, this voltage buffer comprises the first FET M1 that an operational amplifier OP and links to each other with this operational amplifier OP; This current mirror module comprises the 3rd FET M3 that one second FET M2 and links to each other with this second FET M2; This equivalence resistance comprises the capacitor C 2 that the 5th FET M5 and that the 4th FET M4, that an oscillator OSC, links to each other with this oscillator OSC links to each other with this oscillator OSC links to each other with the 4th FET and the 5th FET M5.
This reference voltage generation module VREF is used to produce a reference voltage V ref.This voltage buffer is used to make that the source class voltage of this first FET M1 equals this reference voltage V ref.This filter capacitor C1 is used for eliminating the high fdrequency component of reference current.This oscillator OSC is used to produce a clock signal Fosc and controls discharging and recharging of this capacitor C 2.This current mirror module is used for reference current through this reference current output terminal Iout output.
The physical circuit annexation of the utility model reference current source circuit preferred embodiments is following: this reference voltage generation module VREF links to each other with the normal phase input end OP of this operational amplifier OP; The inverting input of this operational amplifier OP is connected with the source class of this first FET M1, the source class of the 4th FET M4 and the end of this filter capacitor C1 jointly, and the output terminal of this operational amplifier OP links to each other with the grid of this first FET M1.The drain electrode of this first FET M1 links to each other with the grid of grid, drain electrode and the 3rd FET M3 of this second FET M2; The drain electrode of the 3rd FET M3 links to each other with this reference current output terminal Iout, and the source class of this second FET M2 is connected a power end AVD jointly with the source class of the 3rd FET M3.The grid of the 4th FET M4 is connected this oscillator OSC jointly with the grid of the 5th FET M5; The drain electrode of the 4th FET M4 links to each other with the drain electrode of the 5th FET M5 and an end of this capacitor C 2, the common earth terminal AVS that connects of the other end of the other end of the source class of the 5th FET M5, this capacitor C 2 and this filter capacitor C1.
See also Fig. 4, Fig. 4 is the circuit diagram of oscillator OSC in the utility model reference current source circuit preferred embodiments.This oscillator OSC comprises one the 6th FET M6; One the 7th FET M7; One the 8th FET M8; One the 9th FET M9; The tenth a FET M10; The 11 a FET M11; The 12 a FET M12; The 13 a FET M13; The 14 a FET M14; The 15 a FET M15; The 16 a FET M16; The 17 a FET M17; The 18 a FET M18; The 19 a FET M19; One the 20 FET M20; One the 21 FET M21; One first resistance R 1; One second resistance R 2; One the 3rd resistance R 3; The charge and discharge capacitance C3 that one oscillator OSC is inner; One first comparator C OM1; One second a comparator C OM2 and a rest-set flip-flop.
The physical circuit annexation of this oscillator OSC is following: the grid of the grid of the 6th FET M6 and drain electrode, the 7th FET M7, the grid of the 8th FET M8 link to each other with the drain electrode of the 13 FET M13.The drain electrode of the 7th FET M7 links to each other with the grid of the grid of the 14 FET M14 and drain electrode and the 13 FET M13.The drain electrode of the 8th FET M8 links to each other with an end of this second resistance R 2 and the normal phase input end INP of this first comparator C OM1.The grid of the grid of the 9th FET M9 and drain electrode, the tenth FET M10, the grid of the 11 FET M11, the grid of the 12 FET M12 link to each other with the drain electrode of the 16 FET M16.The drain electrode of the tenth FET M10, the grid of the 17 FET M17 and drain electrode link to each other with the grid of the 16 FET M16.The drain electrode of the 11 FET M11, the grid of the 20 FET M20 and drain electrode link to each other with the grid of the 21 FET M21.The drain electrode of the 12 FET M12 links to each other with the source class of the 18 FET M18.The source class of the 13 FET M13 links to each other with an end of this first resistance R 1.The other end of the grid of the 15 FET M15 and drain electrode, this second resistance R 2 links to each other with the inverting input INN of this second comparator C OM2.The source class of the 16 FET M16 links to each other with an end of the 3rd resistance R 3.The grid of the 18 FET M18 and the grid of the 19 FET M19 are connected one first output terminal Q of this rest-set flip-flop jointly, and the end of the drain electrode of the 18 FET M18, the drain electrode of the 19 FET M19, this charge and discharge capacitance C3 links to each other with the inverting input INN of this first comparator C OM1 and the normal phase input end INP of this second comparator C OM2 jointly.The source class of the 19 FET M19 links to each other with the drain electrode of the 21 FET M21.The output terminal of this first comparator C OM1 links to each other with a first input end S of this rest-set flip-flop, and the output terminal of this second comparator C OM2 links to each other with one second input end R of this rest-set flip-flop.One second output terminal QN clock signal Fosc of this rest-set flip-flop is to the grid of the 4th FET M4 and the 5th FET M5.The source class of the source class of the source class of the source class of the source class of the source class of the 6th FET M6, the 7th FET M7, the 8th FET M8, the 9th FET M9, the tenth FET M10, the source class of the 11 FET M11 and the 12 FET M12 connects power end AVD jointly, and the source class of the other end of this first resistance R 1, the source class of the 14 FET M14, the 15 FET M15, the other end of the 3rd resistance R 3, the source class of the 17 FET M17, the source class of the 20 FET M20, the source class of the 21 FET M21 and the other end of this charge and discharge capacitance C3 connect earth terminal AVS jointly.
The principle Analysis of the utility model reference current source circuit preferred embodiments is following:
The 13 FET M13 and the 14 FET M14 work in the saturation region, and the ratio of its breadth length ratio is K1.
The 6th FET M6 and the 7th FET M7 form current mirror, according to circuit working state, and ignore the inclined to one side effect of lining of FET, and the electric current that can obtain flowing through this first resistance R 1 is:
Wherein,
is negative temperature coefficient;
is grid oxygen electric capacity, and
is the breadth length ratio of the 13 FET M13.
So the voltage difference at the 3rd resistance R 3 two ends is:
The 9th FET M9 and the tenth FET M10 form current mirror, according to circuit working state, and ignore the inclined to one side effect of lining of FET, can obtain to the electric current that this charge and discharge capacitance C3 discharges and recharges being:
Therefore the clock frequency of the clock signal Fosc of this oscillator OSC output is:
Wherein,
is the half the of clock period; Temperature coefficient
can full remuneration through design; First resistance R 1, second resistance R 2 and the 3rd resistance R 3 are build-out resistor; The clock frequency of clock signal Fosc that therefore can draw oscillator OSC output by following formula is only with charge and discharge capacitance C3 is inversely proportional to and resistance has nothing to do.
Can be known that by above analysis oscillator OSC produces a clock signal Fosc and comes discharging and recharging of control capacitance C2, the frequency F of this clock signal Fosc is only relevant with charge and discharge capacitance C3, that is:
When clock signal Fosc was low level, the voltage buffer that the operational amplifier OP and the first FET M1 form charged to capacitor C 2 through the 4th FET M4; When clock signal Fosc is a high level, capacitor C 2 is discharged through the 5th FET M5, so the resistance Ron of equivalent resistance is by shown in the following formula:
; The reference current I that this shows reference current output terminal Iout output is relevant with the ratio of capacitor C 2 and charge and discharge capacitance C3; Irrelevant with resistance, promptly need not plug-in resistance.
Can draw by above analysis; The utility model reference current source circuit produces a frequency clock signal relevant with electric capacity through oscillator and comes discharging and recharging of control capacitance, produces reference current thereby obtain one equiva lent impedance relevant with capacitance ratio.
The reference current of the utility model reference current source circuit output is only relevant with capacitance ratio; And the precision of the ratio of electric capacity in semiconductor technology is higher than the precision of the absolute value of electric capacity or resistance far away; Therefore the utility model reference current source circuit need not produce reference current by plug-in resistance; Simple in structure, and reduced the cost of chip.
Claims (6)
1. reference current source circuit; It is characterized in that: said reference current source circuit comprises the reference current output terminal that current mirror module and that filter capacitor, that equivalent resistance, that voltage buffer, that a reference voltage generation module, links to each other with said reference voltage generation module links to each other with said voltage buffer links to each other with said voltage buffer links to each other with said voltage buffer links to each other with said current mirror module; Said voltage buffer comprises first FET that an operational amplifier and links to each other with said operational amplifier; Said current mirror module comprises the 3rd FET that one second FET and links to each other with said second FET; Said equivalent resistance comprises the electric capacity that the 5th FET and that the 4th FET, that an oscillator, links to each other with said oscillator links to each other with said oscillator links to each other with said the 4th FET and said the 5th FET; Said oscillator produces the relevant clock signal of a charge and discharge capacitance in a frequency and the said oscillator and controls discharging and recharging of electric capacity in the said equivalent resistance, and said reference current output terminal is exported a reference current relevant with the ratio of said electric capacity and said charge and discharge capacitance.
2. reference current source circuit as claimed in claim 1; It is characterized in that: said reference voltage generation module links to each other with a normal phase input end of said operational amplifier; One inverting input of said operational amplifier links to each other with the source class of the source class of said first FET, said the 4th FET and an end of said filter capacitor, and an output terminal of said operational amplifier links to each other with the grid of said first FET.
3. reference current source circuit as claimed in claim 2; It is characterized in that: the grid of the drain electrode of said first FET, said second FET links to each other with the grid of drain electrode with said the 3rd FET; The drain electrode of said the 3rd FET links to each other with said reference current output terminal, and the source class of said second FET is connected a power end jointly with the source class of said the 3rd FET.
4. reference current source circuit as claimed in claim 3; It is characterized in that: the grid of said the 4th FET is connected said oscillator jointly with the grid of said the 5th FET; The drain electrode of said the 4th FET links to each other with the drain electrode of said the 5th FET and an end of said electric capacity, the common earth terminal that connects of the other end of the source class of said the 5th FET, the other end of said electric capacity and said filter capacitor.
5. reference current source circuit as claimed in claim 1 is characterized in that: said oscillator also comprises the 14 FET that the 13 FET, that the 12 FET, that the 11 FET, that the tenth FET, that the 9th FET, that the 8th FET, that the 7th FET, that one the 6th FET, links to each other with said the 6th FET links to each other with said the 6th FET and said the 7th FET links to each other with said the 8th FET links to each other with said the 9th FET links to each other with said the 9th FET and said the tenth FET links to each other with said the 11 FET links to each other with said the 6th FET links to each other with said the 13 FET.
6. reference current source circuit as claimed in claim 5 is characterized in that: said oscillator comprises that also first resistance, one that the 21 FET, that the 20 FET, that the 19 FET, that the 18 FET, that the 17 FET, that the 16 FET, that 1 the 15 FET, links to each other with said the 9th FET links to each other with said the 16 FET links to each other with said the 12 FET links to each other with said the 18 FET links to each other with said the 11 FET links to each other with said the 20 FET links to each other with said the 13 FET is connected in the rest-set flip-flop that second comparer and that first comparer, that the 3rd resistance, one that second resistance, one between said the 8th FET and said the 15 FET links to each other with said the 16 FET links to each other with said second resistance links to each other with said first comparer links to each other with several first comparers and said second comparer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204275611U CN202306376U (en) | 2011-11-02 | 2011-11-02 | Reference current source circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011204275611U CN202306376U (en) | 2011-11-02 | 2011-11-02 | Reference current source circuit |
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| CN202306376U true CN202306376U (en) | 2012-07-04 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102411393A (en) * | 2011-11-02 | 2012-04-11 | 四川和芯微电子股份有限公司 | Reference current source circuit and system |
| CN103825556A (en) * | 2014-03-05 | 2014-05-28 | 上海华虹宏力半导体制造有限公司 | Oscillating circuit |
| CN114924604A (en) * | 2022-03-29 | 2022-08-19 | 南方科技大学 | Voltage reference circuit, power supply and electronic equipment |
-
2011
- 2011-11-02 CN CN2011204275611U patent/CN202306376U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102411393A (en) * | 2011-11-02 | 2012-04-11 | 四川和芯微电子股份有限公司 | Reference current source circuit and system |
| CN102411393B (en) * | 2011-11-02 | 2013-10-02 | 四川和芯微电子股份有限公司 | Reference current source circuit and system |
| CN103825556A (en) * | 2014-03-05 | 2014-05-28 | 上海华虹宏力半导体制造有限公司 | Oscillating circuit |
| CN103825556B (en) * | 2014-03-05 | 2017-01-11 | 上海华虹宏力半导体制造有限公司 | Oscillating circuit |
| CN114924604A (en) * | 2022-03-29 | 2022-08-19 | 南方科技大学 | Voltage reference circuit, power supply and electronic equipment |
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Address after: 610041 Sichuan city of Chengdu province high tech Zone Kyrgyzstan Road 33 block A No. 9 Patentee after: IPGoal Microelectronics (Sichuan) Co., Ltd. Address before: 402 room 7, building 610041, incubator Park, hi tech Zone, Sichuan, Chengdu Patentee before: IPGoal Microelectronics (Sichuan) Co., Ltd. |
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Granted publication date: 20120704 Termination date: 20141102 |
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